ee2 chapter12 flip_flop

Apr 11, 2023

Lecturer Name [email protected]

Contact Number

IT2001PAEngineering Essentials (2/2)

Chapter 12 - Flip Flop

2


IT2001PA Engineering Essentials (2/2)

Lesson Objectives

Upon completion of this topic, you should be able to: Determine the operations of various types of flip-flops

in digital circuits (e.g. JK flip-flop).



Specific Objectives

Students should be able to : Draw the symbol of a JK flip-flop. Explain the characteristics of a JK flip flop with the aid of a

truth table. Differentiate between edge and level triggered flip flops. Draw the symbols of :

D type flip flop JK flip flop and T flip flop



Specific Objectives

Students should be able to : Describe with the aid of truth tables the operation of the following flip

flops : D type flip flop JK flip flop T flip flop

Draw the output waveforms of the following flip flops, for a given clock and control input waveforms: D type flip flop JK flip flop T flip flop



Specific Objectives

Students should be able to : Explain the following terms :

Prohibited state Indeterminate state Synchronous and Asynchronous

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Introduction

Flip-flop is digital circuit which functions as a memory element used in the digital system.

Flip-Flop is made up of an assembly of logic gates. Even though a logic gate, by itself, has no storage capability.

Flip-Flop is also known as latch and bi-stable multi-vibrator.

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General Flip-flop Symbol

The symbol shows two outputs, labeled Q and Q, that are the inverse of each other

The FF can has one or more inputs. These inputs are used to cause the FF to switch back and forth between its possible output states

Q

Q

FFinputs

outputs

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General Flip-flop Symbol

Flip-Flop has two allowed output states.

SET state :-

where Q = 1and Q = 0.

RESET state :-

where Q = 0 and Q = 1.

Thus, flip-flop is also known as bi-stable multi-vibrator or latch.

Q

Q

FFinputs

outputs

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Various Types of Flip-Flops

Unclocked RS flip-flop or latch

Clocked RS flip-flop or gated RS flip-flop

JK flip-flop

D-type latch

D-flip-flop

T-flip-flop

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Advantage of JK Flip-Flop

Does not have the problem of a

prohibited input combinations

May be edge-triggered or level-triggered

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Positive edge-triggered

Q

Q

CLK

J

KFF triggers on positive transition

Symbol

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Negative edge-triggered

Q

Q

CLK

J

KFF triggers on negative transition

Symbol

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Q

Q

S

R

Logic circuit

J

K

CLK

Q

Q

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Truth Table

Q Remark QO No change

1 Q = J when J = K

0 Q = J when J = K

QO Toggle state

CLK

K 0

0

1

1

J 0

1

0

1

15




Timing diagram1

01

0

1

0

1

0Q

CLK

K

J

a b c d e f g h i j k

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Operates in the same manner as the positive edge-triggered except that

output changes states only on the negative edge of the clock signal.

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Timing diagram1

01

0

1

0

1

0Q

CLK

K

J

a b c d e f g h i j k

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D Flip-Flops

The D flip-flop is also called Delay or Data flip-flop.

The D flip-flop has only one input.

It can be easily implemented from the RS or JK inputs as shown.

Q

Q

S

R

D

Q

Q

J

K

D

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D Flip-Flops

Edge-triggered D FF

Truth table

Q follows D on the rising edge of the clock pulse.

Q

Q

D

CLK

D Clk Q

0 0 1 1

X 0 no change

“ X ” indicates “don’t care”

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D Flip-Flops

D

Clk

Q

Initaily Q = 1D =1, Clk = and Q = 1

Waveform diagram for a D flip-flop

Q

Q

D

CLK

D = 0, Clk = and Q = 0D = 0, Clk = and Q = 0D = 1, Clk = and Q = 1

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D Flip-Flops

Level-triggered D FF

Truth table

Q follows D when the FF is enabled; i.e. when EN = 1

Q

Q

D

EN

D EN Q

X 0 no change

1 1 1

0 1 0

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D Flip-Flops

Waveform diagram for a D flip-flop

Q

Q

D

EN

D

EN

Q

Both D and EN inputs are 0, and Q = 0

D =1, EN = 0 and Q = 0D =1, EN = 1 and Q = 1D =0, EN = 1 and Q = 0D = 1, EN = 1 and Q = 1D = 0, EN = 0 and Q = 1

“Latched” “Transparent”

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Implementation of the D FF

From the clocked RS FF by

• connecting an INVERTER to the inputs

Q

Q

CLK

S

R

D

CLK

Q

Q

CLK

D

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Implementation of the D FF

From the clocked JK FF by

• connecting an INVERTER to the inputs

Q

Q

CLK

J

K

D

CLK

Q

Q

CLK

D

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Asynchronous Inputs

S R Q Q Remark 0 0 1 1 Prohibited state

0 1 1 0 Set state, Q =1

1 0 0 1 Reset state, Q = 0

1 1 0 1 No change or Hold

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Symbol

Q

Q

FF

S

R

SET

RESET

INPUTS ACTIVE HIGH

Normal

Complementary

SET input set Q-output with a binary ‘1’.

RESET input reset Q-output with a binary ‘0’.

OUTPUTS

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Advantages of synchronous over asynchronous operation

FF outputs change in orderly manner.

Everything in the system happens at the same time.

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Asynchronous Inputs

Preset & Clear inputs

• not triggered by clock pulses.Q

Q

CLK

J

K

PRE

CLR

+5V

Symbol

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Asynchronous Inputs

Preset Clear FF response 1 1

Normal clocked operation. Q will respond to J,K & CLK

0 1 Preset state, Q =1

1 0 Clear state, Q = 0

0 0 Prohibited

Truth Table

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Timing diagram

1CLK

0

1J,K

1

01

01

0a b c d e f g

PRE

CLR

Q

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Operation

Point Operationa

b

c

d

e

f

g

Synchronous toggle on NGT of CLK

Asynchronous set on PRE = 0

Synchronous toggle

Synchronous toggle

Asynchronous clear on CLR = 0

CLR over-rides the NGT of CLK

Synchronous toggle

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T Flip-Flops

The T flip-flop is also called toggle flip-flop. Q

Q

J

T

K

Q

Q

T

Q

Q

J

T

K

Q

Q

J

CLK

K

HighIt can be easily implemented by tying the JK inputs of the JK FF to high as shown.

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T Flip-Flops

Q

Q

T

Truth table

Qn Clk Qn+1

1 1 1 0

0 1

0 0

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T Flip-Flops

Q

Q

T

Wave format T input

Wave form at Q output

fo = 1/2 fin

fo : Output frequency at Qfin : Input frequency at T

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ee2 chapter12 flip_flop

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