ee241 final project high speed sense amplifier with offset compensation for srams yida duan
Post on 15-Jan-2016
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![Page 1: EE241 Final Project High Speed Sense Amplifier With Offset compensation for SRAMs Yida Duan](https://reader035.vdocuments.net/reader035/viewer/2022062804/56649d605503460f94a40c64/html5/thumbnails/1.jpg)
EE241 Final ProjectHigh Speed Sense Amplifier With Offset
compensation for SRAMs
Yida Duan
![Page 2: EE241 Final Project High Speed Sense Amplifier With Offset compensation for SRAMs Yida Duan](https://reader035.vdocuments.net/reader035/viewer/2022062804/56649d605503460f94a40c64/html5/thumbnails/2.jpg)
Motivation & Proposed Solution
• Time Margin needed for input to grow > offset• Response Time = Time Margin + Sense Time• Time Margin is large for large offset (offset compensation)
Problem (Offset)
Solution (offset Compensation)
Ysel
CBLCBLb
1u 1u
M260n
M160n
M3120n
M4120n
M71u
M5120n
M6120nYsel
resetb
Vdd
resetreset
4fF
4fF
120n
90n
90n
120n
90n
90n
Outn Outp
Iin
inninp
![Page 3: EE241 Final Project High Speed Sense Amplifier With Offset compensation for SRAMs Yida Duan](https://reader035.vdocuments.net/reader035/viewer/2022062804/56649d605503460f94a40c64/html5/thumbnails/3.jpg)
Basis of ComparisonVdd
Vdd
SAEN
Ysel Ysel
CBLCBLb
M8120n
M7120n
M6120n
M3120n
M4120n
1u 1u
M160n
M260n
M5200n
Ysel
120n
60n
120n
60n
OutpOutn
In-In+
Iin
Ysel
CBLCBLb
1u 1u
M260n
M160n
M3120n
M4120n
M71u
M5120n
M6120n
120n60n
Ysel
reset
resetb
resetb
Vdd
120n120n
90n90n
90n 90n
resetb resetb
Outn Outp
M8
M9
In+ In-
Iin
Ysel
CBLCBLb
1u 1u
M260n
M160n
M3120n
M4120n
M71u
M5120n
M6120nYsel
resetb
Vdd
resetreset
4fF
4fF
120n
90n
90n
120n
90n
90n
Outn Outp
Iin
inninp
Vdd
M9120n
M2120n
M460n
M160n
M360n
M6120n
M760n1u
M51u
M860n
CBL
Reset
ResetBResetB Reset
ResetB
ResetB
ResetB
M12120n
M1190n
M1090n
Out
4fF4fF X Y
Iin
(a) Conventional Voltage Sense amp (VSA)
(b) Clamped-bitline current sense amp (CSA)
(c) Offset-compensated current sense amp (OCCSA)
(d) Non-strobed regenerative voltage sense amp (NSR-VSA)
![Page 4: EE241 Final Project High Speed Sense Amplifier With Offset compensation for SRAMs Yida Duan](https://reader035.vdocuments.net/reader035/viewer/2022062804/56649d605503460f94a40c64/html5/thumbnails/4.jpg)
Conventional Voltage Sense AmplifierVdd
Vdd
SAEN
Ysel Ysel
CBLCBLb
M8120n
M7120n
M6120n
M3120n
M4120n
1u 1u
M160n
M260n
M5200n
Ysel
120n
60n
120n
60n
OutpOutn
In-In+
Iin
Vdd
Vdd
SAEN
Ysel Ysel
CBLCBLb
M8120n
M7120n
M6120n
M3120n
M4120n
1u 1u
M160n
M260n
M5200n
Ysel
120n
60n
120n
60n
OutpOutn
In-In+
Iin
Reset Phase
Sense Phase
Good:• No Reset Power
Bad:• Complete bitline discharge• Large Sense Time (Bitline loading)• Large Offset
![Page 5: EE241 Final Project High Speed Sense Amplifier With Offset compensation for SRAMs Yida Duan](https://reader035.vdocuments.net/reader035/viewer/2022062804/56649d605503460f94a40c64/html5/thumbnails/5.jpg)
Clamped-bitline Current Sense AmpReset Phase
Sense Phase
![Page 6: EE241 Final Project High Speed Sense Amplifier With Offset compensation for SRAMs Yida Duan](https://reader035.vdocuments.net/reader035/viewer/2022062804/56649d605503460f94a40c64/html5/thumbnails/6.jpg)
Clamped-bitline Current Sense AmpBetween the 2 phases
CBLRM
tin
M eI
I 727 12
• IM7 > Ios prior to regeneration
• IM7 saturates at Iin/2 for large Time Margin
• M7 in linear region, RM7 is small
IM7
![Page 7: EE241 Final Project High Speed Sense Amplifier With Offset compensation for SRAMs Yida Duan](https://reader035.vdocuments.net/reader035/viewer/2022062804/56649d605503460f94a40c64/html5/thumbnails/7.jpg)
Clamped-bitline Current Sense Amp – Offset Calculation
23
21
2MMos III
Assume ,317 , MMM RRR
• To convert Ios to Vos, Vos=RM7Ios
• Offset is mainly due to M1—M4
333
33
11
11
|)|(
)(
dstpgsM
sattngsM
VVVL
WKI
VVVL
WKI
)()(
)()(
33
33
1
11
tpdsM
tnsatM
VVL
WKI
VVL
WKI
)()( 31 MM II Because 3dssat VV
![Page 8: EE241 Final Project High Speed Sense Amplifier With Offset compensation for SRAMs Yida Duan](https://reader035.vdocuments.net/reader035/viewer/2022062804/56649d605503460f94a40c64/html5/thumbnails/8.jpg)
Clamped-bitline Current Sense Amp
Good:• Bitline clamped to a high voltage after sense phase• Small Sense time (No bitline loading)
Bad:• Reset power• large offset, need Time Margin• Will not work if Iin < Ioffset
![Page 9: EE241 Final Project High Speed Sense Amplifier With Offset compensation for SRAMs Yida Duan](https://reader035.vdocuments.net/reader035/viewer/2022062804/56649d605503460f94a40c64/html5/thumbnails/9.jpg)
Ysel
CBLCBLb
1u 1u
M260n
M160n
M3120n
M4120n
M71u
M5120n
M6120nYsel
resetb
Vdd
resetreset
4fF
4fF
120n
90n
90n
120n
90n
90n
Outn Outp
Iin
inninp
• Same Operation as clamped bit line current sense amplifier• Virtually no offset (any offset is sampled on 4fF caps)
Offset-Compensated Clamped-bitline Current Sense Amplifier
![Page 10: EE241 Final Project High Speed Sense Amplifier With Offset compensation for SRAMs Yida Duan](https://reader035.vdocuments.net/reader035/viewer/2022062804/56649d605503460f94a40c64/html5/thumbnails/10.jpg)
Non-strobed Regenerative Voltage Sense Amplifier
Reset Phase
Sense PhaseGood:• No bitline loading• No Time Margin
Bad:• Reset power• Larger area• Compromise robustness
![Page 11: EE241 Final Project High Speed Sense Amplifier With Offset compensation for SRAMs Yida Duan](https://reader035.vdocuments.net/reader035/viewer/2022062804/56649d605503460f94a40c64/html5/thumbnails/11.jpg)
Simulation Results – Sense Time
![Page 12: EE241 Final Project High Speed Sense Amplifier With Offset compensation for SRAMs Yida Duan](https://reader035.vdocuments.net/reader035/viewer/2022062804/56649d605503460f94a40c64/html5/thumbnails/12.jpg)
Simulation Results - Offset
-0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.080
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Voffset (V)P
roba
bilit
y
Input-referred Offset Probability Obtained From 100-pt Monte Carlo Simulation
NSRVSA
VSACSA
OCCSA
Avg=992.9mVσ=46.2mV
VSA NSR-VSA CSA OCCSA
47mV 8.1mV 15.8mV 1.5mV2OSV
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Simulation Results - Yield
-20 0 20 40 60 80 100
30
40
50
60
70
80
90
100
Strobe (SAEN) Signal Delay vs. Yield
Strobe (SAEN) Signal Delay (ps)%
Yie
ld
CSA
OCCSAVSA
0 500 1000 1500 200020
30
40
50
60
70
80
90
100
Strobe (SAEN) Signal Delay vs. Yield
Strobe (SAEN) Signal Delay (ps)
% Y
ield
CSA
OCCSAVSA
![Page 14: EE241 Final Project High Speed Sense Amplifier With Offset compensation for SRAMs Yida Duan](https://reader035.vdocuments.net/reader035/viewer/2022062804/56649d605503460f94a40c64/html5/thumbnails/14.jpg)
Simulation Results – Response Time
Mean (ps)
STD (ps)
Total Response Time (3σ Yield)
NSR-VSA 120.7 4.5 134.2
OCCSA 57.5 1.4 61.7
50 60 70 80 90 100 110 120 1300
5
10
15
20
25
30
35
Response Time (ps)
Num
ber
of S
ampl
es
OCCSA
NSR-VSA
Avg=57.5psσ=1.5ps
Avg=120psσ=4.5ps
![Page 15: EE241 Final Project High Speed Sense Amplifier With Offset compensation for SRAMs Yida Duan](https://reader035.vdocuments.net/reader035/viewer/2022062804/56649d605503460f94a40c64/html5/thumbnails/15.jpg)
Conclusion & Performance Summary
Sense Amp Total Reponse Time(ps)
Reset Power(uW)
Area (um2)
VSA > 2000 0.13 0.052CSA ---- 36.1 0.107
NSR-VSA 134.2 48.9 0.451OCCSA 61.7 36.1 0.473
• OCCSA is 30X faster than VSA, 2X faster than NSR-VSA• OCCSA has comparable reset power with NSR-VSA• OCCSA has comparable area with NSR-VSA
Note: Time Margin Uncertainty is not considered