ee241 - spring 2002bwrcs.eecs.berkeley.edu/classes/icdesign/ee241_s02/lectures/lecture1... · 8085...

EE241

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UC Berkeley EE241 B. Nikolic

EE241 - Spring 2002Advanced Digital Integrated Circuits

Tu-Th 11 – 12:30pm203 McLaughlin


Practical Informationl Instructor: Borivoje Nikolic

570 Cory Hall , 3-9297, [email protected] hours: M 11am-12pm, Tu 12:30-1:30pm

l Reader: TBA

l Admin: Lea Barker558 Cory Hall, 3-6683, leab@eecs

l Class Web pagehttp://bwrc.eecs.berkeley.edu/classes/icdesign/ee241_s02

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Class Organizationl +/- 5 assignmentsl 1 term-long design project

» Phase 1: Proposal (by week 3)» Phase 2: Study (report by week 7)» Phase 3: Design (presentation and report

by final week)» Report and presentations last week of

classes

l Final exam


Class Material

l Textbook: “Design of High-Performance Microprocessor Circuits,” edited by A.Chandrakasan, W. Bowhill, F. Fox

l Must be familiar with “Digital Integrated Circuits - A Design Perspective”, 2nd ed. by J. M. Rabaey, A. Chandrakasan, B. Nikolic

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Other Booksl Other reference books:

» “High-Speed CMOS Design Styles, by K. Bernstein, et al.

» “Digital Systems Engineering” by W. Dally» “High-Performance System Design: Circuits and

Logic,” by V.G. Oklobdžija» “Low-Power CMOS Design,” by Chandrakasan

and Brodersen» “High-Speed Digital System Design,” by S.H. Hall,

G.W. Hall, J. A. McCall» “Logical Effort: Designing Fast CMOS Circuits,” by

I. Sutherland, B. Sproull, D. Harris


Class Materiall List of background material available on

web-sitel Selected papers will be made available

on web-site» Protected area, or linked from Inspec

l Papers on http://www.melvyl.ucop.edul Class-notes on web-site

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Sourcesl IEEE Journal of Solid-State Circuits

(JSSC)l IEEE International Solid-State Circuits

Conference (ISSCC)l Symposium on VLSI Circuits (VLSI)l Other conferences and journals


Lecture Videosl Lectures are videotapedl Use the microphones when you ask

questions

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Class Topicsl This course aims to convey a knowledge of advanced concepts of

circuit design for digital LSI and VLSI components in state of the art MOS technologies. Emphasis is on the circuit design, and optimization of either very high speed, high density or low power circuits for use in applications such as micro-processors, signal and multimedia processors, communications, memory and periphery. Special attention will devoted to the most important challenges facing digital circuit designers today and in the coming decade, being the impact of scaling, deep sub-micron effects, interconnect, signal integrity, power distribution and consumption, and timing.

l SPECIAL FOCUS in SPRING 2002:» Low-power and ‘lower-power’ design» high-performance logic» interconnect» timing» arithmetic circuits» memory


Class Topics

l Fundamentals - Technology and modeling – Scaling and limits of scaling (1.5 weeks)

l Design for deep-submicron CMOS - HIGH SPEED (2.5 weeks)» Static CMOS, transistor sizing, buffer design, high-speed CMOS design styles,

dynamic logic

l Design techniques for LOW POWER (2.5 weeks) » analysis of power consumption sources » power minimization at the technology, circuit, and architecture level

l Arithmetic circuits – adders, multipliers (2 weeks) l Driving interconnect, high-speed signaling (2 weeks) l Timing (2 weeks)

» Timing analysis, flip-flop/latch design, clock skew, clocking strategies, self-timed design, clock generation and distribution, phase-locked loops

l Memory design (2 week)l Design for test (0.5 weeks)

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Project Topicsl High-performance low-power logic l Leakage suppressionl Low voltage designl Circuit optimization techniquesl Interconnect in deep-submicronl Arithmetic circuitsl High-speed communicationl Timing of gigascale circuitsl Flip-flops/latchesl Memory circuitsl Other important circuit topics


Suggested Readingl Chapter 1 – Impact of physical technology on architecture (J.H.

Edmondson),l Chapter 2 – CMOS scaling and issues in sub-0.25µm systems

(Y. Taur)l Technology roadmap (http://public.itrs.net) - and try find some

contradictionsl Selected papers from the web:

» S. Borkar, “Design challenges of technology scaling,” IEEE Micro, vol.19, no.4, p.23-29, July-Aug. 1999.

» J. Meindl, “Low Power Microelectronics: Retrospect and Prospect”, Proceedings of the IEEE, April 1995.

» B. Davari et al., “CMOS Scaling for High Performance and Low Power - The Next Ten Years,” Proceedings of the IEEE, April 1995.

» A. Masaki, “Deep-Submicron warms up to High Speed Logic,” IEEECicuits and Devices Magazine, November 1992.

l This lecture is based on IC seminar by S. Borkar, October 2000. also ISSCC’01 plenary talk by P. Gelsinger.

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Toolsl HSPICE

» You need an account on cory.eecs

l 0.18µm CMOS device models (TSMC/MOSIS)

l Other tools, schematic or layout editors are optional

l Cadence, Synopsys, available on mingus.eecs


Moore’s Law

lIn 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.

lHe made a prediction that semiconductor technology will double its effectiveness every 18 months

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Moore’s Law16151413121110

9876543210

1959

1960

1961

1962

1963

1964

1965

1966

1967

1968

1969

1970

1971

1972

1973

1974

1975

LO

G2

OF

TH

E N

UM

BE

R O

FC

OM

PO

NE

NT

S P

ER

INT

EG

RA

TE

D F

UN

CT

ION

Electronics, April 19, 1965.


Transistor Count

1,000,000

100,000

10,000

1,000

10

100

11975 1980 1985 1990 1995 2000 2005 2010

8086

80286i386

i486Pentium®

Pentium® Pro

K1 Billion 1 Billion

TransistorsTransistors

Source: IntelSource: Intel

ProjectedProjected

Pentium® IIPentium® III

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Technology Evolution (1997 data)

International Technology Roadmap for Semiconductors

17000100006000350021001250750Max frequency [MHz],Local

1831751701601309070Max µP power [W]

1098-97-876-76Metal layers

0.40.5-0.6

0.6-0.90.9-1.2

1.2-1.5

1.5-1.8

1.8-2.5

Supply [V]

25355070100140200Channel length [nm]

2014201120082005200219991997Year of Introduction

http://www.sematech.org, or http://public.itrs.net


Technology Evolution (2000 data)International Technology Roadmap for Semiconductors

18617717116013010690Max µP power [W]

1.4

1.2

6-7

1.5-1.8

180

1999

1.7

1.6-1.4

6-7

1.5-1.8

2000

14.9-3.6

11-37.1-2.53.5-22.1-1.6Max frequency [GHz],Local-Global

2.52.32.12.42.0Bat. power [W]

109-10987Wiring levels

0.3-0.60.5-0.60.6-0.90.9-1.21.2-1.5Supply [V]

30406090130Technology node [nm]

20142011200820042001Year of Introduction

Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm

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ITRS Technology Roadmap Acceleration Continues


Some Other Scares

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Productivity Trends

1

10

100

1,000

10,000

100,000

1,000,000

10,000,000

2003

1981

1983

1985

1987

1989

1991

1993

1995

1997

1999

2001

2005

2007

2009

10

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

Logic Tr./ChipTr./Staff Month.

xxx

xxx

x

21%/Yr. compoundProductivity growth rate

x

58%/Yr. compoundedComplexity growth rate

10,000

1,000

100

10

1

0.1

0.01

0.001

Lo

gic

Tra

nsi

sto

r p

er C

hip

(M)

0.01

0.1

1

10

100

1,000

10,000

100,000

Pro

du

ctiv

ity

(K)

Tra

ns.

/Sta

ff -

Mo

.

Source: Sematech

Complexity outpaces design productivity

Co

mp

lexi

ty


Some Recent DevicesIntel’s 30nm transistor

Ion = 570µm/µmIoff = 60nA/ µm

[B. Doyle]

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More Recent DevicesIntel’s 20nm transistor

[B. Doyle]

@0.75V


More Recent Devices

SOI: Silicon-on-InsulatorUltra-Thin-Body (UTB) MOSFET

[Choi, UCB]

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18nm FinFET

Double-gate structure + raised source/drain

BOX Si fin - Body!

DrainSource

Gate

X. Huang, et al, 1999 IEDM, p.67~70

Gate

Silicon Fin

0

50

100

150

200

250

300

350

400

-1.5 -1.0 -0.5 0.0Vd [V]

I d[u

A/u

m]

-1.50 V

-1.00 V

-0.75 V

-0.50 V

-0.25 V

-1.25 V


Goals of Technology Scalingl Design new devices to be:

» Faster?» Smaller?» Lower power?» Add new features?

l Bottom line:» Want to sell more functions (transistors) per chip

for the same money» Build same products cheaper, sell the same part

for less money» Price of a transistor has to be reduced

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Technology Scalingl Other benefits of scaling the dimensions by

30%:» Reduce gate delay by 30% (increase operating

frequency by 43%)» Double transistor density» Reduce energy per transition by 65% (50% power

savings @ 43% increase in frequencyl Technology generation spans 2-3 years, but

µP speed doubles every generation (not increased only by 43%)

S. Borkar, IEEE Micro, July 1999.


Moore’s law in Microprocessors

40048008

80808085 8086

286386

486Pentium® proc

P6

0.001

0.01

0.1

1

10

100

1000

1970 1980 1990 2000 2010Year

Tra

nsi

sto

rs (

MT

)

2X growth in 1.96 years!

Transistors on Lead Microprocessors double every 2 yearsTransistors on Lead Microprocessors double every 2 years

S. Borkar

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Moore’s Law - Logic Density

Shrinks and compactions meet density goalsNew micro-architectures drop density

Shrinks and compactions meet density goalsNew micro-architectures drop density

Sou

rce:

Inte

lPentium (R)Pentium Pro (R) 486

386

i860

1

10

100

1000

1.5µ

1.0µ

0.8µ

0.6µ

0.35

µ

0.25

µ

0.18

µ

0.13

µ

Lo

gic

Den

sity

2x trend

Lo

gic

Tra

nsi

sto

rs/m

m2

Pentium II (R)


Die Size Growth

40048008

80808085

8086286

386486Pentium ® proc

P6

1

10

100

1970 1980 1990 2000 2010Year

Die

siz

e (m

m)

~7% growth per year~2X growth in 10 years

Die size grows by 14% to satisfy Moore’s LawDie size grows by 14% to satisfy Moore’s Law

S. Borkar

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Frequency

P6Pentium ® proc

48638628680868085

8080800840040.1

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Fre

qu

ency

(M

hz)

Lead Microprocessors frequency doubles every 2 yearsLead Microprocessors frequency doubles every 2 years

Doubles every2 years

S. Borkar


Processor Frequency Trend

386486

Pentium(R)

Pentium Pro(R)

Pentium(R) II

MPC750604+604

601, 603

21264S

2126421164A

2116421064A

21066

10

100

1,000

10,000

1987

1989

1991

1993

1995

1997

1999

2001

2003

2005

Mh

z

1

10

100

Gat

e D

elay

s/ C

lock

Intel

IBM Power PC

DEC

Gate delays/clock

Processor freq scales by 2X per

generation

Frequency doubles each generationNumber of gates/clock reduce by 25%

V.De, S. BorkarISLPED’99

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Power

P6Pentium ® proc

486

3862868086

80858080

80084004

0.1

1

10

100

1971 1974 1978 1985 1992 2000Year

Po

wer

(W

atts

)

Lead Microprocessors power continues to increaseLead Microprocessors power continues to increase

S. Borkar


Obeying Moore’s Law…

40048008

80808085 8086

286386

486Pentium ® procP6

0.001

0.01

0.1

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Tra

nsi

sto

rs (

MT

) 900M

1.8B

425M200M

200M--1.8B transistors on the Lead Microprocessor200M--1.8B transistors on the Lead Microprocessor

S. Borkar

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If die size increases

P6Pentium ® proc486

386286

80868085

8080

80084004

1

10

100

1970 1980 1990 2000 2010Year

Die

siz

e (m

m)

~7% growth per year~2X growth in 10 years

41363228

Die size will have to grow to 30 - 40mmDie size will have to grow to 30 - 40mm

S. Borkar


Frequency will increase

P6Pentium ® proc

48638628680868085

8080800840040.1

1

10

100

1000

10000

100000

1970 1980 1990 2000 2010Year

Fre

qu

ency

(M

hz)

30GHz

14GHz6.5GHz

3 Ghz

3 - 30Ghz Frequency3 - 30Ghz Frequency

S. Borkar

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Supply voltage will continue to reduce

0.10

1.00

10.00

1970 1980 1990 2000 2010Year

Su

pp

ly V

olt

age

(V)

Only 15% Vcc reduction to meet frequency demandOnly 15% Vcc reduction to meet frequency demand

S. Borkar


Processor Power

386386

486 486

Pentium(R)Pentium(R)

MMX

Pentium Pro (R)

Pentium II (R)

1

10

100

1.5µ 1µ 0.8µ 0.6µ 0.35µ 0.25µ 0.18µ 0.13µ

Max

Po

wer

(W

atts

) ?

Lead processor power increases every generation

Compactions provide higher performance at lower power

Sou

rce:

Inte

l

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Active power scaling1

3.1)7.0

1()7.0()14.1

7.01

(fCVPower

),7.0

(Freqand,7.0VccIf.1

222 =×××==

==

8.1)2()7.0()14.17.0

1(fCVPower

,2Freqand,7.0VccIf.2

222 =×××==

==

7.2)2()85.0()14.17.0

1(fCVPower

,2Freqand,85.0VccIf.3

222 =×××==

==


Leakage power increases

10

100

1,000

10,000

100,000

30 40 50 60 70 80 90 100

Temp (C)

Ioff

(na/

u)

0.18u 0.13u 0.1u0.07u 0.05u

8KW

1.7KW

400W

88W 12W

0%

10%

20%

30%

40%

50%

2000 2002 2004 2006 2008Year

Dra

in L

eaka

ge

Po

wer

Drain leakage will have to increase to meet freq demandResults in excessive leakage power

Drain leakage will have to increase to meet freq demandResults in excessive leakage power

S. Borkar

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Power will be a problem

5KW 18KW

1.5KW 500W

40048008

80808085

8086286

386486

Pentium® proc

0.1

1

10

100

1000

10000

100000

1971 1974 1978 1985 1992 2000 2004 2008Year

Po

wer

(W

atts

)

Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitive

S. Borkar


A closer look at the power

18KW

5KW

1.5KW

500W 623W375W

225W135W

100

1,000

10,000

100,000

2002 2004 2006 2008Year

Po

wer

(W

atts

)

Will be...

Should be...

S. Borkar

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Power density will increase

400480088080

8085

8086

286 386486

Pentium® procP6

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Po

wer

Den

sity

(W

/cm

2)

Hot Plate

Nuclear Reactor

Rocket Nozzle

Power density too high to keep junctions at low tempPower density too high to keep junctions at low temp

S. Borkar

Sun’s Surface


Power delivery challenges

P6Pentium® proc

486386286

8086

80858080

800840040.01

0.10

1.00

10.00

100.00

1,000.00

1970 1980 1990 2000 2010Year

Icc

(am

p)

P6Pentium® proc

486386

286

8086

80858080

80084004

1.E-041.E-031.E-021.E-011.E+001.E+011.E+021.E+031.E+041.E+051.E+061.E+07

1970 1980 1990 2000 2010Year

L(d

i/dt)

/Vd

d

High supply currents at low voltage:Challenges: IR drop and L(di/dt) noiseHigh supply currents at low voltage:

Challenges: IR drop and L(di/dt) noise

S. Borkar

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20nm Power Densityl With Vdd ~1.2V, 20nm devices are quite fast. FO4

delay is <5psl If we continue with today’s architectures, we could

run digital circuits at 30GHz

l But - we will end up with 20kW/cm2 power density.

l Lower supply – to 0.6V, we are down to 5kW/cm2.

l Speeds will be a bit lower, too, FO4 = 10ps, lowering the frequencies to ~10GHz [Tang, ISSCC’01], and lowering power

l Assume that a high performance DG or bulk FET can be designed with 1kW/cm2, with FO4 = 10ps [Frank, Proc IEEE, 3/01]


Power is a Limiting Factorl If we have 2cm x 2cm die in a high-performance

microprocessor, we will end up with 4kW power dissipation.

l If our power has to be limited to 180W, we can afford to have only 4.5% of these devices with 0.6V supply on the die, given that nothing else dissipates power.

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Possible Scenariol Example: 0.5 % of devices will be of highest

performancel 35% is leakage (assume: 20% drain, 10% gate, 5%

drain-to-body)l 65% is active power, if just 0.5% of these CV2 = 13W,

leakage 7Wl How would other 99.5% devices that populate the

2cmx2cm die look like?


Do not increase the die size

0

5

10

15

2025

30

35

40

45

2000 2002 2004 2006 2008Year

Die

Siz

e (m

m)

Will be...

Reduce die size

Restrict die size to ~ 20 mmRestrict die size to ~ 20 mm

S. Borkar

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Restrict transistor leakage

7 GHz5.5 GHz

4 GHz2.5 Ghz

P6Pentium® proc

48638610

100

1000

10000

1985 1990 1995 2000 2005 2010Year

Fre

qu

ency

(M

hz)

Reduce leakage _ Frequency will not double every 2 yearsReduce leakage _ Frequency will not double every 2 years

S. Borkar


MicroprocessorsToday → 20nm

µPCore

2GHz

Cache

µPCore

Cache

DedicatedLogic

7-10 GHz

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Microprocessor Designl Core datapath will be running at 7 - 10GHzl Requires fast devices, low thresholds with 0.5-0.6V

suppliesl Lowest NMOS VTh ~ -0.1V to get swing in CMOS. l Assume threshold of 0 – 0.1V. The devices will be

very leaky, will use second threshold to control leakage power.

l With second threshold set to have 10x less leakage, 90% of devices off critical paths can be made high-threshold.

l Power limits the size of the µP core to 5-10% die (today’s transistor count, just shrunk), 30-50% of total power budget.


Add Dedicated Datapath

l Will run at 10x lower frequency, at 0.5-0.7 of the processor VDD= 0.25 - 0.35V

l Thresholds for critical paths VTh = 150mVl Need leakage power management – another threshold or

control of VT

Logic BlockFreq = 1Vdd = 1Throughput = 1Power = 1Area = 1 Pwr Den = 1

Vdd

Logic Block

Freq = 0.5Vdd = 0.5Throughput = 1Power = 0.25Area = 2Pwr Den = 0.125Leakage Curr. = 2

Vdd/2

Logic Block

l Can execute e.g. DIVX decoder, graphics

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180W Gives Us:

Power Area

µP Core

Dedicated datapath

Dedicated datapath

µP Core

Memory

Memory


Memoryl Density is the key requirementl Will occupy 70-80% of the diel Low leakagel Low activity – Inherently low active power, low power

density (at least 10x less than logic)l Need higher VTh ~ 0.5V, and higher supply 0.8-1V (?)

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Systems-on-a-ChipToday → 20nm

Radio(60GHz (?), CMOS ?)

25M transistors, 3MB embedded SRAMMIPS core @ 100MHz, DSP @ 144MHz7 PLLs, 12 ADC, DACs, 100 clocks, 1.4W

Broadcom set-top box

2W


Transistor Requirementsl Will need different kinds of transistors:

» Datapaths (speed, leakage)» Dedicated DSP (power, leakage)» Memory (density is main concern)» Analog (?)

l Power and leakage determine the size ratios between these blocks

l Number of different transistors types is determined by parameter spread

l Less devices could solve the problem, but, need control of the threshold (4th terminal), with strong transfer function.

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Other design challenges

P6Pentium® proc

486386

28680868085

80808008

40040.001

0.01

0.1

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Lo

gic

Tra

nsi

sto

rs (

MT

)

0

5

10

15

20

25

2000 2002 2004 2006 2008Year

Die

Siz

e (m

m) But core will reduce even further...

Die size will reduce...

l Modest increase in Logic transistors

l “Logic Core” size will decrease

l Tools/methodology for memories

l Interconnect RC may not be that big an issue


Digital Cellular Market(Phones Shipped)

1996 1997 1998 1999 2000

Units 48M 86M 162M 260M 435M Analog Baseband

Digital Baseband

(DSP + MCU)

PowerManagement

Small Signal RF

PowerRF

(data from Texas Instruments)(data from Texas Instruments)

How about low power devices?

CellPhone

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Shannon Beats Moore’s Law

1

10

100

1000

10000

100000

1000000

10000000

1980

1984

1988

1992

1996

2000

2004

2008

2012

2016

2020

Algorithmic Complexity(Shannon’s Law)

Battery Capacity

Source: Data compiled from multiple sources

1G

2G

3G Processor Performance (~Moore’s Law)


A Note on Device Variationsl Threshold separation has to be at least ~70mV (assuming S =

70mV/dec) to be effective in leakage suppressionl If separated too much (>150mV) cannot be used efficiently

(percentage of low VTh devices grows)l High temperature dependencyl Threshold control is criticall Note that dedicated signal processing will be operating under

very low overdrives = large delay dependency on Vth variationl Besides using process, will need to use feedback (substrate

biasing) to controll Hard to do in SOI (Need to have control feature in SOI)

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Device variationsl Random dopant fluctuationsl Feature size, oxide thickness variationsl Measurements of first silicons in 130nm show delay

variations of 5-10% in two identical neighboring paths.

l Variations on a small scale will limit the designsl On larger blocks can use feedback.

ee241 - spring 2002bwrcs.eecs.berkeley.edu/classes/icdesign/ee241_s02/lectures/lecture1... · 8085...

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