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EE241 Spring 2010EE241 - Spring 2010Advanced Digital Integrated Circuits
Lecture 19: Managing Leakage
Announcements
Homework #3 due April 8
Quiz #3 on April 13
Reading: Chapter 6, 8, 10, from Rabaey LPDE
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Outline
Last lectureDVS
Clock gating
This lectureLeakage reduction techniques
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Leakage ManagementLeakage Management
3
Power /Energy Optimization SpaceConstant Throughput/Latency Variable Throughput/Latency
Energy Design Time Sleep Mode Run TimeEnergy Design Time Sleep Mode Run Time
Active
Logic design
Scaled VDD
Trans. sizing
Multi-VDD
Clock gatingDFS, DVS
St k ff t
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Leakage
Stack effects
Trans sizing
Scaling VDD
+ Multi-VTh
Sleep T’s
Multi-VDD
Variable VTh
+ Input control
+ Variable VTh
Reducing Leakage
Using lower supply
Using higher thresholdsChannel doping
Body biasing
Reduces drive current
Using stack effectStacked devices
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Sleep transistors
Using longer transistorsIncrease in active power
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Power /Energy Optimization SpaceConstant Throughput/Latency Variable Throughput/Latency
Energy Design Time Sleep Mode Run TimeEnergy Design Time Sleep Mode Run Time
Active
Logic design
Scaled VDD
Trans. sizing
Multi-VDD
Clock gatingDFS, DVS
St k ff t
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Leakage
Stack effects
Trans sizing
Scaling VDD
+ Multi-VTh
Sleep T’s
Multi-VDD
Variable VTh
+ Input control
+ Variable VTh
Leakage vs. Supply
0.8
0.9
1
50
60
0 2
0.3
0.4
0.5
0.6
0.7
0.8
Del
ay
(nor
mal
ized
)
20
30
40
En
erg
y (n
orm
aliz
ed)
Switching power
Leakage power
Delay
3-10x
8
0
0.1
0.2
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
V DD [V]
0
10
5
Power /Energy Optimization SpaceConstant Throughput/Latency Variable Throughput/Latency
Energy Design Time Sleep Mode Run TimeEnergy Design Time Sleep Mode Run Time
Active
Logic design
Scaled VDD
Trans. sizing
Multi-VDD
Clock gatingDFS, DVS
St k ff t
9
Leakage
Stack effects
Trans sizing
Scaling VDD
+ Multi-VTh
Sleep T’s
Multi-VDD
Variable VTh
+ Input control
+ Variable VTh
Technology Options
Ion, HS, LP
Ioff,HP
Ioff,LP
Ig,HP
HP
LP (LOP)
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180 130 90 65 45
Technology [nm]
Ig,LP
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Using Multiple Thresholds
11Yano, SSTCW’00
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7
Power /Energy Optimization SpaceConstant Throughput/Latency Variable Throughput/Latency
Energy Design Time Sleep Mode Run TimeEnergy Design Time Sleep Mode Run Time
Active
Logic design
Scaled VDD
Trans. sizing
Multi-VDD
Clock gatingDFS, DVS
St k ff t
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Leakage
Stack effects
Trans sizing
Scaling VDD
+ Multi-VTh
Sleep T’s
Multi-VDD
Variable VTh
+ Input control
+ Variable VTh
Longer Channels
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7
8
nA
]
Leakage Current35%
•10% longer gates reduce leakage by 35%
0
1
2
3
4
5
0.1 0.15 0.2 0.25 0.3
Lea
kag
e C
urr
ent
[n
Switching energy10%
L
g y• Increases switching energy by 21% with W/L = const.
W/L = const.
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Gate Length [um]Lnom
•Attractive when don’t have to increase W (memory)•Doubling L reduces leakage by 3x (in 0.13um)•Much stronger effect in 45nm!•Effect improves with more aggressive devices
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Power /Energy Optimization SpaceConstant Throughput/Latency Variable Throughput/Latency
Energy Design Time Sleep Mode Run TimeEnergy Design Time Sleep Mode Run Time
Active
Logic design
Scaled VDD
Trans. sizing
Multi-VDD
Clock gatingDFS, DVS
St k ff t
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Leakage
Stack effects
Trans sizing
Scaling VDD
+ Multi-VTh
Sleep T’s
Multi-VDDVariable VTh
+ Input control
+ Variable VTh
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Stack Effect
Reduction (in 0.13μ):
17Narendra, ISLPED’01
Stack Forcing
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Tradeoffs:• W/2 – ¼ of drive current, same loading• 2W – 4x loading, same drive current
Narendra, ISLPED’01
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Power /Energy Optimization SpaceConstant Throughput/Latency Variable Throughput/Latency
Energy Design Time Sleep Mode Run TimeEnergy Design Time Sleep Mode Run Time
Active
Logic design
Scaled VDD
Trans. sizing
Multi-VDD
Clock gatingDFS, DVS
St k ff t
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Leakage
Stack effects
Trans sizing
Scaling VDD
+ Multi-VTh
Sleep T’s
Multi-VDD
Variable VTh
+ Input control
+ Variable VTh
Input Control
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May take many cycles to force the desired state in a block
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Power /Energy Optimization SpaceConstant Throughput/Latency Variable Throughput/Latency
Energy Design Time Sleep Mode Run TimeEnergy Design Time Sleep Mode Run Time
Active
Logic design
Scaled VDD
Trans. sizing
Multi-VDD
Clock gatingDFS, DVS
St k ff t
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Leakage
Stack effects
Trans sizing
Scaling VDD
+ Multi-VTh
Sleep T’s
Multi-VDD
Variable VTh
+ Input control
+ Variable VTh
Dynamic Sleep Transistor
VCCON: gate
Active modePMOS forward body bias
...
CC
Virtual VCC
ON: gateoverdrive
Noise on virtual supply
Dual-VT
core
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ON: gateoverdrive VSS
Virtual VSS
Courtesy of J. Tschanz, Intel (ISSCC’03)
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Dynamic Sleep Transistor
VCCOFF: gate
PMOS reverse body biasIdle mode
...
Virtual VCCunderdrive
Virtual supply collapse
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VSS
Virtual VSSOFF: gateunderdrive
Courtesy of J. Tschanz, Intel (ISSCC’03)
How to Size the Sleep Transistor?
Circuits in active mode see the sleep transistor as extra power line resistance
The wider the sleep transistor the betterThe wider the sleep transistor, the better
Wide sleep transistors cost areaMinimize the size of the sleep transistor for given ripple (e.g. 5%)
Need to find the worst case vectorSleep transistor is not for free – it will degrade the performance in active mode
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performance in active modeCharging and discharging the virtual rails costs energy
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Sleep Transistor
High-VTH transistor has to be very large for low resistancein linear region. gLow-VTH transistor needs much less areafor the same resistance.
25Courtesy: R. Krishnamurthy, Intel
Sleep Transistor Layout
ALUSleep
transistor cells
Area overhead
PMOS 6%
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PMOS 6%
NMOS 3%
Tschanz, ISSCC’03
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Sleep in Standard Cells
27Uvieghara, ISSCC’04
Sleep Transistor Grid
No sleep transistor PMOS & NMOSsleep transistors
Virtual VCC Virtual VSS
VCC M4VCC M4
sleep transistors
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VSSM4VSS
M4
M3 M3 M3 M3Tschanz, ISSCC’03
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Preserving State
Virtual supply collapse in sleep mode will cause the loss of state in registers
Putting the registers at nominal VDD would preserve the state
These registers leak
The second supply needs to be routed as well
Can lower VDD in sleep
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Some impact on robustness, noise and SEU immunity
State preservation and recovery
Register Design
SLEEP High VT
SLEEP High VT
SLEEP High VT
SLEEP High VT
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g T
CLK
High VT
[Mutoh95]
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Power /Energy Optimization SpaceConstant Throughput/Latency Variable Throughput/Latency
Energy Design Time Sleep Mode Run TimeEnergy Design Time Sleep Mode Run Time
Active
Logic design
Scaled VDD
Trans. sizing
Multi-VDD
Clock gatingDFS, DVS
St k ff t
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Leakage
Stack effects
Trans sizing
Scaling VDD
+ Multi-VTh
Sleep T’s
Multi-VDD
Variable VTh
+ Input control
+ Variable VTh
Shared-Well Dual Supply
wer
[mW
]
40
50
60
-42%
[pJ]
Room temp.
600
700
800
Single-supply
Dual supply
1.16GHz
VDDL=1.4VEnergy:-25.3%
In 180nm
VDDL [V]
Leak
age
Pow
0
10
20
30
40
1.0 1.2 1.4 1.6 1.8 2.0
VDDHDomain
VDDLDomain
VDDH
Ener
gy [
TCYCLE [ns]
200
300
400
500
0.6 0.8 1.0 1.2 1.4 1.6
pp y(VDDH=1.8V)Delay :+2.8%
VDDL=1.2VEnergy:-33.3% Delay :+8.3%
32VDDH circuit
VDDL
VSS
VDDL circuit
Shimazaki, ISSCC’03
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Power /Energy Optimization SpaceConstant Throughput/Latency Variable Throughput/Latency
Energy Design Time Sleep Mode Run TimeEnergy Design Time Sleep Mode Run Time
Active
Logic design
Scaled VDD
Trans. sizing
Multi-VDD
Clock gatingDFS, DVS
St k ff t
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Leakage
Stack effects
Trans sizing
Scaling VDD
+ Multi-VTh
Sleep T’s
Multi-VDD
Variable VTh
+ Input control
+ Variable VTh
Dynamic Body Bias
Similar concept to dynamic voltage scalingControl loop adjusts the substrate bias to meet the timingtiming
Can be used just as runtime/sleep
Limited range of threshold adjustments (<100mV)Limited leakage reduction (<10x)No delay penalty
C i d b f d bi
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Can increase speed by forward bias
Energy cost of charging/discharging the substrate capacitance(but doesn’t need a regulator)
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Dynamic Body Bias
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Dynamic Body Bias
450mVFBB
VCC
PMOSbody
PMOSForward body bias
Active mode
... ...
450mVFBB
VSS
body
NMOSbody
bias
NMOSbias
PMOSbodyVHIGH
Forward body bias (FBB)
Local VCC tracking
Idle mode
Dual-VT
core
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PMOSbias
... ...NMOS
bias
500mVRBB
500mVRBB
VCC
VSS
NMOSbody
VLOW
Reverse body bias (RBB)
Triple well needed
Tschanz, ISSCC’03
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Body Bias Layout
Sleep transistor LBGsALU core LBGs
ALUNumber of ALU core LBGs
30
Number of sleep transistor LBGs
10
PMOS device width 13mm
ALU
37
Area overhead 8%
Sleep transistor LBGs
ALU core LBGs
1
Leakage Power Savings vs. Decap
Virtual VCC1.32V, 75°Cwer
0 2
0.4
0.6
0.8
1.32V75°C
Overhead: charging &
Dual-VTcore
lized
leak
age
po
in id
le m
od
e
40%
Low-leakage 133nF decap on
virtual VCC
No decap on virtual VCC
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0
0.2
0.01 1 100 10000
Minimize capacitance on virtual VCC
g gdischarging of virtual VCC
capacitance
Idle time
10ns 1s 100s 10ms10sNo
rmal 90%
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Decoupling Capacitor Placement
Longertime
OxideleakageDual-VT
core
Reducedleakage
timeconstant
Dual-VTcore
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Decap on full supply Decap on virtual supply
Performance
Convergence time
Oxide leakage savings
20%
Total Active Power Savings(Fixed activity: = 0.05)
0.5 5 50 500 5000 50000
Number of consecutive active cycles (TON)
5%
10%
15%
20%
ota
l po
we
r sa
vin
gs
Body bias (1.28V): active: FBB, idle: ZBB
PMOS sleep transistor (1.32V)
otal
pow
er s
avin
gs Max 18%
Max 8%
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0%
5%
10 100 1000 10000 100000 1000000Number of idle cycles
To
Reference: 450mV FBB to core with clock gating, 1.28V, 4.05GHz, 75°C
Number of consecutive idle cycles (TOFF)
Power savings for TOFF > ~100 idle cycles
To
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Techniques Summary
80
100
Standby supply reduction3 4 l k d ti
Reduced VDD
20
40
60
Il ea
k(n
orm
aliz
ed
)
Sleep transistor - up to~25x leakage reduction
~3-4x leakage reduction
Reverse bias~3x leakage
reduction
Standby supply + reverse bias~10x leakage reduction
Off-transistorload line
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0
20
0 0.2 0.4 0.6 0.8 1
VDD [V]
Next Lecture
Optimal supplies and thresholds
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