ee354l quiz (~8.5%) spring 2019 instructor: gandhi puvvada

February 21, 2019 9:22 pm EE354L Quiz - Spring 2019 1/9 C Copyright 2019 Gandhi Puvvada

EE354L Quiz (~8.5%)Closed-book Closed-notes Exam; No cheat sheets;

Calculators, smart phones, tablets (and any kind of computing/Internet devices) are not allowed. Verilog Guides are provided in the exam.

This is a Crowdmark exam. Please do not write on margins or on backside. Use HB or 1H pencil. It should be a dark pencil.

Spring 2019Instructor: Gandhi Puvvada

Friday, 2/22/2019 8:00 AM - 9:45 AM (1 Hour 45 min.) in GFS106

Viterbi School of Engineering

University of Southern California

Ques# Topic Page# Time Points Score

1 Verilog 2 15 min 32

2 Labs 3-5 50 min 108

3 State Machine Design 6-7 25 min 118

4 Memory Address Map 8 10 min 33

Total 1+7+1=9 1H 40M 221

Perfect Score 280


1 ( 12 + 20 = 32 points) 15 min. Verilog

1.1 There are four Verilog codes (A, B, C, D) and four schematics (1, 2, 3, 4). Match them to the extent possible. If there is no match modify one or more of the Verilog codes to the minimum extent.

1.2 If you are in State S0, you can skip coding under what conditions would you go back to S0. T / FBased on the flow-chart, complete the state diagram, complete the two codes #1 and #2, If possible, write code #3 in such a way that you make one of the four state transitions, an implicit state transition! If it is not possible, state the reasons.

12pts

4*3=12

always @(posedge clk, posedge reset)if (~reset)

Q <= 0;else

Q <= D;

always @(posedge clk, negedge reset)if (reset)

Q <= 0;else

Q <= D;

always @(posedge clk)if (~reset)

Q <= 0;else

Q <= D;

always @(negedge clk)if (~reset)

Q <= 0;else

Q <= D;

D Q

clk

reset

D Q

clkclr

D Q

clk

reset

D Q

clkclr

D Q

clkreset

D Q

clkD Q

clkreset

D Q

clk

A

B

C

D

1 2 3 4

same as ____ (1/2/3/4)

same as ____ (1/2/3/4)

same as ____ (1/2/3/4)

same as ____ (1/2/3/4)

20pts

6+6+8A?

T

F

S1

S0

B?TFS3

C?T F

S2

S0

S1

S2

S3

S0: begin

if ( )state <= ;

elseif ( )

state <= ;else

if ( )state <= ;

elsestate <= ;

end

S0: begin

if ( )state <= ;

elsestate <= ;

if ( )state <= ;

if ( )state <= ;

end

#1 #2

nested if statement

independent if statements

#3


2 ( 49+6+12+9+24+8 = 108 points) 50 min. Labs

2.1 Detour signal: You implemented the 7-state detour state machine using one-hot state assignment method. If we go back to the EE101/109L method of encoded state assignment method (see the block diagram below), we would need ______ Flip-Flops in the SM (State Memory) block. And the OFL (Output Function Logic) becomes a logic with _____ input(s) and _____ output(s). And the NSL (Next State Logic) becomes a logic with _____ outputs and a total of ______ inputs ( ____ inputs due to the current state inputs and ____ input(s) due to ____________________________ (write either just "LR_BAR" or "LR_BAR, ~RESET" and explain your choice below)). Explain in detail:__________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________Choosing to implement the state machine in encoded state assignment method _______(A/B/C) in the number of flip-flops in the SM block and it _______(A/B/C) in the complexity of the NSL block.Legend A = causes a reduction, B = causes an increase, C = could cause either a reduction or an increase)

Write either I <= 0; or I < I + 1; in some of the above states as appropriate. In the case of the NSL that you built in lab using the one-hot state assignment method, the NSL for how many FFs (out of the seven) are to be changed to incorporate the I addition? ________And which are they? They are NSLs for ____________________________________________You arrived at the above answer based on ______ (X/Y/Z), where X = based on states which have their RTL changed with either I <= 0; or I < I + 1; Y = state transition conditions changing on the converging arrows (converging on to those states); Z = state transition conditions changing on the diverging arrows (diverging from those states); _________ (ME/AI/Both ME and AI) rule(s) is/are applied to state transition conditions associated with the state transition arrows ______________________ (converging on to / diverging from) a state.

SMNSL OFLPICSDNS

PI = Prevailing InputsCS= Current StateDNS = Desired Next State

49pts

7+4=11

1+1+3

8+4=12

4*2=8

Extract from our ee201_detour_top.v:assign sys_clk = DIV_CLK[25]; // DIV_CLK[25] (~1.5Hz) = (100MHz / 2**26)We have chosen this slow clock, DIV_CLK[25], as our system clock so thatwe can see the states changing not too fast but not too slow either. At this slow rate, the LED groups glow with the same intensity. T / F

Changing the sys_clk to DIV_CLK[24] make it _________ (faster/slower).

Changing it to the rate of scanning SSDs makes it too ______ (fast/slow)for human eye to notice the growing arrow. At this rate, the LED groups glow with the same intensity. T / F

Use a counter I to hold the detour signalin the R123 state (similarly in L123state for 4 clocks (instead of the current1 clock in these states).

Mr. Bruin says that you need a 3-bitcounter for I as 4 in binary is 100. Shallwe allow Mr. Bruin to transfer to USC? _____________________________________________________________________________________________

3++3+3

2+2=4


2.1.1 You simulated the detour design and produced the following waveforms.Which of the following four types of simulations did you choose to perform in ISim?Behavioral Simulation Post-Translate Post-Map Post-Route Did you simulate the top design (ee201l_detour_top.sch) or the core design (ee201l_detour.sch)? top / core Why/Why not? ____________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________

2.1.2 I have removed the LR_Bar waveform from the following. Is it produced by testbench or the DUT (Design Under Test)? _______________ Is it a stimulus or a response? ____________Based on the remaining waveforms, try to draw a possible/suitable waveform for the LR_Bar.Is there only one correct answer or there can be several equally good answers? one / severalExplain: __________________________________________________________________________________________________________________________________________________________________________________________________________________________

2.2 Picoblaze and its interface with fabric logicIdentify signals in the figure on the right that are associated with an INPUT port to interface say ___________ (switches/leds).______________________________________________________________________Identify signals in the figure on the right that are associated with an OUTPUT port to interface say ___________ (switches/leds).______________________________________________________________________Are there any bidirectional signal in the above figure? ________________________________In a general purpose processor chip, which of the above signals may have been combined into a set of bidirectional signals?______________________________________________________

6pts

2+2+4

2+2+4+4

12pts

To and From Reg. File

3*3=9

9pts


2.3 Scanning control alteration to adjust brightness // The clock divider is just for your informationreg [26:0] divclk; always @(posedge board_clk , posedge reset)

beginif (reset)

divclk <= 0;else

divclk <= divclk + 1'b1;end

assign sev_seg_clk = divclk[17:16];

// In the following four lines from the original design,I have replaced An0 with An0_I (standing for Anode 0 Intermediate) and similarly the other three.

assign An0_I= ~((~(sev_seg_clk[1])) && (~(sev_seg_clk[0]))); // when sev_seg_clk = 00assign An1_I= ~((~(sev_seg_clk[1])) && ( (sev_seg_clk[0]))); // when sev_seg_clk = 01assign An2_I= ~(( (sev_seg_clk[1])) && (~(sev_seg_clk[0]))); // when sev_seg_clk = 10assign An3_I= ~(( (sev_seg_clk[1])) && ( (sev_seg_clk[0]))); // when sev_seg_clk = 11

assign W = ( divclk[18] & (~(divclk[19])) );assign X = ~ W;assign Y = ( ( divclk[18] & (~(divclk[19])) ) | (divclk[20]) );assign Z = ~ Y;// In each of the four statements below, you decide whether to use an OR (|) operator or an AND (&) operator to complete it. // Some percentages and fractions: 100%, 75% (3/4), 50% (1/2), 25% (1/4), 12.5% (1/8), 6.25% (1/16), 37.5% (3/8), 62.5% (5/8), 87.5% (7/8),

assign An0 = An0_I) W ; Enabled for ___%, Disabled for ___%, Brightness got reduced to ___assign An1 = An1_I) X ; Enabled for ___%, Disabled for ___%, Brightness got reduced to ___ assign An2 = An2_I) Y ; Enabled for ___%, Disabled for ___%, Brightness got reduced to ___ assign An3 = An3_I) Z ; Enabled for ___%, Disabled for ___%, Brightness got reduced to ___

2.4 GCD lab: If Ain (A initial) and Bin (B initial) are both equal to decimal 64 in the INIT state, how many common factors of 2 are extracted in the SUB state and how many clocks are spent in the MULT state? _____________________________________________________________________________________________________________________________________________________

24pts

di vc l k[ 16]

di vc l k[ 17]

di vc l k[ 18]

di vc l k[ 19]

di vc l k[ 20]

We can use different combinationalfunctions of the three signals, div-clk[20:18], to exercise differentbrightness control on the SSDs. Ihave produced four signals, W, X,Y, and Z for this purpose.

3*4=12

bonus=12

INIT

DONE

MULTSUB

8pts


3 ( 21+21+33+28+15 = 118 points) 25 min. State machine design related to division

Here, given a Xin (X initial), we need to find if it is divisible by both 7 and 3 or at least by one of them or neither of them. Xin is an 8-bit unsigned number. You copy Xin into both A and B and perform A <= A -7; and B <= B - 3; repetitively until you know if it is divisible or not. You are neither interested in the quotients nor in the reminders. You are given unsigned subtracters and comparators. Caution: Remember that 6 minus 7 yields minus 1. The minus 1 shows up as all 1’s (1111_1111) and it looks like a 255. The unsigned comparators find it bigger than both 7 and 3.

3.1 Mealy machine: Complete the DIV state (its RTL and state transition conditions associated with the diverging arrows). Also, complete the clocks spent in the DIV state for the Xin values listed below. Notation: ND7 = Not Divisible by 7, D7 = Divisible by 7, D7_D3 = Divisible by 7 as well as Divisible by 3.

3.2 Moore machine: Complete it along with the data path for B-Reg. on the next page. Here we have three DIV states: DIV73 (Divide by 7 as well as by 3), Div3_ND7 (continue dividing by 3 but the division by 7 has failed) and Div3_D7 (continue dividing by 3 after the division by 7 has succeeded).

14+7pts

21pts

7*3=21

INIA <= XIN;

DIV

START

START

~RES

ET

B <= XIN;A <= A - 7;

B <= B - 3;

if (A 7)

if (B 3)

ND7_ND3 ND7_D3 D7_ND3 D7_D3

1 111


33pts

21 +7pts

15pts

INIA <= XIN;

DIV73

START

START

~RES

ET

B <= XIN;A <= A - 7;

B <= B - 3;

ND7_ND3 ND7_D3 D7_ND3 D7_D3

1 111

DIV3_ND7

B <= B - 3;

DIV3_D7

B <= B - 3;

D[7:0]

Q[7:0]

clk

i0i1 ys

B i0i1 ys

SubtracterPQ

P-Q

11*3=33


4 (4+21+8 = 33 points) 10 min. Memory

4.1 C0000 to CFFFF is a _____ (128K/64K/32K) range.

4.2 If the 32Kx8 memory on the right is built using the 4 chips as shown starting at C8000 Hex in a 20-bit address system (1MByte address space), fill-in the 7 boxes with 3 more staring addresses and 4 ending addresses for the 4 chips.

4.3 Out of the following 4 other alternative arrangements, mark any chip(s) which is/are sitting in unnatural address range(s).

8Kx8

4Kx8

4Kx8

16Kx8

C8000 H

4pts

21pts

7*3=21

4+4pts

8Kx8

4Kx8

4Kx8

16Kx8

8Kx8

4Kx8

4Kx8

16Kx8

8Kx8

4Kx8

4Kx8

16Kx8

8Kx8

4Kx8

4Kx8

16Kx8

The remaining weeks of the semester are very important. Please attend every class and participate in the class discussion/exercise. Do clarify your questions before the next class.Gandhi, TAs Yueh-Hsun Lin, Jinglei Cheng, Kiran Nagendra, and Arun Sai Mamidala, Mentor Ana Rescala, Grader Akshay Keshavamurthy

Blank Area


Blank page: Please write your name and email. Tear it off and use it for rough work. Do not submit at the end. Keep it with you.

Student’s Last Name:____________________ email: __________________

ee354l quiz (~8.5%) spring 2019 instructor: gandhi puvvada

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