ee382v: embedded system design and...

EE382V: Embedded Sys Dsgn and Modeling

Lecture 1

(c) 2009 A. Gerstlauer 1

EE382V:Embedded System Design and Modeling

Andreas GerstlauerElectrical and Computer Engineering

University of Texas at [email protected]

Lecture 1 - Introduction

EE382V: Embedded Sys Dsgn and Modeling, Lecture 1 © 2009 A. Gerstlauer 2

Lecture 1: Outline

• Introduction• Embedded systems

• Abstraction levels, design flow

• System-level design

• Design tasks, challenges and tools

• Course information• Administration

• Topics

• Materials

• Policies

• Projects


Lecture 1



Embedded Systems

• Systems that are part of a larger system

• Application-specific– Diverse application areas

• Tight constraints– Real-time, performance, power, size

– Cost, time-to-market, reliability

• Ubiquitous

• Far bigger market than general-purpose computing (PCs, servers)

– $46 billion in ‘04, >$90 billion by 2010, 14% annual growth

– 4 billion devices in ‘04

– 98% of processors sold[Turley02, embedded.com]


Embedded System Design is hard…


Lecture 1



… and getting harder

• Growing system complexities• Increasing application demands

– Device convergence (multimedia, infotainment, GPS, …)

• Technological advances– Multi-Core/Multi-Processor System-On-Chip (MPSoC)

Raising the level of abstraction

10,000

1,000

100

10

1

0.1

0.01

0.001

Lo

gic

tra

nsi

sto

rs p

er

chip

(in

mill

ion

s)100,000

10,000

1000

100

10

1

0.1

0.01

Pro

du

ctiv

ity

(K)

Tra

ns.

/Sta

ff-M

o.

1 98 1

1 98 3

1 98 5

1 98 7

1 98 9

1 99 1

1 99 3

1 99 5

1 99 7

1 99 9

2 00 1

2 00 3

2 00 5

2 00 7

2 00 9

IC capacity

Productivity

Gap

Source: SEMATECH; Courtesy of: T. Givargis, F. Vahid. “Embedded System Design”, Wiley 2002.


iPhone 3G


Lecture 1



Multi-Processor System-On-Chip (MPSoC)

DCT(IP)

TX

ARM(ARM7TDMI)

M1(SRAM)

M1Ctrl

I/O4(HW)

CoPro(Custom)

DSP(DSP56k)

MBUS

BUS1 (AHB) BUS2 (DSP)

S

SS

S

M

S

M2/S

M1 MA

rbit

er1

Arb

IP BridgeM

S

DCTBus

S

I/O3(HW)

S

I/O2(HW)

S

I/O1(HW)

S

S

DMA(2753A)

• 2 Subsystems

• ARM7TDMI

• MotorolaDSP 56600k

• 4 Accelerator HW blocks

• 10 I/O HW blocks

• 5 Busses


System levelSystem levelSystem levelSystem level

Abstraction Levels

• Growing system complexities

Move to higher levels of abstraction [ITRS07, itrs.net]

Electronic system-level (ESL) design

1E0

1E1

1E2

1E3

1E4

1E5

1E6

1E7

Number of componentsLevel

Gate

RTL

Algorithm

Transistor

Ab

stra

ctio

n

Ac

cura

cy

Source: R. Doemer, UC Irvine


Lecture 1



Abstraction Levels

Temporal orderLow abstraction

High abstraction

Implementation DetailImplementation Detail

Spatial order

physical layout

unstructured

StructureStructure

real time

untimed

TimingTiming


Top-Down Design Flow

Implementation

Architecture

Specification

Logic Design

Product planning

Structure

pure functional

bus functional

RTL / ISA

gates

requirements

Timing

untimed

timing accurate

cycle accurate

gate delays

constraints

System Design

Processor Design


Lecture 1



System-Level Design

• From system specification• Functionality, behavior

– Application algorithms– Constraints

• To system architecture• Structure

– Spatial and temporal order– Components and connectivity– Across hardware and software

Design automation at the system level• Modeling and simulation• Synthesis• Verification

Proc

Proc

Proc

Proc

Proc

Memory

Memory

µProcessor

Interface

Comp.IP

Bus

Interface

Interface

Interface

Custom HW

Requirements, constraints

Implementation (HW/SW synthesis)

Computation & Communication

Design


System Specification

• Capture requirements• Functional

– Free of any implementation details

• Non-functional– Quality metrics, constraints

• Formal representation• Models of computation

– Analysis of properties

• Executable– Validation through simulation

Application development Precise description of desired system behavior

Natural language Ambiguous Incomplete


Lecture 1



System Architecture

Heterogeneous multi-processor systems

Multi-Processor System-on-Chip (MPSoC)

Bri

dg

e

P1 P3

CPU Mem

HW IP

P5

C1, C2

Arb

iter

P4P2

C1, C2CPU Bus IP Bus

• Processing elements (PEs)• Processors

– General-purpose, programmable– Digital signal processors (DSPs)– Application-specific instruction

set processor (ASIP)– Custom hardware processors– Intellectual property (IP)

• Memories

• Communication elements (CEs)• Transducers, bus bridges• I/O peripherals

• Busses• Communication media

– Parallel, master/slave protocols– Serial and network media


System Implementation

• Hardware• Microarchitecture• Register-transfer level (RTL)

• Software binaries• Application object code• Real-time operating

system (RTOS)• Hardware abstraction layer (HAL)

• Interfaces• Pins and wires• Arbiters, muxes, interrupt

controllers (ICs), etc.• Bus protocol state machines

CP

U

Further logic and physical synthesis

Manufacturing

Prototyping boards


Lecture 1



Source: T. Noll, RWTH Aachen, via R. Leupers, “From ASIP to MPSoC”, Computer Engineering Colloquium, TU Delft, 2006

Processor Implementation Options


Design Challenges

• Design quality metrics and constraints

• Performance– Latency and throughput

• Power– Static and dynamic power consumption

• Cost– Unit and non-recurring engineering (NRE) costs

• Dependability and reliability– Fault tolerance, safety, correctness, mean time between failure (MTBF)

• Management– Time-to-market, maintainability, flexibility

• …

Multi-objective optimization in vast design space

Complexity High degree of parallelism, large number of implementation options

Heterogeneity Different types of components and applications, irregular architectures


Lecture 1



Bri

dg

e

CPU Mem

HW IP

Arb

iter

v1

C1

B1 B2

B3 B4

C2

CommunicationComputation &

System SynthesisFront-End


Software / HardwareSynthesisBack-End


TLM

Inst

ruct

ion

-Set

Sim

ula

tor

(IS

S) C

-based

RT

L

Software Object Code

Hardware VHDL/Verilog

Application specification

Transaction-Level ModelsTLMTLMTLMn

Platform library

Electronic System-Level (ESL) Flow

SystemC, CoWare, …

Mentor Catapult,Forte, …

VaST,ARM Realview,…

Green Hills,gcc, VxWorks, …

Synopsys Design Compiler, …

SPIRIT/IP-XACT (XML)

MARTE (UML)

Tensilica

Matlab/Simulink,LabView, …

System-Level Design Languages (SLDLs)

C/C++ code

SCE, Metropolis …


System-On-Chip Environment (SCE)

ArchnArchnTLMn

Impln

Spec

ImplnImpln

Synthesize target HW/SW

Compile onto platform

Commercial derivative for Japanese Aerospace Exploration Agency

Commercial derivative for Japanese Aerospace Exploration Agency

Specification

System Design(Specify-Explore-Refine)

SWDB

Systemmodels

CPUn.bin

Implementation Model

PE/CE/BusDatabase

TLMnTLMnTLMi

Hardware Synthesis

Software Synthesis

RTLDB

RTLnRTLnRTLnISSnISSnISSn CPUn.bin

CPUn.binHWn.vHWn.vHWn.v

Design Decisions


Lecture 1



Bri

dg

e

CPU Mem

HW IP

Arb

iter

v1

C1

B1 B2

B3 B4

C2

CommunicationComputation &





TLM

Inst

ruct

ion

-Set

Sim

ula

tor

(IS

S) C

-based

RT

L

Software Object Code

Hardware VHDL/Verilog

Application specification

Transaction-Level ModelsTLMTLMTLMn

Platform library

UT ECE Courses

System-Level Design Languages (SLDLs)

C/C++ code

EE382V: Embedded System Design & Modeling

EE382V: Embedded System Design & Modeling

EE

382N

-4:

Ad

v. S

yste

m A

rch

ite

ctu

reE

E38

2N-4

: A

dv.

Sys

tem

Arc

hit

ect

ure E

E382V

: Syste

m-o

n-C

hip

Desig

nE

E382V

: Syste

m-o

n-C

hip

Desig

n


Lecture 1: Outline

Introduction Embedded systems

Abstraction levels, design flow

System-level design

Design tasks, challenges and tools

• Course information• Administration

• Topics

• Materials

• Policies

• Projects


Lecture 1



Class Administration

• Schedule• Lectures: TTh 3:30-5pm, ENS109

• Instructor• Prof. Andreas Gerstlauer

– E-mail: [email protected]– Office: ACE 6.118– Office hours: T 5:00-6:30pm, W 2:00-3:30pm

• Teaching Assistant• TBD

• Information• Web page: http://www.ece.utexas.edu/~gerstl/ee382v_f09• Announcements, assignments, grades: Blackboard• Questions, discussions: Blackboard


Course Outline

• System-level design• Methodologies, design flow, models• System-level design languages (SLDL): SpecC, SystemC

• Functional modeling• System specification and validation concepts• Formal Models of Computation (MoC)

• System synthesis• Profiling, analysis and estimation tools• Design space exploration algorithms

• Architecture modeling• Computation and communication refinement• Virtual platform prototyping, transaction-level modeling

Prerequisites Software: C/C++ (algorithms and data structures) Hardware: VHDL/Verilog (digital design) Embedded systems and embedded software


Lecture 1



Textbooks (1)

• Main textbook

• D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner, Embedded System Design: Modeling, Synthesis, Verification, Springer, 2009 (“orange book”)

• Optional books

• A. Gerstlauer, R. Doemer, J. Peng, D. Gajski, System Design: A Practical Guide with SpecC, Kluwer, 2001 (“yellow book”)

– Practical, example-driven introduction using SpecC


Textbooks (2)

• Optional books (cont’d)

• T. Groetker, S. Liao, G. Martin, S. Swan,System Design with SystemC, Kluwer, 2002 (“black book")

– Reference for SystemC language and methodology

• F. Vahid, T. Givargis, Embedded System Design: A Unified Hardware/Software Introduction, Wiley, John & Sons, 2001

– Background about embedded systems in general

Additional reading material posted on class webpage


Lecture 1



Policies

• Grading

• Homeworks: 20%

• Labs: 20%

• Midterm: 20%

• Project: 40%

• Academic dishonesty

• Homeworks– Discuss questions and problems with others

– Turn in own, independent solution

• Labs and project– Project teams, one report and presentation

– Reference and quote any outside source of information


Project

• Project timeline (tentative)

• Abstract: beginning of October

• Proposal, literature survey: week after midterm (mid Oct.)

• Presentations: last week of classes (Dec. 1 & 3)

• Report: finals week

• Past project examples

• A. Pedram, C. Craven, “Modeling Cache Effects at the Transaction Level,” IESS 2009.

• A. Banerjee, “Transaction Level Modeling of Best Effort Channels for Networked Embedded Devices”, IESS 2009.


Lecture 1



Possible Projects

• Design examples

• Develop specification model of a system design example

• Validate, explore and refine example using SCE

• Specification modeling

• Model-based design: mapping of MoCs into SLDLs

• Analysis and optimization of MoCs

• Synthesis

• Investigate design quality estimation techniques

• Develop system-level decision making algorithms

• Implement design space exploration plug-in for SCE

• Architecture modeling

• Component database models: busses, processors

• Platform modeling and simulation concepts: timing, power

ee382v: embedded system design and...

Documents