Chapter 12: Analog-to-Digital Converter

EE383: Introduction to Embedded Systems University of Kentucky

Samir Rawashdeh

With slides based on material by H. Huang – Delmar Cengage Learning

Basics of A/D Conversion Many embedded systems need to deal with nonelectric quantities: weight, humidity, pressure, weight, mass or airflow, temperature, light intensity, and speed. These nonelectric quantities are analog in nature. Analog quantities must be converted into digital format so that they can be processed by the computer. An A/D converter can only deal with electric voltage. Any nonelectric quantity must be converted into an electric quantity using certain type of transducer. A transducer converts a nonelectric quantity into an electric quantity. The output of a transducer may not be in a suitable range for A/D conversion. A signal conditioning circuit is needed to shift and scale the transducer output to a range suitable for A/D conversion.

Transducer

Temperature

Pressure

LightWeight

Airflow

Humidity...

Such as a sensor,load cell,photocall, orthermocouple..

Signal- conditioning

circuit

(optional)

Voltage Voltage A/Dconverter

Computer

Digitalvalue

Figure 12.1 The A/D conversion process

Analog Voltage and Digital Code Characteristic

Voltage

Dig

ital

Cod

e

Figure 12.2 An ideal A/D converter output characteristic

An ideal A/D converter should have an characteristic as shown in Figure 12.2. An A/D converter with characteristic as shown in Figure 12.2 would need infinite number of bits to represent the A/D conversion result.

An n-bit A/D converter has 2n possible output code values. The output characteristic of an n-bit A/D ideal converter is shown in Figure 12.3. The area above and below the dotted line is called quantization error. Using n-bit to represent A/D conversion has an average error of 2n+1. A real A/D converter output may have nonlinearity and non-monotonicity errors.

Figure 12.3 Output characteristic of an ideal n-bit A/D converter

VDD/2n VDD

2n-1

Out

put c

ode

Voltage

Vin (analog input)

Digital-to-analog converter

Output Latch

Digital code

Successive approximationregister (SAR)

Control LogicClock

Figure 12.4 Block diagram of a successive approximation A/D converter

+

-

analog comparator

VRH

VRL

Start

SAR[n-1, ..., 0] ← 0i ← n - 1

SAR[i] ← 1

Convert the value in SAR to a voltage

Is theConverted voltage

greater thanthe input?

SAR[i] 0yes

no

i = 0?

i ← i - 1

Stop

yes

no

Figure 12.5 Successive approximation A/D conversion method

Optimal Voltage Range for A/D Conversion Needs a low reference voltage (VRL) and a high reference voltage (VRH) in performing A/D conversion. VRL is often set to ground level. VRH is often set to VDD. Most A/D converter are ratiometric, i.e., (a) A 0 V (or VRL) analog input is converted to the digital code of 0. (b) A VDD (or VRH) analog input is converted to the digital code of 2n – 1. (c) A k-V input will be converted to the digital code of k × (2n – 1) ÷ VDD. The A/D conversion result will be the most accurate if the value of analog signal covers the whole voltage range from VRL to VRH. The A/D conversion result k can be translated back to an analog voltage VK by the following equation: VK = VRL + (range × k) ÷ (2n – 1)

Clockprescaler

Bus clock

Mode and timing controlConversioncomplete interrupt

SuccessiveapparoximationRegister (SAR)

and DAC

ATD 0ATD 1

ATD 2ATD 3

ATD 4ATD 5

ATD 6ATD 7

11

sample and hold

+-

comparator

ATD input enable register

Port AD data register

AnalogMUX

results

ATD clock

VRHVRL

VDDAVSSA

AN7/PAD7AN6/PAD6AN5/PAD5AN4/PAD4AN3/PAD3AN2/PAD2AN1/PAD1AN0/PAD0

Figure 12.8 The HCS12 ATD block diagram

ADC on the Dragon12_JR board

Trimmer POT

Temperature Sensor

Light Sensor

Temperature Sensor TC1047A Has 3 pins with voltage output directly proportional to the ambient temperature. Can measure temperature in the range of -40oC to 125oC with a supply from 2.7~5.5V. Voltage output at -40oC, 0oC, 25oC, and 125oC are 100mV, 500mV, 750mV, 1.75V.

VSS

VDD VOUT

TC1047A

1 2

3

1.75

0.1

-40 0

0.5

0.9

40 12590

1.4

Temperature

VOUT

Figure 12.17 TC1047A VOUT vs. temperature characteristic

The Humidity Sensor IH-3606 Provides a linear voltage output from 0.8 to 3.9 V in the full range of relative humidity 0% to 100% with 5 V power supply. Is light sensitive and should be shielded from light for best result. Can resist contaminant vapors, such as organic solvents, chlorine, and ammonia. Requires a 1kHz low-pass filter at its voltage output before it can be converted.

Specification Description

total accuracyInterchangeabilityOperating temperatureStorage temperatureLinearityRepeatabilityHumidity StabilityTemp. effect on 0% RH voltageTemp. effect on 100% RH voltageOutput voltage

VS Supply requirement

Current requirement

± 2% RH, 0-100% TH @25oC± 5% RH up to 60% RH, ±8% RH at 90% RH-40 to 85oC (-40 to 185oF)-51 to 110oC (-60 to 223oF)±0.5% RH typical±0.5% RH±1% RH typical at 50% RH in 5 years±0.007% RH/oC (negligible)-0.22% RH/oCVOUT = (VS)(0.16 to 0.78) nominal relative to supply voltage for 0-100% RH; i.e., 1-4.9V for 6.3V supply; 0.8 - 3.9V for 5V supply; Sink capability 50 microamp; drive capability5 microamps typical; low pass 1KHz filter required. Turn on time < 0.1 sec to full output. 4 to 9V, regulated or use output/supply ratio; calibrated at 5V200 microamps typical @5V, increased to 2mA at 9V

Table 12.10 Specifications of IH-3605

The SenSym ASCX30AN Pressure Sensor - Is a 0 to 30 psia (psi absolute) pressure transducer - The range of barometric pressure is between 28 to 32 inches mercury (in-Hg) or 13.75 to 15.72 psi or 948 to 1083.8 mbar. - The transducer output is about 0.15V/psi, which would translate to 2.06V to 2.36V.

ASCX30AN

1 2 3 4 5 6

Pin 1: External offset adjustPin 2: VSPin 3: VOUTPin 4: GNDPin 5: N/CPin 6: N/C

Figure 12.21 ASCX30AN pin assignment

Clockprescaler

Bus clock

Mode and timing controlConversioncomplete interrupt

SuccessiveapparoximationRegister (SAR)

and DAC

ATD 0ATD 1

ATD 2ATD 3

ATD 4ATD 5

ATD 6ATD 7

11

sample and hold

+-

comparator

ATD input enable register

Port AD data register

AnalogMUX

results

ATD clock

VRHVRL

VDDAVSSA

AN7/PAD7AN6/PAD6AN5/PAD5AN4/PAD4AN3/PAD3AN2/PAD2AN1/PAD1AN0/PAD0

Figure 12.8 The HCS12 ATD block diagram

The HCS12 A/D Converter A HCS12 member may have one or two 8-channel 10-bit A/D converters. The highest frequency of the conversion clock is 2 MHz. At 2 MHz conversion clock, a sample may take 6 µs or 7 µs to complete a conversion for 8-bit and 10-bit resolution. An A/D conversion can be started by writing a value to a control register or by an external trigger input. The conversion result can be right-justified unsigned, left-justified signed, and left-justified unsigned.

Signal Pins Related to A/D Converter The AD0 module has analog input pins AN0 ~ AN7. The AD1 module has analog input pins AN8 ~ AN15. The AN7 pin can be optionally used as the trigger input pin for AD0 module. The AN15 pin can be optionally used as the trigger input pin for AD1 module. VRH and VRL are the high and low reference voltage input. VDDA and VSSA are power supply and ground inputs for the A/D converters. Registers Related to A/D Converters Each A/D module has the following registers: Six control registers: ATDxCTL0 ~ ATDxCTL5. (ATDxCTL0 and ATDxCTL1 are used for factory testing only). Two status registers: ATDxSTAT0 and ATDxSTAT1 Two testing registers: ATDxTEST0 and ATDxTEST1 One input enable register: ATDxDIEN One port data register: PTADx Eight 16-bit result registers ATDxDR0~ATDxDR7 where, x = 0 or 1

ATD Control Register 2 (ATD0CTL2, ATD1CTL2)

7 6 5 4 3 2 1 0

ADPU AFFC AWAI ASCIE ASCIFETRIGLE ETRIGP ETRIGE

0 0 0 0 0 0 0 0reset:

ADPU: ATD power down bit 0 = power down ATD 1 = normal ATD operationAFFC: ATD fast flag clear all bit 0 = ATD flag is cleared normally, i.e., read the status register before reading the result register 1 = any access to a result register will cause the associated CCF flag to clear automatically if it is set at the timeAWAI: ATD power down in wait mode bit 0 = ATD continues to run when the HCS12 is in wait mode 1 = halt conversion and power down ATD during wait modeETRIGLE: External trigger level/edge control This bit controls the sensitivity of the external trigger signal. Details are shown in Table 12.1.ETRIGP: External trigger polarity This bit controls the polarity of the external trigger signal. See Table 12.1 for details.ETRIGE: External trigger mode enable 0 = disable external trigger on ATD channel 7 1 = enable external trigger on ATD channel 7ASCIE: ATD sequence complete interrupt enable bit 0 = disables ATD interrupt 1 = enables ATD interrupt on sequence complete (ASCIF = 1)ASCIF: ATD sequence complete interrupt flag 0 = no ATD interrupt occurred 1 = ATD sequence complete interrupt pending

Figure 10.9 ATD control register 2 (ATDxCTL2, x = 0 or 1)

A/D External Triggering A/D external triggering can be edge-triggering or level-triggering. The choice of external triggering is controlled by the ATDxCTL2 register.

Table 12.1 External trigger configurations

ETRIGLE ETRIGP External triggersensitivity

0011

0101

falling edgerising edgelow levelhigh level

7 6 5 4 3 2 1 00 S8C S4C FRZ1 FRZ0S2C S1C FIFO

0 0 0 0 0 0 0 0reset:S8C,S4C,S2C,S1C: Conversion sequence limit 0000 = 8 conversions 0001 = 1 conversion 0010 = 2 conversions 0011 = 3 conversions 0100 = 4 conversions 0101 = 5 conversions 0110 = 6 conversions 0111 = 7 conversions 1xxx = 8 conversionsFIFO: Result register FIFO mode 0 = conversion results are placed in the corresponding result register up to the selected sequence length 1 = conversion results are placed in consecutive result registers (wrap around at end)FRZ1 and FRZ0: background debug (freeze) enable bit 00: continue conversions in active background mode 01: reserved 10: finish current conversion, then freeze 11: freeze immediately when background mode is active

Figure 10.10 ATD control register 3 (ATDxCTL3, x = 0 or 1)

ATD Control Register 3 (ATD0CTL3 and ATD1CTL3) If the FIFO bit is 0, the result of the first conversion appears in the first result register, the second conversion appears in the second result register, and so on. If the FIFO bit is 1, then the result of the first conversion appears in the result register specified by the conversion counter.

ATD Control Register 4 (ATD0CTL4 and ATD1CTL4) This register sets the conversion clock frequency, the length of the second phase of the sample time, and the resolution of the A/D conversion. Writes to this register will abort the current conversion. There are two stages in the sample time. The first stage sample time is fixed at two conversion clock period. The second stage is selected by SMP1 and SMP2 bits of this register.

7 6 5 4 3 2 1 0SRES8 SMP1 SMP0 PRS1 PRS0PRS4 PRS3 PRS2

0 0 0 0 0 1 0 1reset:

SRES8: ATD resolution select bit 0 = 10-bit operation 1 = 8-bit operationSMP1 and SMP0: select sample time bits These bits are used to select the length of the second phase of the sample time in units of ATD conversion clock cycles. See Table 12.2.PRS4--PRS0: ATD clock prescaler bits These five bits are the binary value prescaler value PRS. The ATD conversion clock frequency is calculated as follows:

The ATD conversion frequency must be between 500KHz and 2 MHz. The clock prescaler values are shown in Table 12.3.

Figure 12.11 ATD control register 4 (ATDxCTL4, x = 0 or 1)

ATDclock = [bus clock]PRS + 1

× 0.5

ATD Control Register 5 Selects the type of conversion sequence and the analog input channels to be sampled. Writes to this register will abort the current conversion. Table 12.4 selects the channel to be converted. Table 12.5 summarizes the result data formats available and how they are set up using the control bits. Table 12.6 illustrates the difference between the signed and unsigned, left justified and right justified output codes for an input signal range between 0 and 5.12V.

7 6 5 4 3 2 1 0DJM DSGN SCAN CB CAMULT 0 CC

0 0 0 0 0 0 0 0reset:

DJM: Result register data justification 0 = left justified data in the result registers 1 = right justified data in the result registersDSGN: Result register data signed or unsigned representation 0 = unsigned data representation in the result registers 1 = signed data representation in the result registers (not available in right justification)SCAN: Enable continuous channel scan bit 0 = single conversion sequence 1 = continuous conversion sequences (scan mode)MULT: Enable multichannel conversion bit 0 = sample only one channel 1 = sample across several channelsCC, CB, and CA: Channel select code The channel selection is shown in Table 12.4.

Figure 12.12 ATD control register 5 (ATDxCTL5, x = 0 or 1)

Writes to this register start conversion

Table 12.4 Analog input channel select code

CC CB CA

00001111

00110011

01010101

analog input channel

AN0AN1AN2AN3AN4AN5AN6AN7

Table 11.5 Available result data formats

SRES8 DJM DSGN Result data formatsdescription and bus bit mapping

111000

001001

01x01x

8-bit /left justified /unsigned -- bits 8-158-bit /left justified /signed -- bits 8 - 158-bit /right justified /unsigned -- bits 0 - 710-bit /left justified /unsigned -- bits 6 - 1510-bit /left justified /signed -- bits 6 - 1510-bit /right justified /unsigned -- bits 0 -9

Table 11.6 Left justified, signed and unsigned ATD output codes

input signalVRL = 0 VVRH = 5.12 V

Signed8-bitcodes

Unsigned8-bit codes

unsigned 10-bit codes

Signed 10-bit codes

5.120 volts5.1005.080

2.5802.5602.540

0.0200.000

7F7F7F

0100FF

8180

FFFFFE

81807F

0100

7FC07F007E00

01000000FF00

81008000

FFC0FF00FE00

810080007F00

01000000

ATD Status Register (ATD0STAT0 and ATD1STAT0) Each status flag can be cleared by writing a 1 to it.

7 6 5 4 3 2 1 0SCF 0 ETORF CC1 CC0FIFOR 0 CC2

0 0 0 0 0 0 0 0reset:

SCF: Sequence complete flag 0 = conversion sequence not completed 1 = conversion sequence has completedETORF: External trigger overrun flag 0 = no external trigger overrun has occurred 1 = external trigger overrun has occurredFIFOR: FIFO overrun flag 0 = no overrun has occurred 1 = an overrun has occurredCC2, CC1, CC0: conversion counter The conversion counter points to the result register that will receive the result of the current conversion. In non-FIFO mode, this counter is reset to 0 at the begin and end of the conversion. In FIFO mode, this counter is not reset and will wrap around when its maximum value is reached.

Figure 12.13 ATD status register 1 (ATDxSTAT0, x = 0 or 1)

Procedure for Performing A/D Conversion Step 1 Connect the hardware properly: VDDA: connect to VDD (5 V). VSSA: connect to GND VRH: connect to VDD (5 V) VRL: connect to GND Step 2 If the transducer is not in the appropriate range, use a signal conditioning circuit to shift and scale it to between VRL and VRH. Step 3 Select the appropriate channel (s) and operation modes by programming the ATD control register 5. Writing to the ATDxCTL5 register starts an A/D conversion sequence. Step 4 Wait until the SCF flag of the status register ATDxSTAT0 is set, then collect the A/D conversion results and store them in memory.

Example 12.6 Write a subroutine to initialize the AD0 converter for the MC9S12DP256 and start the conversion with the following setting: nonscan mode select channel 7 (single channel mode) fast ATD flag clear all stop AD0 in wait mode disable interrupt perform 4 conversions in a sequence disable FIFO mode finish current conversion then freeze when BDM becomes active 10-bit operation and 2 A/D clock periods of the second stage sample time choose 2 MHz as the conversion frequency for the 24 MHz bus clock result is unsigned and right justified Solution: The setting of ATD0CTL2 (a) enable AD0 (b) select fast flag clear all (set bit 6 to 1) (c) stop AD0 when in wait mode (set bit 5 to 1) (d) disable external trigger on channel 7 (set bits 4, 3, and 2 to 0) (e) disable AD0 interrupt (set bit 1 to 0) Write the value 0xE0 to ATD0CTL2.

Setting of ATD0CTL3 (a) perform four conversions (b) disable FIFO mode (c) when BDM becomes active, complete the current conversion then freeze Write the value of 0x22 into this control register. Setting of ATD0CTL4 (a) select 10-bit operation (set bit 7 to 0) (b) two A/D clock periods for sample time (set bits 6 and 5 to 00) (c) set the value of PRS4~PRS0 to 00101 Write the value 0x05 to this control register. Setting of ATD0CTL5 (a) result register right justified (set bit 7 to 1) (b) result is unsigned (set bit 6 to 0) (c) nonscan mode (set bit 5 to 0) (d) single channel mode (set bit 4 to 0) (e) select channel 7 (set bits 2..0 to 111) Write the value 0x87 to this control register

The assembly subroutine that performs the AD0 initialization:

#include "c:\miniide\hcs12.inc" openATD0 movb #$E0,ATD0CTL2 ldy #2 jsr delayby10us ; wait for 20 us movb #$22,ATD0CTL3 movb #$05,ATD0CTL4 rts #include “c:\miniide\delay.asm”