ee40 lec 19ee40 lec 19 mosfet - university of california ...ee40/fa09/lectures/lec_19.pdf · ee40...

EE40 Lec 19EE40 Lec 19

MOSFETMOSFET

Reading: Chap. 12 of Hambleyg p ySupplement reading on MOS Circuitshttp://www.inst.eecs.berkeley.edu/~ee40/fa09/handouts/EE40_MOS_Circuit.pdf

Slide 1EE40 Fall 2009 Prof. Cheung

OUTLINE

– MOSFET Structure– The MOSFET as a controlled resistor– Pinch-off ,current saturation ,channel , ,

modulation– MOSFET iD vs. vGS characteristic D GS– NMOS and PMOS I-V characteristics– Load-line analysis; Q operating point;Load line analysis; Q operating point;

Bias circuits


The MOSFET

Metal-Oxide-Semiconductor

GATE LENGTH, LOXIDE GATE WIDTH, W

Semiconductor

Field-Effect Transistor

Gate

Source Drain

THICKNESS, Tox

• No current through the gate Desired characteristics:• High ON current

Substrate

to channel• Current flowing between the

SOURCE and DRAIN is

• High ON current• Low OFF current

VTSOURCE and DRAIN is controlled by the voltage on the GATE electrode

URRE

NT


|GATE VOLTAGE|

CU

n-channel MOSFET

DSG

noxide insulatorgate

n

S

• Without a gate voltage applied no current can flow

p

Without a gate voltage applied, no current can flow between the source and drain regions (2 diodes back-to -back)

• Above a certain gate-to-source voltage (threshold voltage VT), a conducting layer of mobile electrons is formed at the Si surface beneath the oxide These


formed at the Si surface beneath the oxide. These electrons can carry current between the source and drain.

The MOSFET as a Controlled Resistor

• When VDS is low, ID increases linearly with VDS

Inversion charge density Qi(x) = -Cox[ VGS – VT - V(x) ]where Cox ≡ εox / tox.

ID

V = 1 V > V

VGS = 2 V

VDS

VGS = 1 V > VT


IDS = 0 if VGS < VT

Pinch-off and Saturation

• As VDS increases, V(x) along channel increases.Inversion-layer charge density Qn at the drain end of the channel is reduced; therefore, ID increases slower than linearly with VDS.

• When VDS reaches VGS − VT, the channel is “pinched off” at the drain end, and ID saturates (i.e. it does not increase with further increases in VDS).

VGS

+

S

G

D

VDS > VGS - VT

+–

( )2

2 TGSoxnDSAT VVLWCI −= µ

n+n+

S

VGS - VT+-

2L


pinch-off region

EE40 Fall 2009 Prof. Cheung

ID vs. VDS Characteristics

The MOSFET ID-VDS curve consists of two regions:1) Resistive or “Triode” Region: 0 < V < V V1) Resistive or “Triode” Region: 0 < VDS < VGS − VT

DSDS

TGSnD VVVVWkI

−−′=

oxnn

DSTGSnD

CkL

µ=′

where

2

2) Saturation Region: V V V

process transconductance parameter

VDS > VGS − VT

( )TGSn

DSAT VVLWkI −

′= 2

2


oxnn CkL

µ=′ where2

“CUTOFF” region: VG < VT

Channel-Length Modulation

If L is small, the effect of ∆L to reduce the inversion-layer “resistor” length is significant

→ ID increases noticeably with ∆L (i.e. with VDS)ID

I = I ′(1 + λV )ID = ID′(1 + λVDS)

λ is the slope

ID′ is the intercept

VD


VD

S

NMOS versus PMOS

T i dS t tiff

NMOS

VGSv

TriodeSaturationCut-off

V DS tov V+0 toV

PMOSTriode Saturation Cut-off

PMOS

DS tov V+ 0GSv

toV


to

N-Channel MOSFET Summary

VDS and VGS normally positive values• VGS< Vt : cut off mode, IDS=0 for any VDS

V > V t i t i t d• VGS> Vt : transistor is turned on1) VDS< VGS-Vt: Triode Region

[ ]2)(2KPWi

2) VDS> VGS - Vt: Saturation Region

[ ]2DSDStGSD vv)Vv(22KP

LWi −−•=

[ ]2tGSD )Vv(22KP

LWi −•=

Boundary between Triode and Saturation Regions

GS t DSv V v− =


GS t DS

P-Channel MOSFET Summary

vDS and vGS normally negative values• vGS > Vt :cut off mode, IDS=0 for any VDS

• vGS < Vt :transistor is turned on1) vDS > VGS-Vt: Triode Region

[ ]KPW

2) v < v V : Saturation Region

[ ]2DSDStGSD vv)Vv(22KP

LWi −−•=

2) vDS < vGS-Vt: Saturation Region

[ ]2tGSD )Vv(22KP

LWi −•=

Boundary

GS t DSv V v− =

2L


GS t DS

P-Channel MOSFET ID vs. VDS

• As compared to an n-channel MOSFET, the signs of all the voltages and the currents are reversed:g


For reference only

∝IDsat Not proportional to(VGS-Vt)2( GS t)


MOSFET VT Measurement

• VT can be determined by plotting ID vs. VGS, using a low value of VDS :using a low value of VDS :

[ ]VV)VV(2KI =I [ ] DSDSTGSD VV)VV(2KI −−=ID(A)

VGSV0


GS(V)VT

0

Common-Source (CS) Amplifier

• The input voltage vs causes vGS to

• The changing voltage drop across RD causes

vary with time, which in turn causes i to vary

VDDan amplified (and inverted) version of the input signal to appearcauses iD to vary.

RD

i

input signal to appear at the drain terminal.

+vs− +

iD

vOUT = vDS+

vIN = vGS+–VBIAS


−−

Notation• Subscript convention:

VDS ≡ VD – VS , VGS ≡ VG – VS , etc.

• Double-subscripts denote DC sources:VDD , VCC , ISS , etc.

• To distinguish between DC and incremental components of an electrical quantity, the following convention is used:– DC quantity: upper-case letter with upper-case subscriptDC quantity: upper case letter with upper case subscript

ID , VDS , etc.– Incremental quantity: lower-case letter with lower-case subscript

i v etcid , vds , etc.– Total (DC + incremental) quantity:

lower-case letter with upper-case subscript


pp piD , vDS , etc.

Load-Line Analysis of CS Amplifier• The operating point of the circuit can be determined

by finding the intersection of the appropriate MOSFET i h t i ti d th l d liMOSFET iD vs. vDS characteristic and the load line:

iD (mA)

DSDDDD viRV +=vGS (V) load-line equation:load-line


vDS (V)

Voltage Transfer Function

Goal: vOUT

Operate the amplifier in the high-gain region,

th t ll hso that small changes in vIN result in large changes in vOUT

(1): transistor biased in cutoff region

changes in vOUTvIN

(1): transistor biased in cutoff region(2): vIN > VT ; transistor biased in saturation region(3): transistor biased in saturation region (best)


(4): transistor biased in “triode” region

Quiescent Operating Point

• The operating point of the amplifier for zero input signal (vs = 0) is often referred to as the quiescent operating point. (Another word: bias.)– The bias point should be chosen so that the output

lt i i t l t d b t V d 0 Vvoltage is approximately centered between VDD and 0 V.– vs varies the input voltage around the input bias point.

Note: The relationship between vOUT and vIN is not linear; thi lt i di t t d t t lt i l If ththis can result in a distorted output voltage signal. If the input signal amplitude is very small, however, we can have amplification with negligible distortion.


p g g

Bias Circuit Example

VDD

RRD

R1

R2


Rules for Small-Signal Analysis

• A DC supply voltage source acts as a short circuitEven if AC current flows through the DC voltage source– Even if AC current flows through the DC voltage source, the AC voltage across it is zero.

A DC l t t i it• A DC supply current source acts as an open circuit– Even if AC voltage is applied across the current source,

the AC current through it is zerothe AC current through it is zero.


NMOSFET Small-Signal Model

+ idDG

+

gmvgs rovgs vds

−

DD vgvgvivii +∂

+∂

SS−

( )D

dsogsmdsDS

Dgs

GS

Dd

VVkWi

vgvgvv

vv

i

′∂

+=∂

+∂

=

from saturation region model( )

D

TGSGS

Dm

i

VVkLv

g

λ∂

−′≅∂

≡ transconductanceg

from channel modulation model


DDS

Do I

vig λ≅

∂∂

≡ output conductancefrom channel modulation model

Small-Signal Equivalent Circuit for ac signals

+ +

G D

+

gmvgs rovgs RD voutR1 R2vin

− −

S S

−

S S

( )Rrvgv ||−= ( )

( )Dout

Dogsmout

RrgvA

Rrvgv

||

||

−==

=

voltage gain


( )Domin

v Rrgv

A ||voltage gain

ee40 lec 19ee40 lec 19 mosfet - university of california ...ee40/fa09/lectures/lec_19.pdf · ee40...

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