ee457 midterm (~20%)...ee457 midterm (~20%) closed-book closed-notes exam; no cheat sheets;...

October 31, 2014 4:18 am EE457 MT - Fall 2014 1 / 10 C Copyright 2014 Gandhi Puvvada

EE457 Midterm (~20%)Closed-book Closed-notes Exam; No cheat sheets;

Calculators and Verilog Guides are allowed.

Fall 2014Instructor: Gandhi Puvvada

Friday, 10/31/201405:10 PM - 08:00 PM (2 Hour 50 min.)

Location: SGM123

Viterbi School of EngineeringUniversity of Southern California

Ques# Topic Page# Time Points Score

1 Cache and MM organization 2 15 min. 36

2 Pipelining Part 1 3-5 40 min. 95

2 Pipelining Part 2 6-7 25 min. 40

3 Single-cycle CPU vs. Multi-cycle CPU

8 15 min. 20

4 Virtual memory 9-10 40 min. 90

Total 165 min 281

Perfect Score 265

Student’s Last Name: _______________________________________

Student’s First Name: _______________________________________

Student’s DEN Bb username: [email protected]


1 ( 18 + 10 + 8 = 36 points) 15 min.

Cache and Main Memory Organization:

A 16-bit data (D15-D0) 32-bit (logical) address byte-addressable processor (address pins: A31-A1, /BE1-/BE0) has its cache and MM organized as shown below. Fill-in the 9 boxes.

1.1 Block size (based on degree of lower-order interleaving of the MM) = _______ Words = ______ BytesThe design uses ______________________ (set-associative / direct) mapping.If set-associative, degree of set associativity = _______ blocks/set The processor address space = _______ GBytes. Cache size = ________ KBytes

1.2 Please divide the address below into appropriate fields and name the fields.

18pts

CPU

Cache

16-bitbus

2-w

ay lo

wer

-ord

er

inte

rleav

ed M

M

16

One of the TAG RAMs

Addr

Data-inData-out

Comp

1

Hit

A10-A2 16

Valid

?9

(5 such TAG RAMs)

=

D7-0D15-8 D7-0D15-8XCVR XCVR

Note

Note

Address??

16-bitbus

16

Size of one TAG Ram ?

Size of one Byte-wide bank

?

Size of one Comparator

?

D7-0D15-8D15-D0

D7-0

Address

D7-0D15-8 D7-0D15-8

D7-0D15-8D7-0D15-8

proc

esso

r

Addr.

Data

CacheData RAM

Block 0’s Block 2’sBlock 1’s

Block 3’s Block 4’s

?

D15-8

AddressAddr.

Data

?

Size of one Byte-wide bank

?10pts

8pts

A19 A18 A17 A16A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A3 A2 A1 A0A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4

BE

1-B

E0


2 ( 5 + 20 + 15 + 4 + 27 + 8 + 8 +12 + 16 + 12 = 127 points) min.

Pipelining:

2.1 The figure from Lab 6 Part 5 on the side has four 5-bit comparison units and two "$0 checkers". Design a $0 checker by completing the 5-input gate by adding bubbles as needed (and if needed) on the left or right or on both sides) to produce the high-active signal EQto$0 (standing for Equal to $0).

2.2 How many comparison units are present in the 4 boxes in the 7-stage pipeline below?HDU: _____; HDU_Br: _____; FU_Br: _____; FU: _____; How many "$0 checkers" are present in the 4 boxes in the 7-stage pipeline below?HDU: _____; HDU_Br: _____; FU_Br: _____; FU: _____; _____________ (Mr. Trojan / Mr. Bruin) says that the number of "$0 checkers" should not change when you move from 5-stage to 7-stage as it is based on the number of ______________(source / destination) registers.

Now, like in Part 5 of lab 6, if we open up the four boxes and transfer all comparators and "$0 checkers" to the ID stage and then remove redundancies, we will be left with ________ 5-bit comparison units and ________ "$0 checkers".

2.2.1 Miss Bruin created two 7-stage pipelines of her own by adding two dummy stages to the 5-stage pipeline in two different ways as shown on the next page. The dummy stages are labeled IMD (Instruction memory Dummy) and DMD (Data memory Dummy). Miss Bruin has simply added the rest of circuitry (the hazard detection and stalling via HDU and HDU_Br, forwarding via I.F.R.F., FU_Br, and FU, flushing via Wrist-banding). Her TA told her that, since these is no ALU or memory access in the DMD stage, perhaps forwarding can be done at the beginning of the clock from this DMD stage. Review the stalling needs of dependent instructions and opportunities to forward to them and answer the questions below.

EQ

5 5

EQ

5 5

EQ

5 5

EQ

5 5

EQ

5 5

EQ

5 5

EQto$0

5pts

8pts

4pts

RegInstr.TLB

Instr.cache

HDU

DataTLB

Datacache

FU

IF1 IF2 ID EX MEM1 MEM2 WB

BRANCH

BR

1

7-stage pipelined version of our lab 6

FU_Br

PC

con

tro

l

HDU_Br

Zero

Assume that this is not removed

pair

#1pa

ir #2

pair

#3

pair

#1pa

ir #2

#1

8pts


Compare all three 7-stage pipelines (the one on the previous page and the above two). One student says that all the following ten items are the same in all three designs. What do you say? Assume that we are not proposing yet any redundant mux removals.

1.The flushing logic for flushing IF1 and IF2: Same / Not the same 2.The HDU: Same / Not the same 3.The HDU_Br: Same / Not the same 4.The IFRF (the internally forwarding register file): Same / Not the same 5.The two pairs of forwarding muxes in ID stage: Same / Not the same 6.The FU_Br: Same / Not the same 7.The three pairs of forwarding muxes in EX stage: Same / Not the same 8.The FU: Same / Not the same 9.Like in Lab 6 Part 5, the number of 5-bit comparators in ID: Same / Not the same 10.Like in Lab 6 Part 5, the number of $0 Checkers in ID: Same / Not the same

RegInstr.

Memory

IMD(Dummy)

HDU

DataMemory

DMDDummy

FU


BRANCH

BR

1

7-stage pipeline (5 stages plus two dummy stages) Version #1

FU_Br

PC

contr

ol

HDU_Br

Zero

pair

#1pa

ir #2

pair

#3

pair

#1pa

ir #2

RegInstr.

Memory

IMD(Dummy)

HDU

DataMemory

DMDDummy

FU


BRANCH

BR

1

7-stage pipeline (5 stages plus two dummy stages) Version #2

FU_Br

PC

con

tro

l

HDU_Br

Zero

pair

#1pa

ir #2

pair

#3

pair

#1pa

ir #2

#2

#3

Note

pts

10+5bonus


Consider the four short instruction streams below.

Dependency of lw for $3 on sub does not cause stall(s) in any of the streams running on any of the three pipelines. Agree / DisagreeFor $4 and $5 dependencies, fill-up the table below.

Relative performance of the three designs: Design(s) ___________ is/are better than design(s) ____________ because ________________________________________________________ __________________________________________________________________________________________________________________________________

sub $3, $2, $1;lw $4, 40($3);beq $5, $4, Target;

sub $3, $2, $1;lw $4, 40($3);lw $5, 60($0);beq $5, $4, Target;

sub $3, $2, $1;lw $4, 40($3);add $6, $5, $4;

sub $3, $2, $1;lw $4, 40($3);lw $5, 60($0);add $6, $5, $4;

Stream #1 Stream #2 Stream #3 Stream #4

4pts

6+3

pts6+36+3

4+4

pts4+4

Stream #1

Stream #2

Stream #3

Stream #4

$4 dependency -- stalls and eventual forwarding of correct help from lw is in MEM1/MEM2/WB

7-stage pipeline design #1 7-stage pipeline design #2 7-stage pipeline design #3

# of

stal

ls Correct forwarding helpfromMEM1/MEM2/WB

via IFRF/FU_Br/FU/Multiple #

of st

alls Correct forwarding help

fromMEM1/MEM2/WB


of st


fromMEM1/MEM2/WB

via IFRF/FU_Br/FU/Multiple

Stream #2

Stream #4

$5 dependency -- stalls and eventual forwarding of correct help from lw is in MEM1/MEM2/WB

7-stage pipeline design #1 7-stage pipeline design #2 7-stage pipeline design #3

# of

stal

ls Correct forwarding helpfromMEM1/MEM2/WB


of st


fromMEM1/MEM2/WB


of st


fromMEM1/MEM2/WB

via IFRF/FU_Br/FU/Multiple

8pts


2.2.2 Given below is a simplified block diagram of our 5-stage early branch of Lab 6.

In the above 5-stage early branch we said that A. The HDU_Br acts like a guardian angel to the FU_Br so that there is no harm if FU_Br forwards from MEM stage to ID stage even if the Senior #2 in MEM is a load word (lw). B. The FU in EX forwards from the MEM stage to the EX stage without checking if the Senior #1 in MEM stage is a load word (lw) instruction because an instruction dependent on an immediate lw senior (Senior #1) will be stalled (and distanced) in ID stage by the HDU.Comment on the following similar statements for the three 7-stage pipelines:AA. The HDU_Br acts like a guardian angel to the FU_Br so that there is no harm if FU_Br forwards from MEM1 and/or MEM2 stages to ID stage even if the Senior #2 and #3 in MEM1 MEM2 stages are load word (lw) instructions. BB. The FU in EX forwards from the MEM1 and/or MEM2 stages to the EX stage without checking if the Senior #1 in MEM1 stage and/or Senior #2 in MEM2 stage is a/are load word (lw) instruction(s) because an instruction dependent on an immediate lw senior (Senior #1) or the next senior lw instruction (Senior #2) will be stalled (and distanced) in ID stage by the HDU.Your comment on AA: _____________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________Your comment on BB: _____________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________

RegInstr.

HDU

Data

FU

IF ID EX MEM WB

BRANCH

BR

1

5-stage pipeline of the early-branch design of the 3rd ed. and our lab 6

FU_Br

PCco

ntro

l

HDU_Br

Zero

6pts

6pts


2.2.3 Opportunity to remove redundant forwarding muxes in the EX stage:In Lab 6 Part 4, we noted that we can remove the mux pair #2 in the EX stage in our original 7-stage pipeline design #1 on page #3. Which forwarding mux pair/pairs can be removed in which? Explain if it is different from the above.In #2 7-stage pipeline, we can remove _____________________________________________ ____________________________________________________________________________ In #3 7-stage pipeline, we can remove _____________________________________________ ____________________________________________________________________________ Explanation of any difference: ___________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________

2.3 In the 5-stage late branch pipeline, the VLSI engineer wanted us to shift the HDU to the EX stage even if it means creating an extra WB stage. Two students have created the extra WB stage in two different ways.

8pts

8pts

6+6pts

Data

FU

IF ID EX MEM WB

Zero

Zero

BRANCH

BR

1

RegInstr.

PC

HDU

co

ntr

ol

Before_WB

Pai

r#1

Pai

r#2

Pai

r#3

Data

FU

IF ID EX MEM After_WB

Zero

Zero

BRANCH

BR

1

RegInstr.

PC

HDU

co

ntr

ol

WB

Pai

r#1

Pai

r#2

Pai

r#3

S#1 S#2 S#3

S#1 S#2 S#3

sub $3, $2, $1;lw $5, 40($4);add $6, $3, $5;Unrelated Instr.

add lw subbubble

addlwsub bubble

Stream#1

Both students argued that their design is correctas it is able handle stream#1 as displayed witha bubble on their pipelines.

Your TA tells them to check with the followingtwo streams. One of them should fail for one ofthe two streams, he said. Notice that he used thesame very four instructions and moved the"Unrelated" instruction. Find out which fails forwhich stream and explain how.

Student #1

Student #2

Not

e

sub $3, $2, $1;lw $5, 40($4);Unrelated Instr.add $6, $3, $5;

Stream#2

Not

e

sub $3, $2, $1;Unrelated Instr.lw $5, 40($4);add $6, $3, $5;

Stream#3

You found that Student # _____ ’s design failed for stream #____. Basically in this design, an instruction in ID has to deal with ____ seniors unlike the other design which has to deal with only _____ seniors. Help from ____ ($3 / $4) was already received through IFRF in student #____’s design, so it is not necessary receive his help 2nd time.

Not

e

Not

e


3 ( 10 + 10 = 20 points) 12 min.

Single-cycle CPU vs. Multi-cycle CPU:

Compare and contrast our MIPS single-cycle CPU (in Short SCC) from our MIPS multi-cycle CPU (in short MCC) on the following aspects

Instruction register is in __________ (SCC / MCC).ALU and two separate adders are in __________ (SCC / MCC).Two separate memories are in __________ (SCC / MCC).PC_Write control is present in __________ (SCC / MCC).Control unit is a translator in __________ (SCC / MCC).There are more/wider muxes at the input of the ALU in __________ (SCC / MCC). __________ (SCC / MCC) design is taught as this maps well to the pipelined CPU design.

Since __________ (SCC / MCC) datapath has more components and less sharing, you can design the control unit in a way different from the text book namely ____________________ (SCC-based control unit / MCC-based control unit) there by providing a chunk(s) of time __________ _____________ (as needed by different instructions / maximum needed by any instruction ).

7+3pts

6+4pts


4 ( 9+4+12+10+8+6+5+8+6+4+8+4+6 90 points) 40 min.

Virtual memory:

4.1 VPN stands for ____________________________________.PPFN stands for _________________________________________________.PTBR stands for _________________________________________________.VIPT standing for __________________________________________ is _____________(better/worse) than PIPT standing for _____________________________________________.MMU standing for _________________________________

4.2 We learned that a Dirty bit is included in a page table entry to facilitate writing back that page to disc eventually. Is dirty bit included in every entry of every one of the A, B, C, and D tables? Yes / No

Is Presence bit included in every entry of every one of the four tables? Yes / No

If a process has been started for the first time, the O.S (operating system) which builds page tables on demand would start modestly with ___ (0/1) of A-table, ___ (0/1) of B-table, ___ (0/1) of C-table, and ___ (0/1) of D-table. Maximum possible number of B tables in the diagram above _______. With this maximum number of B tables, the minimum number of C tables possible are _______ and the minimum number of D tables possible are _______. Simultaneous indexing of all the four tables _________ (is/isn’t) possible.

4.3 While a pointer to a location in a 4GByte address space (of a byte-addressable processor) is 32 bits in size in general, if you are pointing to a 32-bit word location (such as 44 or 48 for example), the lower ____ bits are sure to be zero. This property is exploited in the (circle all applicable). (i) A-level table on the side (ii) B-level tables on the side (iii)C-level tables on the side

(iv)D-level tables on the sideto accommodate in a 32-bit entry, a _______________________ bit besides the pointer to the next level table. If that bit is a ______ (0 / 1), we declare page fault. Fields to hold dirty bit, protection bits, reference bits are provided _______________________________________________________________________ (in every entry in every table / only in the entries of ..).

9pts

A table16 entries

B tables8 entries

C tables4 entries

D tables4 entries

PageFrame

A B C D Page Offset4 3 2 2 11

4pts

8+4pts

8+2pts


4.4 In a 32-bit virtual address system, with a 8KB page size, state two word-addresses (in hex) that are next to each other but actually belong to different virtual pages. ________________________ Now state two other word addresses which belong to the same virtual page but they are at their maximum distance apart in their own virtual page. ___________________________________

4.5 Since VPN to PPFN translation happens _______________ (before / after) the cache control unit tries to locate the block in its data RAM, if there is a cache miss, _______(A / B).A. it is sure to find the block in the main memoryB. there is no guarantee that the block will be found in the main memory.

4.6 Dirty bit associated with the TAG of a Block-frame, when set, indicates (circle all applicable).A. that the page needs to be written back to the hard disk eventually.B. the dirty bit in the corresponding page table entry needs to be set. C. that the dirty bit in the corresponding TLB entry needs to be set.D. None of the above.

4.7 Consider a TLB with 960 entries (64 X 3 X5) which is not a power of 2. It ______ (can / cannot) be direct mapped TLB.It ______ (can / cannot) be set_associative mapped TLB.It ______ (can / cannot) be fully_associative mapped TLB.Explain with some more detailed __________________________________________________________________________________________________________________________________________________________________________________________________________

4.8 What comes out of the inner CPU is __________________________________ (Virtual address / physical address) where as, what comes out of the CPU chip is __________________________________ (Virtual address / physical address),which is based on the fact that the MMU is __________ (on the CPU chip / outside the CPU chip).

4.9 The main memory needs to be 4-way interleaved if the ___________ (cache/TLB/PT) ______ ____________________________________________________________________________

4.10 TLB entries are usually _________ (wider/narrower) compared to the page table entries because they ___________________ (contain/do not contain) the LHS (Left-hand side of the look up tables) __________________ (besides / but not) the RHS (Right-hand side of the look up table).

4.11 We used the term "mega virtual address space" to refer to _______________________________________________________________________________________________________________________________________________________________________________________

4.12 A 3-level page table as compared to a 2-level page has an advantage namely _____________________________________________________________________________________________but has a disadvantage namely ______________________________________________________________________________________________________________________________

8pts

3+3pts

5pts

8pts

6pts

4pts

8pts

4pts

4 +2pts

Stream #1

ID EX M1 M2 WB

beq lw sub

7-stage pipeline #1 7-stage pipeline #2 7-stage pipeline #3

Stream #1

ID EX M1 M2 WB

beq lw sub

Stream #1

ID EX M1 M2 WB

beq lw sub

Stream #2

ID EX M1 M2 WB

beq lw lw

Stream #2

ID EX M1 M2 WB

beq lw lw

Stream #2

ID EX M1 M2 WB

beq lw lwsub sub sub

Q#2.2.1

Stream #3

ID EX M1 M2 WB

add lw sub

7-stage pipeline #1 7-stage pipeline #2 7-stage pipeline #3

Stream #3

ID EX M1 M2 WB

add lw sub

Stream #3

ID EX M1 M2 WB

add lw sub

Stream #4

ID EX M1 M2 WB

add lw lw

Stream #4

ID EX M1 M2 WB

add lw lw

Stream #4

ID EX M1 M2 WB

add lw lwsub sub sub

Q#2.2.1

Stream #1

ID EX M WB

add lw sub

Original 5-stage pipeline 6-stage pipeline Student #1

Stream #1

ID EX M BWB WB

add lw sub

Stream #1

ID EX M WB AWB

add lw sub

6-stage pipeline Student #2Q#2.3

Stream #2

ID EX M WB

add lw sub

Original 5-stage pipeline 6-stage pipeline Student #1

Stream #2

ID EX M BWB WB

Stream #2

ID EX M WB AWB

6-stage pipeline Student #2

U add lw subU add lw subU

Stream #3

ID EX M WB

add lw sub

Stream #3

ID EX M BWB WB

Stream #3

ID EX M WB AWB

U add lw subU add lw subU

Q#2.3

ee457 midterm (~20%)...ee457 midterm (~20%) closed-book closed-notes exam; no cheat sheets;...

Documents