eec 216 lecture #10: ultra low voltage and subthreshold ...ramirtha/eec216/w09/lecture10.pdfr....
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EEC 216 Lecture #10:Ultra Low Voltage and
Subthreshold Circuit Design
Rajeevan AmirtharajahUniversity of California, Davis
R. Amirtharajah, EEC216 Winter 2009 4
Opportunities for Ultra Low Voltage
Moteiv Sky mote, 2006
• Battery Operated and Mobile Systems– Wireless sensors– RFID tags– Biomedical implants– Mobile Phones, internet devices, and
netbooks– Maximize operating lifetime for stored
energy (minimum energy operation)• Wall-plug and Rack Mounted Systems
– Power-down and sleep modes in servers
– Maintain state in on-chip caches, SRAM memory while minimizing leakage power
R. Amirtharajah, EEC216 Winter 2009 5
CMOS Delay and Power Dissipation
leakstaticcircuitshortdynamicTOT PPPPP +++= −
Total Power:
Voltage scaling decreases all power components, at expense of increasing circuit delay.
leakddstaticdd
frpeakddddL
IVIV
ftt
IVfVC
++
⎟⎟⎠
⎞⎜⎜⎝
⎛ ++=
22α
( )22 thddox
ddL
D
ddL
VVLWC
VCIVC
IVCt
−≈=
Δ=Δ μDelay:
R. Amirtharajah, EEC216 Winter 2009 6
Low Voltage CMOS Inverter Operation
Swanson and Meindl, JSSC 1972
• Thermal noise limit:
• Inverter gain limit:
• Equalized NMOS-PMOS off currents:
1004≈
qkT
mV
2008≈
qkT
mV
572≈
qnkT
mV
R. Amirtharajah, EEC216 Winter 2009 7
Supply Voltage Scaling With Technology Node
• From 2007 ITRS Roadmap
0
0.2
0.4
0.6
0.8
1
1.2
2007 2009 2011 2013 2015 2017 2019 2021
Year
VDD
(V
0
5
10
15
20
25
30
Leng
th (n
m
VDD (High Perf.)
VDD (Low Power)
MPU Physical Gate Length
R. Amirtharajah, EEC216 Winter 2009 8
Commercial Wireless Sensor Mote
Moteiv Sky mote, 2006Jiang, IPSN/SPOTS 2005
• Current sensor node: 70 mW all active, 17 μW idle• Power sources contribute significant volume and cost• Smaller system (1 cm3) desirable (less obtrusive military
sensor, implantable biomedical device)• Reduce power consumption, get energy from environment
R. Amirtharajah, EEC216 Winter 2009 9
Specific Opportunities for ULV Design• Extremely low power mixed-signal circuits
– Analog design without operational amplifiers
• Low voltage swing on-chip interconnects– Good current drive at low VDD desirable
• Power gates and cutoff devices to minimize leakage power during inactive state– Need steep subthreshold slope to limit leakage current when
blocks turned off
• Low voltage active mode and sleep mode memories, caches– Need reliable operation under variable VDD
• Low voltage standard cells– Operate at minimum energy point, balancing leakage and
dynamic power
R. Amirtharajah, EEC216 Winter 2009 10
Extremely Brief MOSFET Review
Triode:
“Classical” MOSFET model, will discuss deep submicron modifications as necessary
( ) ( )DSTGSox
D VVVLWCI λμ
+−= 12
2Saturation:
( ) ⎟⎟⎠
⎞⎜⎜⎝
⎛−−=
2
2DS
DSTGSoxDVVVV
LWCI μ
Subthreshold:⎟⎟
⎠
⎞
⎜⎜
⎝
⎛−=
−q
kTDS
qkTGS V
nV
SD eeII 1
R. Amirtharajah, EEC216 Winter 2009 11
Subthreshold Current Equation
( )DS
VnV
SD VeeII qkTDS
qkTGS
λ+⎟⎟
⎠
⎞
⎜⎜
⎝
⎛−=
−
11
• Is and n are empirical parameters
• Typically, often ranging around
• Usually want small subthreshold leakage for digital designs
– Define quality metric: inverse of rate of decline of current wrt VGS below VT
– Subthreshold slope factor S:
1≥n 5.1≈n
( )10lnq
kTnS =
R. Amirtharajah, EEC216 Winter 2009 12
Detailed Subthreshold Current Equation
( ) ⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎠⎞
⎜⎝⎛ −−⎟
⎠⎞
⎜⎝⎛ +−−=
kTqVVVVV
nkTqAI DS
DSTGSD exp1exp 0 ηγ
• VT0 = zero bias threshold voltage,
• μ0 = zero bias mobility
• Cox = gate oxide capacitance per unit area
• γ = linear body effect coefficient (small source voltage)
• η = DIBL coefficient
8.12
0 eq
kTLWCA ox ⎟⎟
⎠
⎞⎜⎜⎝
⎛= μ
R. Amirtharajah, EEC216 Winter 2009 13
Leakage Currents vs. Active Currents
1=A
1=B
Out
M0
M1
Ileak
• Iactive/Ileak (Ion/Ioff) ratio can be small in subthreshold
Ileak
Iactive
R. Amirtharajah, EEC216 Winter 2009 14
Degraded Output Levels
• Balance current ratio through sizing, limiting fanin
Vdd
VddVin
Vout
ideal
actual
0 V
VOH
VOL
R. Amirtharajah, EEC216 Winter 2009 15
Degraded Logic Levels Impact Functionality
D
Q
80=Clk
220=Clk
80=Clk mV
mV Driven by two inverters to intermediate voltage
• VDD = 0.3 V
Iactive
Ioff
mV
R. Amirtharajah, EEC216 Winter 2009 16
SRAM Cell Leakage Paths
BL BL
WL
0 1
• Leakage paths can degrade read and write noise margins
R. Amirtharajah, EEC216 Winter 2009 17
Circuit Design Summary
• Subthreshold design similar to ratioed ckt design– Must guarantee active currents sufficiently greater than
leakage currents to maintain valid logic levels– Degraded logic levels can cause failure in
combinational and sequential circuits– All circuits (esp. SRAMs) sensitive to VTH variation
• Be careful with subthreshold circuits– Consider worst case leakage situations (data
dependent) when analyzing Ion/Ioff ratio problems– Use nonminimum channel lengths, limit fanin– Watch sneak leakage paths through pass gates– Interrupt pass gate chains with static logic
16
Challenges for Ultra Low Voltage
• Device variability (within die, across dies, and across wafers)
– Variations in threshold voltage drastically affect critical circuit performance parameters
– Examples: Ion/Ioff ratios, gate delays, static memory noise margins, subthreshold slope for leakage limiting devices
• Noise and event tolerance– Approaching fundamental noise limit may decrease
reliability and MTTF– Limited charge storage on circuit nodes may increase
susceptibility to soft errors in both memory and logic
0 0.1 0.2 0.30
0.1
0.2
0.3
VIN
(V)
VO
UT (
V)
Sub-Vt Design Challenges
Sub-Vt static CMOS gates exhibit variation in logic levels (VOH, VOL)
Active
Leakage
on off
RDF
t
© 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE
From Kwong et al., ISSCC 08
0 0.1 0.2 0.30
0.1
0.2
0.3
VIN
(V)
VO
UT (
V)
0 1 2 30
0.1
0.2
0.3
Time (µµµµs)
Vo
lta
ge
(V
)
Sub-Vt Logic Functionality
Degraded logic levels adversely impact functionality
CLK
N2N3
N4Not completely off, causing functional
failure
CLKCLK N3
N4
N2,Q
© 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE
From Kwong et al., ISSCC 08
Sub-Vt Logic Design
Functional metric necessary to manage
sizing trade-off
0 0.1 0.20
0.1
0.2
VIN-NAND
, VOUT-NOR
VO
UT
-NA
ND,
VIN
-NO
R
NAND
NOR
0 0.1 0.20
0.1
0.2
VIN-NAND
, VOUT-NOR
VO
UT
-NA
ND,
VIN
-NO
R
Logic failure
NAND
NOR
NAND NOR
t
WLtVσ 1∝∝∝∝
© 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE
From Kwong et al., ISSCC 08
Sub-Vt Standard Cell Library
0.2 0.25 0.30
500
1000
VOH
(V)
Occu
rren
ces
0.2 0.25 0.30
5000
10000
VOH
(V)
Occu
rren
ces
0 0.1 0.2 0.30
1000
2000
VOL
(V)
Occu
rren
ces
t
Leakage
Active
Outliers
t
0 0.1 0.2 0.30
5000
10000
VOL
(V)
Occu
rren
ces
© 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE
From Kwong et al., ISSCC 08
Sub-Vt SRAM Challenges
Hold SNM Read SNM
Hold SNM preserved to low-voltages
NT NCNT NC
NC, NT (V)
0.2 0.4 0.6 0.8 1.00
NT
, N
C (
V)
0.2
0.4
0.6
0.8
1.0
0
NC, NT (V)
NT
, N
C (
V)
0.2
0.4
0.6
0.8
1.0
00.2 0.4 0.6 0.8 1.00
Read SNM degraded at low-voltages
WLWL
BLBL
© 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE
From Kwong et al., ISSCC 08
SRAM Architecture and Bit-Cell
Buffer eliminates read SNM limitationPeripheral assists allow sub-Vt writing and sensing
Based on Verma, ISSCC 2007
© 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE
From Kwong et al., ISSCC 08
Peripheral Assists
“0”
PCHRG
“1”
No sub-Vtleakage
VVDD
ReadWrite
“0”
“1” (64 Cells)
“1” (256 Cells)
“1” (256, 64 Cells)
RD
BL
Vo
ltag
e 0.3
0.4
0.2
0.1
0
10 20 30 40µs
6T Cell
VVDDWR
NTNC
0.3
0.2
0.1
0
Vo
lts
0.3
0.2
0.1
0
Vo
lts
10 12 14 16 18 20
10 12 14 16 18 20µs
NT NC
“1” “0”
VVDD
“1” “1”
WR
© 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE
From Kwong et al., ISSCC 08
Sub-Vt Timing Analysis Challenges
Order-of-magnitude higher delay variation in sub-Vt
Oc
cu
rre
nc
es
Occ
urr
en
ces
© 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE
From Kwong et al., ISSCC 08
0 200 4000
0.2
0.4
0.6
Mean delay [ns]
σσ σσ/ µµ µµ
(S
td.
de
v.
ov
er
me
an
)
Comprehensive Timing Simulations
Increasing mean delay
Delay (ns)Path #
Simulation of 30000 timing paths illustrates trends in sub-Vt delay variability
© 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE
From Kwong et al., ISSCC 08
Test-Chip Summary
Performance
1.36mm2SRAM
0.12mm2DC-DC Converter
Area
0.14mm2Logic
65nm CMOSProcess
VDD = 300mVMinimum
Functional VDD
VDD = 500mVMinimum
Energy Point
2.29mm
128Kb SRAM
array
DC-DC
converter
Core logic
(2 power domains)
1.8
6m
m
© 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE
From Kwong et al., ISSCC 08
17
Conclusions
• Many opportunities for ultra low voltage design exist– Energy Constrained Applications: wireless sensors,
mobile devices, biomedical implants
– Minimum Power Applications: sleep and minimum leakage modes in processors and memories
• Main challenge is device parameter variations– Threshold voltage variation severely impacts delays,
noise margins in logic and SRAM
• Very active area of circuits research– ISSCC 2009 Advanced Circuits Forum on Ultra Low
Voltage