eecc550 - shaaban #1 lec # 8 spring 2003 4-28-2003 main memory main memory generally utilizes...
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EECC550 - ShaabanEECC550 - Shaaban#1 Lec # 8 Spring 2003 4-28-2003
Main MemoryMain Memory• Main memory generally utilizes Dynamic RAM (DRAM),
which use a single transistor to store a bit, but require a periodic data refresh by reading every row (~every 8 msec).
• Static RAM may be used for main memory if the added expense, low density, high power consumption, and complexity is feasible (e.g. Cray Vector Supercomputers).
• Main memory performance is affected by:
– Memory latency: Affects cache miss penalty. Measured by:
• Access time: The time it takes between a memory access request is issued to main memory and the time the requested information is available to cache/CPU.
• Cycle time: The minimum time between requests to memory
(greater than access time in DRAM to allow address lines to be stable)
– Memory bandwidth: The maximum sustained data transfer rate between main memory and cache/CPU.
EECC550 - ShaabanEECC550 - Shaaban#2 Lec # 8 Spring 2003 4-28-2003
Logical DRAM Organization (16 Mbit)Logical DRAM Organization (16 Mbit)
Data In
Data Out
Column DecoderColumn Decoder
Sense Sense Amps & I/OAmps & I/O
Memory Memory ArrayArray(16,384 x 16,384)(16,384 x 16,384)
A0…A13A0…A130
…14DD
WWord Lineord Line Storage CellCell
Row
Dec
oder
Row
Dec
oder
Row/ColumnAddress
Control Signals:Row Access Strobe (RAS): Low to latch row addressColumn Address Strobe (CAS): Low to latch column addressWrite Enable (WE)Output Enable (OE)
EECC550 - ShaabanEECC550 - Shaaban#3 Lec # 8 Spring 2003 4-28-2003
Key DRAM Speed Parameters
• Row Access Strobe (RAS)Time:– Minimum time from RAS (Row Access Strobe) line falling
to the first valid data output.– A major component of memory latency and access time.– Only improves 5% every year.
• Column Access Strobe (CAS) Time/data transfer time:– The minimum time required to read additional data by
changing column address while keeping the same row address.
– Along with memory bus width, determines peak memory bandwidth.
EECC550 - ShaabanEECC550 - Shaaban#4 Lec # 8 Spring 2003 4-28-2003
Memory Hierarchy: MotivationMemory Hierarchy: Motivation• The gap between CPU performance and realistic (non-ideal) main memory
speed has been widening with higher performance CPUs creating performance bottlenecks for memory access instructions.
• The memory hierarchy is organized into several levels of memory or storage with the smaller, more expensive, and faster levels closer to the CPU: registers, then primary or Level 1 (L1) SRAM Cache, then possibly one or more secondary cache levels (L2, L3…), then DRAM main memory, then mass storage (virtual memory).
• Each level of the hierarchy is a subset of the level below: data found in a level is also found in the level below but at a lower speed.
• Each level maps addresses from a larger physical memory/storage level to a smaller level above it.
• This concept is greatly aided by the principal of locality both temporal and spatial which indicates that programs tend to reuse data and instructions that they have used recently or those stored in their vicinity leading to working set of a program.
EECC550 - ShaabanEECC550 - Shaaban#5 Lec # 8 Spring 2003 4-28-2003
From Technology TrendsFrom Technology Trends Capacity Speed (latency)
Logic: 2x in 3 years 2x in 3 years
DRAM: 4x in 3 years 2x in 10 years
Disk: 4x in 3 years 2x in 10 years
DRAM Generations
Year Size RAS (ns) CAS (ns) Cycle Time
1980 64 Kb 150-180 75 250 ns1983 256 Kb 120-150 50 220 ns1986 1 Mb 100-120 25 190 ns1989 4 Mb 80-100 20 165 ns1992 16 Mb 60-80 15 120 ns1996 64 Mb 50-70 12 110 ns1998 128 Mb 50-70 10 100 ns2000 256 Mb 45-65 7 90 ns2002 512 Mb 40-60 5 80 ns
8000:1 15:1 3:1 (Capacity) (~bandwidth) (Latency)
EECC550 - ShaabanEECC550 - Shaaban#6 Lec # 8 Spring 2003 4-28-2003
Memory Hierarchy: MotivationMemory Hierarchy: MotivationProcessor-Memory (DRAM) Performance GapProcessor-Memory (DRAM) Performance Gap
µProc60%/yr.
DRAM7%/yr.
1
10
100
1000198
0198
1 198
3198
4198
5 198
6198
7198
8198
9199
0199
1 199
2199
3199
4199
5199
6199
7199
8 199
9200
0
DRAM
CPU
198
2
Processor-MemoryPerformance Gap:(grows 50% / year)
Per
form
ance
EECC550 - ShaabanEECC550 - Shaaban#7 Lec # 8 Spring 2003 4-28-2003
Processor-DRAM Performance Gap Impact Processor-DRAM Performance Gap Impact • To illustrate the performance impact, assume a single-issue pipelined RISC
CPU with ideal CPI = 1 using non-ideal memory. • Ignoring other factors, the minimum cost of a full memory access in terms of
number of wasted CPU cycles:
CPU CPU Memory Minimum CPU cycles or Year speed cycle Access instructions wasted MHZ ns ns
1986: 8 125 190 190/125 - 1 = 0.51989: 33 30 165 165/30 -1 = 4.51992: 60 16.6 120 120/16.6 -1 = 6.21996: 200 5 110 110/5 -1 = 211998: 300 3.33 100 100/3.33 -1 = 292000: 1000 1 90 90/1 - 1 = 892002: 2000 .5 80 80/.5 - 1 = 159
EECC550 - ShaabanEECC550 - Shaaban#8 Lec # 8 Spring 2003 4-28-2003
Memory Hierarchy: MotivationMemory Hierarchy: Motivation
The Principle Of LocalityThe Principle Of Locality• Programs usually access a relatively small portion of their address
space (instructions/data) at any instant of time (program working set).
• Two Types of locality:
– Temporal Locality: If an item is referenced, it will tend to be referenced again soon.
– Spatial locality: If an item is referenced, items whose addresses are close will tend to be referenced soon.
• The presence of locality in program behavior, makes it possible to satisfy a large percentage of program access needs using memory levels with much less capacity than program address space.
EECC550 - ShaabanEECC550 - Shaaban#9 Lec # 8 Spring 2003 4-28-2003
Levels of The Memory HierarchyLevels of The Memory Hierarchy
Part of The On-chip CPU Datapath 16-256 Registers
One or more levels (Static RAM):Level 1: On-chip 16-64K Level 2: On or Off-chip 128-512KLevel 3: Off-chip 128K-8M
Registers
Cache
Main Memory
Magnetic Disc
Optical Disk or Magnetic Tape
Farther away from The CPU
Lower Cost/Bit
Higher Capacity
Increased AccessTime/Latency
Lower ThroughputDynamic RAM (DRAM) 16M-16G
Interface:SCSI, RAID, IDE, 13944G-100G
EECC550 - ShaabanEECC550 - Shaaban#10 Lec # 8 Spring 2003 4-28-2003
A Typical Memory HierarchyA Typical Memory Hierarchy ((With Two Levels of Cache)With Two Levels of Cache)
Control
Datapath
VirtualMemory,
SecondaryStorage(Disk)
Processor
Registers
MainMemory(DRAM)
SecondLevelCache
(SRAM)L2
1s 10,000,000s
(10s ms)
Speed (ns): 10s 100s
100s GBsSize (bytes): KBs MBs
TertiaryStorage(Tape)
10,000,000,000s (10s sec)
TBs
On-ChipLevel OneCache L1
Larger CapacityFaster
On or off Chip
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Levels of The Memory HierarchyLevels of The Memory Hierarchy
EECC550 - ShaabanEECC550 - Shaaban#12 Lec # 8 Spring 2003 4-28-2003
SRAM Organization ExampleSRAM Organization Example 4 words X 3 bits each4 words X 3 bits each
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Memory Hierarchy OperationMemory Hierarchy Operation If an instruction or operand is required by the CPU, the levels of the
memory hierarchy are searched for the item starting with the level closest to the CPU (Level 1, L1 cache):
– If the item is found, it’s delivered to the CPU resulting in a cache hit without searching lower levels.
– If the item is missing from an upper level, resulting in a cache miss, then the level just below is searched.
– For systems with several levels of cache, the search continues with cache level 2, 3 etc.
– If all levels of cache report a miss then main memory is accessed for the item.
• CPU cache memory: Managed by hardware.
– If the item is not found in main memory resulting in a page fault, then disk (virtual memory) is accessed for the item.
• Memory disk: Mainly managed by the operating system with hardware support.
EECC550 - ShaabanEECC550 - Shaaban#14 Lec # 8 Spring 2003 4-28-2003
Memory Hierarchy: TerminologyMemory Hierarchy: Terminology• A Block: The smallest unit of information transferred between two
levels.
• Hit: Item is found in some block in the upper level (example: Block X)
– Hit Rate: The fraction of memory access found in the upper level.
– Hit Time: Time to access the upper level which consists of
RAM access time + Time to determine hit/miss
• Miss: Item needs to be retrieved from a block in the lower level (Block Y)
– Miss Rate = 1 - (Hit Rate)
– Miss Penalty: Time to replace a block in the upper level +
Time to deliver the block the processor
• Hit Time << Miss Penalty
Lower LevelMemoryUpper Level
MemoryTo Processor
From ProcessorBlk X
Blk Y
EECC550 - ShaabanEECC550 - Shaaban#15 Lec # 8 Spring 2003 4-28-2003
Cache ConceptsCache Concepts• Cache is the first level of the memory hierarchy once the address leaves
the CPU and is searched first for the requested data.
• If the data requested by the CPU is present in the cache, it is retrieved from cache and the data access is a cache hit otherwise a cache miss and data must be read from main memory.
• On a cache miss a block of data must be brought in from main memory to into a cache block frame to possibly replace an existing cache block.
• The allowed block addresses where blocks can be mapped into cache from main memory is determined by cache placement strategy.
• Locating a block of data in cache is handled by cache block identification mechanism.
• On a cache miss the cache block being removed is handled by the block replacement strategy in place.
• When a write to cache is requested, a number of main memory update strategies exist as part of the cache write policy.
EECC550 - ShaabanEECC550 - Shaaban#16 Lec # 8 Spring 2003 4-28-2003
Cache Design & Operation IssuesCache Design & Operation IssuesQ1: Where can a block be placed cache?
(Block placement strategy & Cache organization)• Fully Associative, Set Associative, Direct Mapped.
Q2: How is a block found if it is in cache?
(Block identification)• Tag/Block.
Q3: Which block should be replaced on a miss? (Block replacement policy)
• Random, Least Recently Used (LRU).
Q4: What happens on a write? (Cache write policy)
• Write through, write back.
EECC550 - ShaabanEECC550 - Shaaban#17 Lec # 8 Spring 2003 4-28-2003
We will examineWe will examine:
• Cache Placement StrategiesCache Placement Strategies– Cache Organization.Cache Organization.
• Locating A Data Block in Cache.Locating A Data Block in Cache.
• Cache Replacement Policy.Cache Replacement Policy.
• What happens on cache Reads/Writes.What happens on cache Reads/Writes.
• Cache write strategies.Cache write strategies.
• Cache write miss policies.Cache write miss policies.
• Cache performance.Cache performance.
EECC550 - ShaabanEECC550 - Shaaban#18 Lec # 8 Spring 2003 4-28-2003
Cache Organization & Placement StrategiesCache Organization & Placement StrategiesPlacement strategies or mapping of a main memory data block onto cache block frame addresses divide cache into three organizations:
1 Direct mapped cache: A block can be placed in one location only, given by (mapping function):
(Block address) MOD (Number of blocks in cache)
2 Fully associative cache: A block can be placed anywhere in cache (no mapping function).
3 Set associative cache: A block can be placed in a restricted set of places, or cache block frames. A set is a group of block frames in the cache. A block is first mapped onto the set and then it can be placed anywhere within the set. The set in this case is chosen by:
(Block address) MOD (Number of sets in cache)
If there are n blocks in a set the cache placement is called n-way set-associative.
EECC550 - ShaabanEECC550 - Shaaban#19 Lec # 8 Spring 2003 4-28-2003
Cache Organization: Cache Organization: Direct Mapped CacheDirect Mapped Cache
0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 0 1
00
0
C a c h e
M e m o ry
00
1
01
0
01
1
10
0
10
1
11
0
11
1
A block can be placed in one location only, given by: (Block address) MOD (Number of blocks in cache) In this case, mapping function: (Block address) MOD (8)
32 memory blockscacheable
8 cache block frames
Example: 29 MOD 8 = 5(11101) MOD (1000) = 101
EECC550 - ShaabanEECC550 - Shaaban#20 Lec # 8 Spring 2003 4-28-2003
4KB Direct Mapped 4KB Direct Mapped Cache ExampleCache Example
A d d re s s ( s h o w in g b it p o s i t io n s )
2 0 1 0
B y te
o ffs e t
V a l id T a g D a taIn d e x
0
1
2
1 0 2 1
1 0 2 2
1 0 2 3
T a g
In d e x
H i t D a ta
2 0 3 2
3 1 3 0 1 3 1 2 1 1 2 1 0
1K = 1024 BlocksEach block = one word
Can cache up to232 bytes = 4 GBof memory
Mapping function:
Cache Block frame number =(Block address) MOD (1024)
Index fieldTag field
Block offset = 2 bits
Block Address = 30 bits
Tag = 20 bits Index = 10 bits
EECC550 - ShaabanEECC550 - Shaaban#21 Lec # 8 Spring 2003 4-28-2003
64KB Direct Mapped Cache Example64KB Direct Mapped Cache ExampleA d d re s s (s ho w in g b it p o s ition s)
1 6 1 2 B yte
o ffs e t
V T a g D a ta
H it D a ta
1 6 32
4 K
e n tr ie s
1 6 b its 12 8 b i ts
M u x
3 2 3 2 3 2
2
3 2
B lo c k o f fs e tIn d ex
T ag
3 1 16 1 5 4 3 2 1 04K= 4096 blocksEach block = four words = 16 bytes
Can cache up to232 bytes = 4 GBof memory
Mapping Function: Cache Block frame number = (Block address) MOD (4096)Larger blocks take better advantage of spatial locality
Index fieldTag field
Word select
Block Address = 28 bits
Tag = 16 bits Index = 12 bits Block offset = 4 bits
EECC550 - ShaabanEECC550 - Shaaban#22 Lec # 8 Spring 2003 4-28-2003
T a g D a ta T a g D a ta T a g D a ta T a g D a ta T a g D a ta T a g D a ta T a g D a ta T a g D a ta
E ig h t - w a y s e t a s s o c ia t iv e ( fu l ly a s s o c ia t iv e )
T a g D a t a T a g D a ta T a g D a ta T a g D a ta
F o u r - w a y s e t a s s o c ia t iv e
S e t
0
1
T a g D a t a
O n e - w a y s e t a s s o c ia t iv e
(d i re c t m a p p e d )
B lo c k
0
7
1
2
3
4
5
6
T a g D a ta
T w o - w a y s e t a s s o c ia t iv e
S e t
0
1
2
3
T a g D a ta
Cache Organization: Cache Organization: Set Associative CacheSet Associative Cache
EECC550 - ShaabanEECC550 - Shaaban#23 Lec # 8 Spring 2003 4-28-2003
Cache Organization ExampleCache Organization Example
EECC550 - ShaabanEECC550 - Shaaban#24 Lec # 8 Spring 2003 4-28-2003
Locating A Data Block in CacheLocating A Data Block in Cache• Each block frame in cache has an address tag.
• The tags of every cache block that might contain the required data are checked or searched in parallel.
• A valid bit is added to the tag to indicate whether this entry contains a valid address.
• The address from the CPU to cache is divided into:
– A block address, further divided into:
• An index field to choose a block set in cache.
(no index field when fully associative).
• A tag field to search and match addresses in the selected set.
– A block offset to select the data from the block.
Block Address BlockOffsetTag Index
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Address Field SizesAddress Field Sizes
Block Address BlockOffsetTag Index
Block offset size = log2(block size)
Index size = log2(Total number of blocks/associativity)
Tag size = address size - index size - offset sizeTag size = address size - index size - offset size
Physical Address Generated by CPU
Mapping function:
Cache set or block frame number = Index = = (Block Address) MOD (Number of Sets)
Number of Sets
EECC550 - ShaabanEECC550 - Shaaban#26 Lec # 8 Spring 2003 4-28-2003
4K Four-Way Set Associative Cache:4K Four-Way Set Associative Cache:MIPS Implementation ExampleMIPS Implementation Example
Ad dress
2 2 8
V TagIndex
0
1
2
253
254
255
D ata V Tag D ata V Tag D ata V Tag D ata
3 22 2
4 - to - 1 m ultip lexo r
H it D a ta
123891011123 031 0
Index Field(8 bits)
TagField (22 bits)
1024 block framesEach block = one word4-way set associative256 sets
Can cache up to232 bytes = 4 GBof memory
Block Address = 30 bits
Tag = 22 bits Index = 8 bits Block offset = 2 bits
Mapping Function: Cache Set Number = (Block address) MOD (256)
Block Offset Field(2 bits)
EECC550 - ShaabanEECC550 - Shaaban#27 Lec # 8 Spring 2003 4-28-2003
Cache Organization/Addressing ExampleCache Organization/Addressing Example
• Given the following:– A single-level L1 cache with 128 cache block frames
• Each block frame contains four words (16 bytes)
– 16-bit memory addresses to be cached (64K bytes main memory or 4096 memory blocks)
• Show the cache organization/mapping and cache address fields for:
• Fully Associative cache.
• Direct mapped cache.
• 2-way set-associative cache.
EECC550 - ShaabanEECC550 - Shaaban#28 Lec # 8 Spring 2003 4-28-2003
Cache Example: Fully Associative CaseCache Example: Fully Associative Case
Block offset = 4 bits
Block Address = 12 bits
Tag = 12 bits
All 128 tags mustbe checked in parallelby hardware to locate a data block
V
V
V
Valid bit
Mapping Function = none
EECC550 - ShaabanEECC550 - Shaaban#29 Lec # 8 Spring 2003 4-28-2003
Cache Example: Direct Mapped CaseCache Example: Direct Mapped Case
Block offset = 4 bits
Block Address = 12 bits
Tag = 5 bits Index = 7 bits Main Memory
Only a single tag mustbe checked in parallelto locate a data block
V
Valid bit
V
V
V
Mapping Function: Cache Block frame number = Index = (Block address) MOD (128)
EECC550 - ShaabanEECC550 - Shaaban#30 Lec # 8 Spring 2003 4-28-2003
Block offset = 4 bits
Block Address = 12 bits
Tag = 6 bits Index = 6 bits
Cache Example: 2-Way Set-AssociativeCache Example: 2-Way Set-Associative
Main Memory
Two tags in a set mustbe checked in parallelto locate a data block
Valid bits not shown
Mapping Function: Cache Set Number = Index = (Block address) MOD (64)
EECC550 - ShaabanEECC550 - Shaaban#31 Lec # 8 Spring 2003 4-28-2003
Calculating Number of Cache Bits NeededCalculating Number of Cache Bits Needed• How many total bits are needed for a direct- mapped cache with 64 KBytes of
data and one word blocks, assuming a 32-bit address?
– 64 Kbytes = 16 K words = 214 words = 214 blocks– Block size = 4 bytes => offset size = 2 bits, – #sets = #blocks = 214 => index size = 14 bits– Tag size = address size - index size - offset size = 32 - 14 - 2 = 16 bits – Bits/block = data bits + tag bits + valid bit = 32 + 16 + 1 = 49– Bits in cache = #blocks x bits/block = 214 x 49 = 98 Kbytes
• How many total bits would be needed for a 4-way set associative cache to store the same amount of data?
– Block size and #blocks does not change.– #sets = #blocks/4 = (214)/4 = 212 => index size = 12 bits– Tag size = address size - index size - offset = 32 - 12 - 2 = 18 bits– Bits/block = data bits + tag bits + valid bit = 32 + 18 + 1 = 51– Bits in cache = #blocks x bits/block = 214 x 51 = 102 Kbytes
• Increase associativity => increase bits in cache
EECC550 - ShaabanEECC550 - Shaaban#32 Lec # 8 Spring 2003 4-28-2003
Calculating Cache Bits NeededCalculating Cache Bits Needed• How many total bits are needed for a direct- mapped cache with 64
KBytes of data and 8 word blocks, assuming a 32-bit address (it can cache 232 bytes in memory)?
– 64 Kbytes = 214 words = (214)/8 = 211 blocks– block size = 32 bytes
=> offset size = block offset + byte offset = 5 bits,
– #sets = #blocks = 211 => index size = 11 bits
– tag size = address size - index size - offset size = 32 - 11 - 5 = 16 bits–
– bits/block = data bits + tag bits + valid bit = 8 x 32 + 16 + 1 = 273 bits
– bits in cache = #blocks x bits/block = 211 x 273 = 68.25 Kbytes
• Increase block size => decrease bits in cache.
EECC550 - ShaabanEECC550 - Shaaban#33 Lec # 8 Spring 2003 4-28-2003
Cache Replacement PolicyCache Replacement Policy• When a cache miss occurs the cache controller may have to
select a block of cache data to be removed from a cache block frame and replaced with the requested data, such a block is selected by one of two methods:
– Random: • Any block is randomly selected for replacement providing
uniform allocation.
• Simple to build in hardware.
• The most widely used cache replacement strategy.
– Least-recently used (LRU): • Accesses to blocks are recorded and and the block
replaced is the one that was not used for the longest period of time.
• LRU is expensive to implement, as the number of blocks to be tracked increases, and is usually approximated.
EECC550 - ShaabanEECC550 - Shaaban#34 Lec # 8 Spring 2003 4-28-2003
Cache Read/Write OperationsCache Read/Write Operations• Statistical data suggest that reads (including instruction
fetches) dominate processor cache accesses (writes account for 25% of data cache traffic).
• In cache reads, a block is read at the same time while the tag is being compared with the block address. If the read is a hit the data is passed to the CPU, if a miss it ignores it.
• In cache writes, modifying the block cannot begin until the tag is checked to see if the address is a hit.
• Thus in cache writes, tag checking cannot take place in parallel, and only the specific data requested by the CPU can be modified.
• Cache is classified according to the write and memory update strategy in place as: write through, or write back.
EECC550 - ShaabanEECC550 - Shaaban#35 Lec # 8 Spring 2003 4-28-2003
Cache Write StrategiesCache Write Strategies1 Write Though: Data is written to both the cache block and to
a block of main memory.– The lower level always has the most updated data; an important
feature for I/O and multiprocessing.– Easier to implement than write back.– A write buffer is often used to reduce CPU write stall while data is
written to memory.
2 Write back: Data is written or updated only to the cache block frame. The modified cache block is written to main memory when it’s being replaced from cache.
– Writes occur at the speed of cache.– A status bit called a dirty bit, is used to indicate whether the block
was modified while in cache; if not the block is not written to main memory.
– Uses less memory bandwidth than write through.
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Cache Write Miss PolicyCache Write Miss Policy• Since data is usually not needed immediately on a write miss
two options exist on a cache write miss:
Write Allocate:
The cache block is loaded on a write miss followed by write hit actions.
No-Write Allocate:
The block is modified in the lower level (lower cache level, or main
memory) and not loaded into cache.
While any of the above two write miss policies can be used with either write back or write through:
• Write back caches use write allocate to capture subsequent writes to the block in cache.
• Write through caches usually use no-write allocate since subsequent writes still have to go to memory.
EECC550 - ShaabanEECC550 - Shaaban#37 Lec # 8 Spring 2003 4-28-2003
Miss Rates for Caches with Different Size, Miss Rates for Caches with Different Size, Associativity & Replacement AlgorithmAssociativity & Replacement Algorithm
Sample DataSample Data
Associativity: 2-way 4-way 8-way
Size LRU Random LRU Random LRURandom
16 KB 5.18% 5.69% 4.67% 5.29% 4.39% 4.96%
64 KB 1.88% 2.01% 1.54% 1.66% 1.39% 1.53%
256 KB 1.15% 1.17% 1.13% 1.13% 1.12% 1.12%
EECC550 - ShaabanEECC550 - Shaaban#38 Lec # 8 Spring 2003 4-28-2003
Unified vs. Separate Level 1 CacheUnified vs. Separate Level 1 Cache• Unified Level 1 Cache (Princeton Memory Architecture).
A single level 1 cache is used for both instructions and data.
• Separate instruction/data Level 1 caches (Harvard Memory Architecture):
The level 1 (L1) cache is split into two caches, one for instructions (instruction cache, L1 I-cache) and the other for data (data cache, L1 D-cache).
Control
Datapath
Processor
Registers
UnifiedLevel OneCache L1
Control
Datapath
Processor
Registers
L1
I-cache
L1
D-cache
Unified Level 1 Cache (Princeton Memory Architecture)
Separate Level 1 Caches (Harvard Memory Architecture)
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Cache Performance:Average Memory Access Time (AMAT), Memory Stall cycles
• The Average Memory Access Time (AMAT): The number of cycles required to complete an average memory access request by the CPU.
• Memory stall cycles per memory access: The number of stall cycles added to CPU execution cycles for one memory access.
• For ideal memory: AMAT = 1 cycle, this results in zero memory stall cycles.
• Memory stall cycles per average memory access = (AMAT -1)
• Memory stall cycles per average instruction =
Memory stall cycles per average memory access
x Number of memory accesses per instruction
= (AMAT -1 ) x ( 1 + fraction of loads/stores)
Instruction Fetch
EECC550 - ShaabanEECC550 - Shaaban#40 Lec # 8 Spring 2003 4-28-2003
Cache PerformanceCache PerformancePrinceton (Princeton (Unified L1) Memory ArchitectureMemory Architecture
For a CPU with a single level (L1) of cache for both instructions
and data (Princeton memory architecture) and no stalls for
cache hits:
CPU time = (CPU execution clock cycles +
Memory stall clock cycles) x clock cycle time
Memory stall clock cycles = (Reads x Read miss rate x Read miss penalty) + (Writes x Write miss rate x Write miss penalty)
If write and read miss penalties are the same:
Memory stall clock cycles = Memory accesses x Miss rate x Miss penalty
With ideal memory
EECC550 - ShaabanEECC550 - Shaaban#41 Lec # 8 Spring 2003 4-28-2003
Cache PerformanceCache PerformancePrinceton Memory ArchitecturePrinceton Memory Architecture
CPUtime = Instruction count x CPI x Clock cycle time
CPIexecution = CPI with ideal memory
CPI = CPIexecution + Mem Stall cycles per instruction
CPUtime = Instruction Count x (CPIexecution +
Mem Stall cycles per instruction) x Clock cycle time
Mem Stall cycles per instruction = Mem accesses per instruction x Miss rate x Miss penalty
CPUtime = IC x (CPIexecution + Mem accesses per instruction x
Miss rate x Miss penalty) x Clock cycle time
Misses per instruction = Memory accesses per instruction x Miss rate
CPUtime = IC x (CPIexecution + Misses per instruction x Miss penalty) x
Clock cycle time
EECC550 - ShaabanEECC550 - Shaaban#42 Lec # 8 Spring 2003 4-28-2003
Memory Access TreeFor Unified Level 1 Cache
CPU Memory Access
L1 Miss: % = (1- Hit rate) = (1-H1) Access time = M + 1 Stall cycles per access = M x (1-H1)
L1 Hit: % = Hit Rate = H1 Access Time = 1Stalls= H1 x 0 = 0 ( No Stall)
L1
AMAT = H1 x 1 + (1 -H1 ) x (M+ 1) = 1 + M x ( 1 -H1)
Stall Cycles Per Memory Access = AMAT - 1 = M x (1 -H1)Mem Stall cycles per instruction = Mem accesses per instruction x Stall cycles per memory access
M = Miss PenaltyH1 = Level 1 Hit Rate1- H1 = Level 1 Miss Rate
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Cache Performance ExampleCache Performance Example• Suppose a CPU executes at Clock Rate = 200 MHz (5 ns per cycle) with a
single level of cache (unified).
• CPIexecution = 1.1
• Instruction mix: 50% arith/logic, 30% load/store, 20% control• Assume a cache miss rate of 1.5% and a miss penalty of 50 cycles.
CPI = CPIexecution + mem stalls per instruction
Mem Stalls per instruction =
Mem accesses per instruction x Miss rate x Miss penalty
Mem accesses per instruction = 1 + .3 = 1.3
Mem Stalls per instruction = 1.3 x .015 x 50 = 0.975
CPI = 1.1 + .975 = 2.075
The CPU with ideal cache (no misses) is 2.075/1.1 = 1.88 times faster
Instruction fetch Load/store
EECC550 - ShaabanEECC550 - Shaaban#44 Lec # 8 Spring 2003 4-28-2003
Cache Performance ExampleCache Performance Example• Suppose for the previous example we double the clock rate to
400 MHZ, how much faster is this machine, assuming similar miss rate, instruction mix?
• Since memory speed is not changed, the miss penalty takes more CPU cycles:
Miss penalty = 50 x 2 = 100 cycles.
CPI = 1.1 + 1.3 x .015 x 100 = 1.1 + 1.95 = 3.05
Speedup = (CPIold x Cold)/ (CPInew x Cnew)
= 2.075 x 2 / 3.05 = 1.36
The new machine is only 1.36 times faster rather than 2 times faster due to the increased effect of cache misses.
CPUs with higher clock rate, have more cycles per cache miss and more
memory impact on CPI.
EECC550 - ShaabanEECC550 - Shaaban#45 Lec # 8 Spring 2003 4-28-2003
Cache PerformanceCache PerformanceHarvard Memory ArchitectureHarvard Memory Architecture
For a CPU with separate level one (L1) caches for instructions
and data (Harvard memory architecture) and no stalls for
cache hits:CPUtime = Instruction count x CPI x Clock cycle time
CPI = CPIexecution + Mem Stall cycles per instruction
CPUtime = Instruction Count x (CPIexecution +
Mem Stall cycles per instruction) x Clock cycle time
Mem Stall cycles per instruction = Instruction Fetch Miss rate x Miss Penalty + Data Memory Accesses Per Instruction x Data Miss Rate x Miss Penalty
EECC550 - ShaabanEECC550 - Shaaban#46 Lec # 8 Spring 2003 4-28-2003
Memory Access TreeFor Separate Level 1 Caches
CPU Memory Access
L1
Instruction Data
Data L1 Miss:Access Time : M + 1Stalls per access: % data x (1 - Data H1 ) x M
Data L1 Hit:Access Time: 1 Stalls = 0
Instruction L1 Hit:Access Time = 1Stalls = 0
Instruction L1 Miss:Access Time = M + 1Stalls Per access
%instructions x (1 - Instruction H1 ) x M
Stall Cycles Per Memory Access = % Instructions x ( 1 - Instruction H1 ) x M + % data x (1 - Data H1 ) x M
AMAT = 1 + Stall Cycles per access
Mem Stall cycles per instruction = Mem accesses per instruction x Stall cycles per memory access
EECC550 - ShaabanEECC550 - Shaaban#47 Lec # 8 Spring 2003 4-28-2003
Cache Performance ExampleCache Performance Example• Suppose a CPU uses separate level one (L1) caches for instructions and data (Harvard memory
architecture) with different miss rates for instruction and data access:
– A cache hit incurs no stall cycles while a cache miss incurs 200 stall cycles for both memory reads and writes.
– CPIexecution = 1.1
– Instruction mix: 50% arith/logic, 30% load/store, 20% control– Assume a cache miss rate of 0.5% for instruction fetch and a cache data miss rate of 6%. – A cache hit incurs no stall cycles while a cache miss incurs 200 stall cycles for both memory reads and
writes. Find the resulting CPI using this cache? How much faster is the CPU with ideal memory?
CPI = CPIexecution + mem stalls per instruction
Mem Stall cycles per instruction = Instruction Fetch Miss rate x Miss Penalty +
Data Memory Accesses Per Instruction x Data Miss Rate x Miss Penalty
Mem Stall cycles per instruction = 0.5/100 x 200 + 0.3 x 6/100 x 200 = 1 + 3.6 = 4.6
CPI = CPIexecution + mem stalls per instruction = 1.1 + 4.6 = 5.7
The CPU with ideal cache (no misses) is 5.7/1.1 = 5.18 times faster
With no cache the CPI would have been = 1.1 + 1.3 X 200 = 261.1 !!
EECC550 - ShaabanEECC550 - Shaaban#48 Lec # 8 Spring 2003 4-28-2003
Improving Cache Performance:Improving Cache Performance:
2 Levels of Cache: L2 Levels of Cache: L11, L, L22
CPU
L1 Cache
L2 Cache
Main Memory
Hit Rate= H1, Hit time = 1 cycle (No Stall)
Hit Rate= H2, Hit time = T2 cycles
Memory access penalty, M
EECC550 - ShaabanEECC550 - Shaaban#49 Lec # 8 Spring 2003 4-28-2003
Miss Rates For Multi-Level CachesMiss Rates For Multi-Level Caches• Local Miss Rate: This rate is the number of misses in a cache
level divided by the number of memory accesses to this level. Local Hit Rate = 1 - Local Miss Rate
• Global Miss Rate: The number of misses in a cache level divided by the total number of memory accesses generated by the CPU.
• Since level 1 receives all CPU memory accesses, for level 1:
– Local Miss Rate = Global Miss Rate = 1 - H1
• For level 2 since it only receives those accesses missed in 1:
– Local Miss Rate = Miss rateL2= 1- H2
– Global Miss Rate = Miss rateL1 x Miss rateL2
= (1- H1) x (1 - H2)
EECC550 - ShaabanEECC550 - Shaaban#50 Lec # 8 Spring 2003 4-28-2003
CPUtime = IC x (CPIexecution + Mem Stall cycles per instruction) x C
Mem Stall cycles per instruction = Mem accesses per instruction x Stall cycles per access
• For a system with 2 levels of cache, assuming no penalty when found in L1 cache:
Stall cycles per memory access =
[miss rate L1] x [ Hit rate L2 x Hit time L2
+ Miss rate L2 x Memory access penalty) ] =
(1-H1) x H2 x T2 + (1-H1)(1-H2) x M
2-Level Cache Performance 2-Level Cache Performance
L1 Miss, L2 HitL1 Miss, L2 Miss: Must Access Main Memory
EECC550 - ShaabanEECC550 - Shaaban#51 Lec # 8 Spring 2003 4-28-2003
2-Level Cache Performance 2-Level Cache Performance Memory Access TreeMemory Access Tree
CPU Stall Cycles Per Memory AccessCPU Stall Cycles Per Memory Access
CPU Memory Access
L1 Miss: % = (1-H1)
L1 Hit:Stalls= H1 x 0 = 0(No Stall)
L2 Miss: Stalls= (1-H1)(1-H2) x M
L2 Hit:(1-H1) x H2 x T2
Stall cycles per memory access = (1-H1) x H2 x T2 + (1-H1)(1-H2) x MMem Stall cycles per instruction = Mem accesses per instruction x Stall cycles per access
L1
L2
EECC550 - ShaabanEECC550 - Shaaban#52 Lec # 8 Spring 2003 4-28-2003
Two-Level Cache ExampleTwo-Level Cache Example• CPU with CPIexecution = 1.1 running at clock rate = 500 MHZ
• 1.3 memory accesses per instruction.• L1 cache operates at 500 MHZ with a miss rate of 5%
• L2 cache operates at 250 MHZ with local miss rate 40%, (T2 = 2 cycles)
• Memory access penalty, M = 100 cycles. Find CPI.
CPI = CPIexecution + Mem Stall cycles per instruction
With No Cache, CPI = 1.1 + 1.3 x 100 = 131.1
With single unified L1, CPI = 1.1 + 1.3 x .05 x 100 = 7.6Mem Stall cycles per instruction = Mem accesses per instruction x Stall cycles per access
Stall cycles per memory access = (1-H1) x H2 x T2 + (1-H1)(1-H2) x M
= .05 x .6 x 2 + .05 x .4 x 100
= .06 + 2 = 2.06Mem Stall cycles per instruction = Mem accesses per instruction x Stall cycles per access
= 2.06 x 1.3 = 2.678
CPI = 1.1 + 2.678 = 3.778
Speedup = 7.6/3.778 = 2