eecs 150 components & design techniques for digital systems...

UC Regents Spring 2009 © UCBEECS 150 L28: Graphics Processors

2009-4-30John Lazzaro

(www.cs.berkeley.edu/~lazzaro)

EECS 150 Components & Design Techniques

For Digital Systems

Lecture 28: Graphics Processors

www-inst.eecs.berkeley.edu/~cs150/

TAs: CS 194-6 alums - Chris, Ilia, and Chen

Play

1


Today: Graphics Processors

Computer Graphics. A brief introduction to “the pipeline”.

Stream Processing. Casting the graphics pipeline into hardware.

Unified Pipelines. GeForce 8800,from Nvidia, introduced in 2006.

Larrabee. Intel multi-core graphics architecture, SIGGRAPH 2008.

2


Personal computer graphics architecture

Case Study: Mac Mini (PowerPC edition)

3


Personal computer graphics architecture

4


Figure 2-1 Block diagram

167 MHzMaxBus

12 MbpsUSB

PCI bus

BootROM

USB 2.0 port (480 Mbps)


PCI USB 2.0controller

DDR SDRAMDIMM slot

32 MBDDR RAM

DVI/VGA/composite/S-videooutput port

Ethernet port10/100 Mbps

FireWire 400 port

AGP 4Xbus

167 MHzMemory

bus

PMUpower controller

Powerbutton Fan

Opticaldrive

UltraATA/100

bus

Device 0

Device 1

Headphone/audio line-out jack

Hard diskdrive

Radeon9200

graphics IC

Audiocodec

EthernetPHY

FireWirePHY

PowerPC G4microprocessor

(L2 cache: 512K 1:1)

AirPort Extreme

I2S

I2S

I2C

BluetoothModem port

Modem module

Data pumpand DAA

Built-inspeaker

Intrepidmemorycontrollerand I/Odevice

controller

Main ICs and Buses

The architecture of Mac mini is designed around the PowerPC G4 microprocessor and the Intrepidmemory and I/O device controller. The Intrepid occupies the center of the block diagram.

The MaxBus connects the PowerPC G4 microprocessor to the Intrepid ASIC. The MaxBus has 64 datalines, 32 address lines, and a bus clock speed of 167 MHz. The Intrepid ASIC has other buses thatconnect with the boot ROM, the hard disk drive, and the optical drive, the power controller IC, thesound IC, the internal modem module, and the optional wireless LAN module.

The Intrepid I/O controller has a 32-bit PCI bus with a bus clock speed of 33 MHz.

Each of the components listed here is described in one of the following sections.

16 Block Diagram and Buses2005-04-05 | © 2005 Apple Computer, Inc. All Rights Reserved.

C H A P T E R 2

Architecture

Processor bus.How the CPUtalks to everything else.

CPU: PowerPC G4 (Freescale)

Bus controller. Low-cost Mac Mini only has 1. Most PCs have two: fast North Bridge, slow South Bridge.

Mac Mini G4: System block diagram

5



167 MHzMaxBus

12 MbpsUSB

PCI bus

BootROM




DDR SDRAMDIMM slot

32 MBDDR RAM



FireWire 400 port

AGP 4Xbus

167 MHzMemory

bus

PMUpower controller

Powerbutton Fan

Opticaldrive

UltraATA/100

bus

Device 0

Device 1


Hard diskdrive

Radeon9200

graphics IC

Audiocodec

EthernetPHY

FireWirePHY


(L2 cache: 512K 1:1)

AirPort Extreme

I2S

I2S

I2C

BluetoothModem port

Modem module

Data pumpand DAA

Built-inspeaker


controller

Main ICs and Buses






C H A P T E R 2

Architecture

The bus controller talks to everything elseAGP 4X bus.Graphics chip.

PCI bus: Boot ROM, USB 2.

ATA/100 bus.For hard disk,DVD/CD ROM.

PCI, ATA, AGP devices can be bus master, for Direct Memory Access (DMA). Disk can write RAM directly.

6



167 MHzMaxBus

12 MbpsUSB

PCI bus

BootROM




DDR SDRAMDIMM slot

32 MBDDR RAM



FireWire 400 port

AGP 4Xbus

167 MHzMemory

bus

PMUpower controller

Powerbutton Fan

Opticaldrive

UltraATA/100

bus

Device 0

Device 1


Hard diskdrive

Radeon9200

graphics IC

Audiocodec

EthernetPHY

FireWirePHY


(L2 cache: 512K 1:1)

AirPort Extreme

I2S

I2S

I2C

BluetoothModem port

Modem module

Data pumpand DAA

Built-inspeaker


controller

Main ICs and Buses






C H A P T E R 2

Architecture

ATI Radeon 9200: Graphics Processing Unit (GPU).

Mac Mini: Graphics sub-system

To Display

AGP 4X: Hi-Speed Graphics Bus

Dedicated Graphics RAM

Average selling price (ASP) for GPUs: $307


8


9

Parts + manufacturing cost: $283.37

Parts cost in volume: $274.69

GPU cost a significant part of total “Bill of Materials”

Source: iSuppli corporation

10


About 12 MB/frame (24-bit pixels)24 frames/sec: 300 MB/second

1600

2560

11



167 MHzMaxBus

12 MbpsUSB

PCI bus

BootROM




DDR SDRAMDIMM slot

32 MBDDR RAM



FireWire 400 port

AGP 4Xbus

167 MHzMemory

bus

PMUpower controller

Powerbutton Fan

Opticaldrive

UltraATA/100

bus

Device 0

Device 1


Hard diskdrive

Radeon9200

graphics IC

Audiocodec

EthernetPHY

FireWirePHY


(L2 cache: 512K 1:1)

AirPort Extreme

I2S

I2S

I2C

BluetoothModem port

Modem module

Data pumpand DAA

Built-inspeaker


controller

Main ICs and Buses






C H A P T E R 2

Architecture


167 MHzMaxBus

12 MbpsUSB

PCI bus

BootROM




DDR SDRAMDIMM slot

32 MBDDR RAM



FireWire 400 port

AGP 4Xbus

167 MHzMemory

bus

PMUpower controller

Powerbutton Fan

Opticaldrive

UltraATA/100

bus

Device 0

Device 1


Hard diskdrive

Radeon9200

graphics IC

Audiocodec

EthernetPHY

FireWirePHY


(L2 cache: 512K 1:1)

AirPort Extreme

I2S

I2S

I2C

BluetoothModem port

Modem module

Data pumpand DAA

Built-inspeaker


controller

Main ICs and Buses






C H A P T E R 2

Architecture

Anatomy of a “dumb” graphics card ...AGP 4X: 1.1 GB/s. Can handle 24 f/s(300 MB/s) for a 2560x1600 display.

DVI Formatter D/A

Control Logic

12 MB Frame Buffer

12 MB Frame Buffer

Double Buffering:

CPU writes “next frame” in one buffer.

Control logic sends “this frame” out of other buffer to display.

Problem: CPU has to compute a new pixel every 10 ns. 10 clock cycles for a 1 GHz CPU clock.

12


Graphics Acceleration

Q. In a multi-core world, why should we use a special processor for graphics? A. Programmers generally use a certain coding style for graphics. We can design a processor to fit the style.

Q. What kind of graphics are we accelerating?A. In 2009, interactive entertainment (3-D games). In the 1990s, 2-D acceleration (fast windowing systems, games like Pac-Man).

Next: An intro to 3-D graphics.

13


The Triangle ...

Simplest closed shape that may be defined by straight edges.

With enough triangles, you can make anything.

14


A cube whose faces are made up of triangles. This is a 3-D model of a cube -- model includes faces we can’t see in this view.

A sphere whose faces are made up of triangles. With enough triangles, the curvature of the sphere can be made arbitrarily smooth.

15


A teapot (famous object in computer graphics history). A “wire-frame” of triangles can capture the 3-D shape of complex, man-made objects.

16


Triangle defined by 3 verticesBy transforming (v’ = f(v)) all vertices in a 3-D object (like the teapot), you can move it in the 3-D world, change it’s size, rotate it, etc.

vertex vo = (xo, yo, zo)vertex v1 = (x1, y1, z1)

vertex v2 = (x2, y2, z2)

If a teapot has 10,000 triangles, need to transform 30,000 vertices to move it in a 3-D scene ... per frame!

17


Vertex can have color, lighting info ...If vertices colors are different, this means that a smooth gradient of color washes across triangle.

vertex vo = (ro, go, bo)vertex v1 = (r1, g1, b1)

vertex v2 = (r2, g2, b2)

More realistic graphics models include light sources in the scene. Per-vertex information can carry information about how light hits the vertex.

18


We see a 2-D window into the 3-D world

Let’s follow

one 3-D

triangle.

19


From 3-d triangles to screen pixelsFirst, project each 3-D triangle that might

“face” the “eye” onto the image plane.

Then, create “pixel fragments” on the boundary of the

image plane triangle

Then, create “pixel fragments” to fill in the triangle

(rasterization).

Why “pixel fragments”? A screen pixel color might depend on many triangles (example: a glass teapot).

20


Process pixel fragment to “shade” it.Algorithmic approach: Per-pixel computational model of metal and how light reflects off of it. Move teapot and what reflects off it changes.

21


Process each fragment to “shade” it.Artistic approach: Artist paints surface of teapot in Photoshop. We “map” this “texture” onto each pixel fragment during shading.Final step: Output Merge. Assemble pixel fragments to make final 2-d image pixels.

22


Real-world texture maps: Bike decals

23


Applying texture maps: Quality matters! !"#$%&'()*!

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“Good” algorithm. B and C look blurry.

“Better” algorithm. B and C aredetailed.

24


Putting it All Together ...

Luxo, Jr: Short movie made by Pixar, shown at SIGGRAPH in 1986.

First Academy Award given to a computer graphics movie.

25


26


Graphics Acceleration

Next: Back to architecture ...

27


The graphics pipeline in hardware (2004)Figure 2-1 Block diagram

167 MHzMaxBus

12 MbpsUSB

PCI bus

BootROM




DDR SDRAMDIMM slot

32 MBDDR RAM



FireWire 400 port

AGP 4Xbus

167 MHzMemory

bus

PMUpower controller

Powerbutton Fan

Opticaldrive

UltraATA/100

bus

Device 0

Device 1


Hard diskdrive

Radeon9200

graphics IC

Audiocodec

EthernetPHY

FireWirePHY


(L2 cache: 512K 1:1)

AirPort Extreme

I2S

I2S

I2C

BluetoothModem port

Modem module

Data pumpand DAA

Built-inspeaker


controller

Main ICs and Buses






C H A P T E R 2

Architecture

Output Merge


167 MHzMaxBus

12 MbpsUSB

PCI bus

BootROM




DDR SDRAMDIMM slot

32 MBDDR RAM



FireWire 400 port

AGP 4Xbus

167 MHzMemory

bus

PMUpower controller

Powerbutton Fan

Opticaldrive

UltraATA/100

bus

Device 0

Device 1


Hard diskdrive

Radeon9200

graphics IC

Audiocodec

EthernetPHY

FireWirePHY


(L2 cache: 512K 1:1)

AirPort Extreme

I2S

I2S

I2C

BluetoothModem port

Modem module

Data pumpand DAA

Built-inspeaker


controller

Main ICs and Buses






C H A P T E R 2

Architecture

To display

Create pixels fragments

Algorithms are usually hardwired

Process each vertex

3-D vertex “stream” sent by CPU

Programmable CPU”Vertex Shader”

Process pixel fragments

Programmable CPU”Pixel Shader”

Programming Language/API? DirectX, OpenGL

28


Vertex Shader: A “stream processor”

Shader CPU

Input Registers (Read Only)

Vertex “stream” from CPUOnly one vertex at a time placed in input registers.

Constant Registers

(Read Only)

From CPU: changes slowly (per frame,

per object)

Output Registers (Write Only)

Vertex “stream” ready for 3-D to 2-D conversion

Shader creates one vertex out for each vertex in.Working

Registers (Read/Write)

Shader Program Memory

Short (ex: 128 instr)straight-line code. Same code runs on every vertex.

29


Optimized instructions and data formats

Input Registers

From CPU

Output Registers

Shader CPU Shader Program Memory

128-bit registers, holding four 32-bit floats.

Typical use: (x,y,z,w) representation of a point in 3-Dspace.

x y z w

x y z w

Typical instruction:

rsq dest src

dest.{x,y,z,w} = 1.0/sqrt(abs(src.w)).If src.w=0, dest ∞.

The 1/sqrt() function is often used in graphics.

To 3-D/2-D 30


Easy to parallelize: Vertices independent

Input Registers

From CPU

Output Registers

Shader CPU

x y z w

x y z w

Input Registers

Output Registers

Shader CPU

x y z w

x y z w

To 3-D/ 2-D

Caveat: Care might be needed when merging streams.

Why?3-D to 2-D may expect triangle vertices in order in the stream.

Shader CPUs easy to multithread.

31


Pixel shader specializations ...

Process each vertex

Create pixels fragments

Output Merge


167 MHzMaxBus

12 MbpsUSB

PCI bus

BootROM




DDR SDRAMDIMM slot

32 MBDDR RAM



FireWire 400 port

AGP 4Xbus

167 MHzMemory

bus

PMUpower controller

Powerbutton Fan

Opticaldrive

UltraATA/100

bus

Device 0

Device 1


Hard diskdrive

Radeon9200

graphics IC

Audiocodec

EthernetPHY

FireWirePHY


(L2 cache: 512K 1:1)

AirPort Extreme

I2S

I2S

I2C

BluetoothModem port

Modem module

Data pumpand DAA

Built-inspeaker


controller

Main ICs and Buses






C H A P T E R 2

Architecture


167 MHzMaxBus

12 MbpsUSB

PCI bus

BootROM




DDR SDRAMDIMM slot

32 MBDDR RAM



FireWire 400 port

AGP 4Xbus

167 MHzMemory

bus

PMUpower controller

Powerbutton Fan

Opticaldrive

UltraATA/100

bus

Device 0

Device 1


Hard diskdrive

Radeon9200

graphics IC

Audiocodec

EthernetPHY

FireWirePHY


(L2 cache: 512K 1:1)

AirPort Extreme

I2S

I2S

I2C

BluetoothModem port

Modem module

Data pumpand DAA

Built-inspeaker


controller

Main ICs and Buses






C H A P T E R 2

Architecture

Pixel shader needs fast access to the map of Europe on teapot (via graphics card RAM).

Texture maps (look-up tables) play a key role.

Process pixel fragments

”Pixel Shader” CPU

32


Pixel Shader: Stream processor + Memory

Shader CPU

Input Registers (Read Only)

Pixel fragment stream from rasterizerOnly one fragment at a time placed in input registers.

Constant Registers

(Read Only)

From CPU: changes slowly (per frame,

per object)

Registers (Read/Write)

Register R0 is pixel fragment,

ready for output merge

Shader creates one fragment out for each fragment in.

Indices into texture maps.

TextureRegisters

Texture Engine

Memory System

Engine does interpolation.

33


Example Design: Nvidia GeForce 7900

Vertex Shaders: 8

Pixel Shaders:24

3-D to 2-D

Output Merge Units

Texture Cache

278 Million Transistors, 650 MHz clock, 90 nm process


167 MHzMaxBus

12 MbpsUSB

PCI bus

BootROM




DDR SDRAMDIMM slot

32 MBDDR RAM



FireWire 400 port

AGP 4Xbus

167 MHzMemory

bus

PMUpower controller

Powerbutton Fan

Opticaldrive

UltraATA/100

bus

Device 0

Device 1


Hard diskdrive

Radeon9200

graphics IC

Audiocodec

EthernetPHY

FireWirePHY


(L2 cache: 512K 1:1)

AirPort Extreme

I2S

I2S

I2C

BluetoothModem port

Modem module

Data pumpand DAA

Built-inspeaker


controller

Main ICs and Buses






C H A P T E R 2

Architecture

34


Break Time ...

Next: Unified architectures

Play

35


Unified Architectures

Basic idea: Replace specialized logic (vertex shader, pixel shader, hardwired algorithms) with many copies of one unified CPU design.

Consequence: You no longer “see” the graphics pipeline when you look at the architecture block diagram.

Designed for: DirectX 10 (Microsoft Vista), and new non-graphics markets for GPUs.

36


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DirectX 10 (Vista): Towards Shader UnityEarlier APIs: Pixel and Vertex CPUs very different ...

DirectX 10: Many specs are identical for Pixel and Vertex CPUs

37


DirectX 10 : New Pipeline Features ...!

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Geometry Shader: Lets a shader program create new triangles.

Stream Output: Lets vertex streamrecirculate through shaders many times ...(and also, back to CPU)

Also: Shader CPUs are more

like RISC machines in many ways.

38


Why? “Particle Systems” ...Why? Particle systems ...

39


Why? Fractal images ...

40


! GeForce 8800 Architecture in Detail

!

!

Figure 12. GeForce 8800 GTX Block Diagram !

!

!

!

TB-02787-001_v1.0 19

NVidia 8800: Unified GPU, announced Fall 2006

128 Shader CPUs Streams

loop around...

Thread processor sets shader type of each CPU

1.35 GHz Shader CPU Clock, 575 MHz core clock41


! GeForce 8800 Architecture in Detail

!

!

Figure 12. GeForce 8800 GTX Block Diagram !

!

!

!

TB-02787-001_v1.0 19

Graphics-centric functionality ...3-D to 2-D (vertex to pixel)

Pixel fragment output merge

Texture engine and memory system

42


Can be reconfigured with graphics logic hidden ...

128 scalar 1.35 GHz processors: Integer ALU, dual-issue single-precision IEEE floats.

! GeForce 8800 Architecture Overview

!

!

Figure 9. CUDA Thread Computing Pipeline "#$%!&'()*&+!'&,!(--*./(0.1'+!,.02!(!+0('3(43!-*(05146!514!&704(/0.'8!9(*:()*&!.'5146(0.1'!5416!9(+0!;:('0.0.&+!15!4(,!3(0(<!('3!-419.3&!02&!51**1,.'8!=&>!)&'&5.0+!.'!02.+!(4&(?!

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!

TB-02787-001_v1.0 13

Texture system set up to look like a conventional memory system (768MB GDDR3, 86 GB/s)

1000s of active threads

3 TeraFlops Peak Performance Ships with a C compiler.

43


Chip Facts

90nm process681M Transistors80 die/wafer (pre-testing)

A big die. Many chips will not work (low yield). Low profits.

4 year design cycle

Design Facts

$400 Million design budget600 person-years: 10 people at start, 300 at peak

44


GeForce 8800 GTX Card: $599 List Price

PCI-Express 16X Card - 2 Aux Power Plugs!

185 Watts Thermal Design Point (TDP) -- TDP is a “real-world” maximum power spec.

45


Some products are “loss-leaders”

Breakthrough product creates“free” publicity you can’t buy.

(1) Hope: when chip “shrinks” to 65nm fab process, die will be smaller, yields will improve, profits will rise.

(2) Simpler versions of the design will be made to create an entire product family, some very profitable.“We tape out a chip a month”, NVidia CEO quote.

46


And it happened! 2008 nVidia products

9800 GTX

Specs similar to 8800, card sells for $199.

GTX 280

Price similar to 8800, stream CPU count > 2X ...

47


48


Face was “scanned” to create a vertex model. 8800 GTX was used to do skin, eye, lips and hair rendering.

49


History and Graphics Processors

Create standard model from common practice: Wire-frame geometry, triangle rasterization, pixel shading.

Put model in hardware: Block diagram of chip matches computer graphics math.

Evolve to be programmable: At some point, it becomes hard to see the math in the block diagram.

“Wheel of reincarnation” -- Hardwired graphics hardware evolves to look like general-purpose CPU. EECS visitor Ivan Sutherland co-wrote a paper on this topic in 1968!

50


Intel @ SIGGRAPH 2008: Larrabee

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ACM Transactions on Graphics, Vol. 27, No. 3, Article 18, Publication date: August 2008.

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ACM Transactions on Graphics, Vol. 27, No. 3, Article 18, Publication date: August 2008.

A GPU that looks a lot like a many-core CPU.However, cores are specialized for graphics ...

51


Larrabee CPU core microarchitecture !

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Larra

bee: A

Many-C

ore

x86 A

rchite

ctu

re fo

r Vis

ual C

om

putin

g • 1

8:3

AC

M T

ransactio

ns o

n G

raphics, V

ol. 2

7, N

o. 3

, Article 1

8, P

ublicatio

n d

ate: August 2

008.

16-lane Vector Unit takes 2/3 of CPU core chip area.

Handles the graphics “heavy lifting”.

x86-ISA Scalar Unit

based on the 1992 original

Pentium.

In-order static

pipeline, dual issue.

52


Vector Unit specializations ...

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Load/store instruction variants may specify type conversion.

This supports a toll-free way store low resolution data in packed form, while letting the CPU compute on the data in a high-resolution format.

53


Can two EECS students prototype a GPU in one semester?

54

-Xilinx Virtex-5 ML505-110T-Vertex Shaders : Red-Pixel Shaders: Yellow-Rasterizer: Cyan-DDR2 Interface: Green

60% slice usage

55

UC Regents Fall 2008 © UCBCS 194-6 L1: Virtex-5 Microarchitecture

Fall 2008 CS 194-6: Pure project course.

Project teams: 1-to-3 person groups. This Friday: setting project topics. 10-noon, 125 Cory (not 119 Cory!).

No exams.

Mondays: Lectures teach topics useful for the project

No homework.

Fridays: Project

check-ups. 56

UC Regents Fall 2008 © UCBCS 194-6 L1: Virtex-5 Microarchitecture

CS 194-6: Project red-letter days.

Grade is based on revised versions of presentation slides (email PDFs to Greg and John after presentation).

Specification Design ReviewMon, Sept 29

Implementation Design Review

Mon, Nov 3

Final Presentation

Fri, Dec 5

57

YONG-JIN KWONCHEN SUN

PEGASUSPipeline Engineered Graphics Accelerator Supporting Unified

Shaders

58

Top level Block Diagram

59

3D API

<Constants>

Transform Matrix (4x4)

Inverse Perspective Matrix (4x4)

Transposed Rotation Matrix (4x4)

</Constant>

<Lights>

0, Vertex Index1

1, Vertex Index2

</Lights>

<Vertex>

0: x y z r g b nx ny nz



</Vertex>

<Triangle>

0: V1 V2 V3

1: V3 V4 V5

</Triangle>

Bit-widths:

Matrix – 256b

Element: 16 bits

Lights – 32b

Light Index: 16 bits

Vertex Index: 16 bits

Vertices – 115b

Vertex: 16 bits

Index: 16 bits

Color: 8 bits

Normal: 9 bits

Triangles – 64b

Triangle Index: 16 bits

Vertex Index: 16 bits

60

Java Framework

61

Java vs Hardware Comparison

� Java simulation on top

� Hardware Render on Bottom

� No lights yet� Ignore the

Black Vs. Gray background

62

More Java vs Hardware

-Java on the left, Actual render on the right-No hardware results yet for pixel shaded teapot

-Hardware fully functional (buggy shader code)-One thing to note: 500+ vertices and 900+ triangles

63


Next Tuesday’s Lecture:

Highly recommended !

64

eecs 150 components & design techniques for digital systems...

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