eecs150 - digital design lecture 3 - timingcs150/fa02/handouts/2/lecturea/lec03-timing.pdffall 2002...
TRANSCRIPT
Fall
2002
EEC
S150
-Le
c03-
Tim
ing
Page
1
EEC
S150
-D
igita
l Des
ign
Lect
ure
3 -T
imin
g
Sept
embe
r 3, 2
002
John
Waw
rzyn
ek
Fall
2002
EEC
S150
-Le
c03-
Tim
ing
Page
2
Out
line
•Fi
nish
up
from
lect
ure
2•
Gen
eral
Mod
el o
f Syn
chro
nous
Sys
tem
s–
Perfo
rman
ce L
imits
•An
noun
cem
ents
•D
elay
in lo
gic
gate
s•
Del
ay in
wire
s•
Clo
ck S
kew
•D
elay
in fl
ip-fl
ops
Fall
2002
EEC
S150
-Le
c03-
Tim
ing
Page
3
Tran
sist
or-le
vel L
ogic
Circ
uits
(con
t.)•
Posi
tive
Leve
l-sen
sitiv
e la
tch
•Tr
ansi
stor
Lev
el•
Posi
tive
Edge
-trig
gere
d fli
p-flo
p
clk’ clk
clk
clk’
Fall
2002
EEC
S150
-Le
c03-
Tim
ing
Page
4
Gen
eral
Mod
el o
f Syn
chro
nous
Circ
uit
•Al
l wire
s, e
xcep
t clo
ck, m
ay b
e m
ultip
le b
its w
ide.
•R
egis
ters
(reg
)–
colle
ctio
ns o
f flip
-flop
s•
cloc
k–
dist
ribut
ed to
all
flip-
flops
–ty
pica
l rat
e?
•C
ombi
natio
nal L
ogic
Blo
cks
(CL)
–no
inte
rnal
sta
te–
outp
ut o
nly
a fu
nctio
n of
inpu
ts•
Parti
cula
r inp
uts/
outp
uts
are
optio
nal
•O
ptio
nal F
eedb
ack
reg
reg
CLCL
clock
inpu
t
outp
ut
optio
n fe
edba
ck
inpu
tou
tput
Fall
2002
EEC
S150
-Le
c03-
Tim
ing
Page
5
Exam
ple
Circ
uit
•Pa
ralle
l to
Seria
l Con
verte
r
•Al
l sig
nal p
aths
sin
gle
bit w
ide
•R
egis
ters
are
sin
gle
flip-
flops
•C
ombi
natio
nal L
ogic
blo
cks
are
sim
ple
mul
tiple
xors
•N
o fe
edba
ck in
this
cas
e.
Fall
2002
EEC
S150
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c03-
Tim
ing
Page
6
Gen
eral
Mod
el o
f Syn
chro
nous
Circ
uit
•H
ow d
o w
e m
easu
re p
erfo
rman
ce?
–op
erat
ions
/sec
?–
cycl
es/s
ec?
•W
hat l
imits
the
cloc
k ra
te?
•W
hat h
appe
ns a
s w
e in
crea
se th
e cl
ock
rate
?
reg
reg
CLCL
clock
inpu
t
outp
ut
optio
n fe
edba
ck
inpu
tou
tput
Fall
2002
EEC
S150
-Le
c03-
Tim
ing
Page
7
Lim
itatio
ns o
n C
lock
Rat
e1
Logi
c G
ate
Del
ay
•W
hat a
re ty
pica
l del
ay v
alue
s?
2D
elay
s in
flip
-flop
s
•Bo
th ti
mes
con
tribu
te to
lim
iting
th
e cl
ock
perio
d.
t
inpu
t
outp
ut
D clk Q setu
p tim
eclo
ck to
Q d
elay
•W
hat m
ust h
appe
n in
one
clo
ck c
ycle
for c
orre
ct o
pera
tion?
•As
sum
ing
perfe
ct c
lock
dis
tribu
tion
(all
flip-
flops
see
the
cloc
k at
the
sam
e tim
e):
–Al
l sig
nals
mus
t be
read
y an
d “s
etup
” bef
ore
risin
g ed
ge o
f clo
ck.
Fall
2002
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S150
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c03-
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8
Exam
ple
•Pa
ralle
l to
seria
l con
verte
r:
a bT ≥
time(
clk→
Q) +
tim
e(m
ux) +
tim
e(se
tup)
T ≥τ c
lk→
Q+ τ m
ux+ τ s
etup
clk
Fall
2002
EEC
S150
-Le
c03-
Tim
ing
Page
9
Gen
eral
Mod
el o
f Syn
chro
nous
Circ
uit
•In
gen
eral
, for
cor
rect
ope
ratio
n:
for a
ll pa
ths.
•H
ow d
o w
e en
umer
ate
all p
aths
?–
Any
circ
uit i
nput
or r
egis
ter o
utpu
t to
any
regi
ster
inpu
t or c
ircui
t ou
tput
.–
“set
up ti
me”
for c
ircui
t out
puts
dep
ends
on
wha
t it c
onne
cts
to–
“clk
-Q ti
me”
for c
ircui
t inp
uts
depe
nds
on fr
om w
here
it c
omes
.
reg
reg
CLCL
clock
inpu
t
outp
ut
optio
n fe
edba
ck
inpu
tou
tput
T ≥
time(
clk→
Q) +
tim
e(C
L) +
tim
e(se
tup)
T ≥τ c
lk→
Q+ τ C
L+ τ s
etup
Fall
2002
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S150
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c03-
Tim
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10
Anno
unce
men
ts•
Rem
embe
r to
chec
k th
e w
eb-p
age
ofte
n.
–H
omew
ork
due
Frid
ay.
Star
t ear
ly, g
et h
elp
in d
iscu
ssio
n se
ctio
ns
and
offic
e ho
urs.
•Lo
ok a
t not
es o
nlin
e be
fore
cla
ss.
–Su
gges
tion:
prin
t out
and
brin
g co
py to
cla
ss -
anno
tate
whe
n ne
cess
ary.
My
note
s ar
e in
tent
iona
lly in
com
plet
e. F
ull p
age
is
easi
er fo
r thi
s th
an “6
-up”
. •
Turn
in H
W#1
bef
ore
1pm
Frid
ay.
Hom
ewor
k bo
x m
ovin
g fro
m o
utsi
de 2
18 C
ory
to o
utsi
de 1
25 C
ory
–N
ot s
ure
whe
re it
will
be o
n Fr
iday
.•
Dis
cuss
ions
, TA
offic
e ho
urs,
and
labs
this
wee
k.•
Qui
z Fr
iday
at l
ab le
ctur
e.
Fall
2002
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S150
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c03-
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ing
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11
Qua
litat
ive
Anal
ysis
of L
ogic
Del
ay•
Impr
oved
Tra
nsis
tor M
odel
: nF
ET•
We
refe
r to
trans
isto
r "st
reng
th" a
s th
e am
ount
of c
urre
nt th
at fl
ows
for
a gi
ven
Vds
and
Vgs.
•
The
stre
ngth
is li
near
ly p
ropo
rtion
al
to th
e ra
tio o
f W/L
.
pFET
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2002
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S150
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c03-
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12
Gat
e Sw
itchi
ng B
ehav
ior
•In
verte
r:
•N
AND
gat
e:
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2002
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S150
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c03-
Tim
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13
Gat
e D
elay
•C
asca
ded
gate
s:
Vout
Vin
Fall
2002
EEC
S150
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c03-
Tim
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14
Gat
e D
elay
•Fa
n-ou
t:
•Th
e de
lay
of a
gat
e is
pro
porti
onal
to it
s ou
tput
cap
acita
nce.
Bec
ause
, ga
tes
#2 a
nd 3
turn
on/
off a
t a la
ter t
ime.
(It
take
s lo
nger
for t
he o
utpu
t of
gat
e #1
to re
ach
the
switc
hing
thre
shol
d of
gat
es #
2 an
d 3
asw
e ad
d m
ore
outp
ut c
apac
itanc
e.)
1
32
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2002
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S150
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c03-
Tim
ing
Page
15
Gat
e D
elay
•“F
an-in
”
•W
hat i
s th
e de
lay
in th
is c
ircui
t?•
Crit
ical
Pat
h: th
e pa
th w
ith th
e m
axim
um d
elay
, fro
m a
ny
inpu
t to
any
outp
ut.
–In
gen
eral
, we
incl
ude
regi
ster
set
-up
and
clk-
to-Q
tim
es in
cr
itica
l pat
h ca
lcul
atio
n.•
Why
do
we
care
abo
ut th
ecr
itica
l pat
h?
Fall
2002
EEC
S150
-Le
c03-
Tim
ing
Page
16
Del
ay in
Flip
-flop
s•
Setu
p tim
ere
sults
del
ay th
roug
h fir
stla
tch.
•C
lock
to Q
del
ayre
sults
from
de
lay
thro
ugh
seco
ndla
tch.
D clk Q setu
p tim
eclo
ck to
Q d
elay
clk
clk’
clk
clk
clk’clk’
clk
clk’
Fall
2002
EEC
S150
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c03-
Tim
ing
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17
Wire
Del
ay•
In g
ener
al, w
ire b
ehav
e as
“tr
ansm
issi
on li
nes”
:–
sign
al w
ave-
front
mov
es c
lose
to
the
spee
d of
ligh
t•
~1ft/
ns–
Tim
e fro
m s
ourc
e to
des
tinat
ion
is c
alle
d th
e “tr
ansi
t tim
e”.
–In
ICs
mos
t wire
s ar
e sh
ort,
and
the
trans
it tim
es a
re re
lativ
ely
shor
t com
pare
d to
the
cloc
k pe
riod
and
can
be ig
nore
d.–
Not
so
on P
C b
oard
s.
t
x
Fall
2002
EEC
S150
-Le
c03-
Tim
ing
Page
18
Wire
Del
ay•
Even
in th
ose
case
s w
here
the
trans
mis
sion
line
effe
ct is
ne
glig
ible
:–
Wire
s po
sses
dis
tribu
ted
resi
stan
ce a
nd c
apac
itanc
e
–Ti
me
cons
tant
ass
ocia
ted
with
di
strib
uted
RC
is p
ropo
rtion
al to
th
e sq
uare
of th
e le
ngth
•Fo
r sho
rt w
ires
on IC
s,
resi
stan
ce is
insi
gnifi
cant
(re
lativ
e to
effe
ctiv
e R
of
trans
isto
rs),
but C
is im
porta
nt.
–Ty
pica
lly a
roun
d ha
lf of
C o
f ga
te lo
ad is
in th
e w
ires.
•Fo
r lon
g w
ires
on IC
s:–
buss
es, c
lock
line
s, g
loba
l co
ntro
l sig
nal,
etc.
–R
esis
tanc
e is
sig
nific
ant,
ther
efor
e di
strib
uted
RC
effe
ct
dom
inat
es.
–si
gnal
s ar
e ty
pica
lly “r
ebuf
fere
d”
to re
duce
del
ay:
v1
v4v3
v2
time
v1v2
v3v4
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2002
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19
Clo
ck S
kew
•U
nequ
al d
elay
in d
istri
butio
n of
the
cloc
k si
gnal
to v
ario
us p
arts
of a
ci
rcui
t:–
if no
t acc
ount
ed fo
r, ca
n le
ad to
erro
neou
s be
havi
or.
–C
omes
abo
ut b
ecau
se:
•cl
ock
wire
s hav
e de
lay,
•ci
rcui
t is d
esig
ned
with
a d
iffer
ent n
umbe
r of c
lock
buf
fers
from
the
cloc
k so
urce
to th
e va
rious
clo
ck lo
ads,
or•
buff
ers h
ave
uneq
ual d
elay
.–
All s
ynch
rono
us c
ircui
ts e
xper
ienc
e so
me
cloc
k sk
ew:
•m
ore
of a
n is
sue
for h
igh-
perf
orm
ance
pip
elin
ed d
esig
ns o
pera
ting
with
ver
y lit
tle e
xtra
tim
e pe
r clo
ck c
ycle
.
cloc
k sk
ew, d
elay
in d
istri
butio
n
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2002
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c03-
Tim
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20
Clo
ck S
kew
(con
t.)
•If
cloc
k pe
riod
T =
T CL+
T set
up+T
clk→
Q, c
ircui
t will
fail.
•Th
eref
ore:
1. C
ontro
l clo
ck s
kew
a) C
aref
ul c
lock
dis
tribu
tion.
Equ
aliz
e pa
th d
elay
from
clo
ck s
ourc
e to
all
cloc
k lo
ads
by c
ontro
lling
wire
s de
lay
and
buffe
r del
ay.
b) d
on’t
“gat
e” c
lock
s.2.
T ≥
T CL+
T set
up+T
clk→
Q +
wor
st c
ase
skew
.•
Mos
t mod
ern
larg
e hi
gh-p
erfo
rman
ce c
hips
(mic
ropr
oces
sors
) con
trol
end
to e
nd c
lock
ske
w to
a fe
w te
nths
of a
nan
osec
ond.
cloc
k sk
ew, d
elay
in d
istri
butio
nC
L
CLK
CLK
’
CLK
CLK
’
Fall
2002
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S150
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Clo
ck S
kew
(con
t.)
•N
ote
reve
rsed
buf
fer.
•In
this
cas
e, c
lock
ske
w a
ctua
lly p
rovi
des
extra
tim
e(a
dds
to th
e ef
fect
ive
cloc
k pe
riod)
.•
This
effe
ct h
as b
een
used
to h
elp
run
circ
uits
as
high
er
cloc
k ra
tes.
Ris
ky b
usin
ess!
CL
CLK
CLK
’
cloc
k sk
ew, d
elay
in d
istri
butio
n
CLK
CLK
’