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AD-AI02 841 GENERAL ELECTRIC CO PITTSFIELD MA ORDNANCE SYSTEMS F/6 9/5ELECTRICAL CHARACTERIZATION AND SPECIFICATION OF PERIPHERAL OI--ETC(U)RAY 81 J S KULPIN$KI. T HACK, T SIMONSEN F30602-80-C-0057
UNCLASSIFIED RADC-TR-81-72 NL.FEEEEEEEEEIEIIEEEEEEEEEIIEEEEEEEEEEEEI/EIEEE-EhEEEEE//EglEgllEEEEEEIIIIEEIIEIIEIIEI
RADC-TR-8 1-72Final Technical ReportMay 1981 E
ELECTRICAL CHARACTERIZATION AND
SPECIFICATION OF PERIPHERAL DRIVERS,
CORE DRIVERS AND MULTIPLYING DACs
General Electric Ordnance Systems DTICJohn S. Kulpinski, et al S |T
AUO 14 1981
[APPROVED FOR PUBLIC RELEASE; DISTRIBUTION UNLIMITED]
, ROME AIR DEVELOPMENT CENTERAir Force Systems Command
Latij Griffiss Air Force Base, New York 13441
S818 14055
This report has been reviewed by the RADC Public Affairs Office (PA) and
is releasable to the National Technical Information Service (NTIS). At NTIS
it will be releasable to the general public, including foreign nations.
RADC-TR-81-72 has been reviewed and is approved for publication.
APPROVED: .,
THOMAS L. DELLECAVEProject Engineer
APPROVED: 4CDAVID C. LUKE, Colonel, USAF
Chief, Reliability & Compatibility Division
FOR THE COMMANDER: %
JOHN P. HUSSActing Chief, Plans Office
If your address has changed or if you wish to be removed from the RADCmailing list, or if the addressee is no longer employed by your organization,
please notify RADC.(RBRA) Griffiss AFB NY 13441. This will assistus in
maintaining a current mailing list.
Do~not return this copy. Retain or destroy. (.4I
S - . . - - -
SECURITY Z"lkLCATIDN :) TaS PA-3i When 0.1. F- Prod),
REPOT DCUMETATON PGE EAD INSTRUCTIONS/ RPOR DOUMETATON AGEBEFORE CaMP! ETINC. 1 RM
4. TIT665. TYPE OF REPORT PIE LICTR I CA~L C11ARACll: RKI XAI I ON ANDI SI) E 1I 1 CA.1, 1 Filia Tec'in i ca IR ppot
) MULTI PLY I NG IACs, 0 Ro NumPER
7AU YNO-R(.) O 3~'A R GRANT NUMBER,.,
Johnf S. Ku II pillki , ot al F I 10002-80-t-Ow
9 PERFORMING ORGANIZATION NAME AND ADDRESS 10 PROGRAM ELEMENT PRO,Efl(hin' ra1 LIci' r ic Odn~i C.'5v~- t Qa-iARE A 5 *OR% NI T NoiMBE QS
2 V380~ 18oP'ittsfielId MA\ 01201 Ati 70NTROL..ING OFFICE NAME AND ADDRESS 'Z REPORT DATE
Ma\' 1981
C:r if iss A\:), NY 1 34 I1 1204 .4ONITrRING AGEN,-a N AME &A~E3,J4 I.nt ram C,nfrollhnd Off-s 'S SE-jRIaY :ASS --- -
I N (.\ S
16 DISTR19UTION iT'FM'EEN r of rh.l Rep~ort)
Approved i or I'b1 I i ' EIL' I ease-;L; d is-t I- ibot i )In til I il'i i t cd
John S. /Kulpinski Thomas /Hack
17 OISTRI~tuTION SrA-EMENT ,theasrc I Theodore /Simonsen Larry /DelucaJohn /Dunn
18 SUPPLmEN ARf NOTES
1IA[W P'ro ;i.* k- L i l i lit-I- T t~o iii,-i s 1. 1X Iec ve ( RIKIR.\
t9 KEY *OROS Co lu or ees ie, e s.rv -nd ,defffll hy hlock n.be,
Re' I jab i i t vInlterfa',CC Mi CI-Oi rtc it
20 ABSTRACT7 -- 10-nu -r -.ve10 -id. if -,ce-.- -d ,d-nv,lv by block -15b-r)
- lThis ri-tt co\lVQrs th b o rk pe.'r V a med bN' ( L'tiro I Ioctr ic Ordnaiitc
spoim f~i i an, LperloI 1t k. i I ic ta s t lit elec rcca IC li ra tI 1- 01, t V at
is Jaiiwiirv 1980 to talnirv 1981. 11c nla in tilruISt at tliiS ' eti~c;Iar'icter izatiol elfart sa directed alt Ii iii i lit arv iis!''.( 1)r I ie rl-an1d c or'-c dI- i v'ci an; 1d 11un ItL ip 1)1V in 1 CMO "S d i i tit I L o anal i o' COn\ ItterS . the'
1?DD jAN% 3 1473 E71TON OF NOV 65 IS OBSOLETE U'N C A S S 1 1 1SECuRIYY :L ASSIFICATION I'F THIS PAGE *14,, le.En.t..d)
UNCLASSIFIED
SECURITY CLASSIFICATION OF 11IS PAGE(Whw Data EZnead
following device types were evaluated:
Peripheral Drivers - 55450 and 55460 family,
Core Drivers - 55325/6/7,1 .-- (
Multiplying CMOS DACs - 7520 family,
Data obtained during device characterization is published in handbook
form and is available under separate cover from this document. However,
samples of data sheets, histograms and plots are included in this report.
A
UINCLASS! F[ED
SECUR ITY CL.aSSIFICATiCg O -A EW n Dal- F,1e.qd,
PREFACE
This report was prepared by General Electric Ordnance Systems, 100 PlasticsAvenue, Pittsfield, Massachusetts, for Rome Air Development Center, GriffissAir Force Base, Rome, New York, under contract F30602-80-C-0057. It covers
the period from January 1980 to January 1981.
The work on this project was performed by the Electronic Circuits EngineeringOperation of Ordnance Systems. Project responsibility was held by Mr. JohnKulpinski of Circuit Design Engineering. Key individuals who made significantcontributions to this work effort were Messrs. Thomas Hack and TheodoreSimonsen of Circuit Design Engineering and Messrs. Larry Deluca, John Dunn,Robert Mossman and Jamie Schwehr of Circuit Test Engineering.
Mr. Thomas Dellecave, RBRA, is the Project Engineer at RADC for this contract.
Accession For
NTIS ID ' T'
fD . _
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wI
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ELECTRICAL CHARACTERIZATION AND SPECIFICATION OFPERIPHERAL DRIVERS, CORE DRIVERS, AND MULTIPLYING DACs
List of Sections
PACESECT ION T ITLE NUMBER
I. INTRODUCTION I-i
II. AUTOMATIC TEST DEVELOPMENT LI-i
III. CHARACTERIZATION OF PERIPHERAL DRIVERS Ill-iMIL-M-38510/129
IV. CHARACTERIZATION OF CORE DRIVERS, IV-iMIL-M-38510/130
V. CHARACTERIZATION OF CMOS MDACs, V-iMIL-M-38510/127
F"
SECTION I
INTRODUCTION
TABLE OF CONTENTS
Page
Jbjectives I- 1
Scope of Applied Effort I- 2
Background I- 2
Development of Slash Sheets 1- 3
Characterization Data I- 1,
orral MeetLngs Attended I- 4.
&
I
- v: •. -
SECTION I
INTRODUCTION
Objectives
The overall objective of this work effort is to chiaracterize and specify
MIL-M-38510 ("General Specification for Microcircuits") detailed slash sheets.
Generally, "characterization" of a device type includes several related tasks:
o Assessment of test parameters, limits, and test conditions.
o Development of test procedures and test circuits compatible with
automatic test systems.
o Analysis of limits and verification of test circuits via sampledevice testing and data evaluation.
o Assessment of device performance, identification of anorio!ies.
o Generation and verification of detailed burn-in life test c-rcuits
Concurrent with characterization, detailed MIIL-M-38510 siioc s!;eet developmentincludes:
o Formulation of Table I, Electrical Performance Characteristicsselection of test parameters required by military users and
determination of test conditions and limits, compatible withautomatic test methods and with device yield.
o Formulation of Table II, Electrical Test Requirements; Table ill,
Group A Inspection; Table IV, Group C End Point Electrical
pa rame te rs.
o Design of static and dynamic test circuits, terminal connectiondiagrams, steady-state power and reverse bias burn-in circuits,
accelerated burn-in and life test circuits.
All of the above activity is either guided by or reviewed by the manufacturers
of the devices involved, and by Rome Air Development Center (RADC).
All of the characterization and specification effort performed is based upon
the fundamental objectives of the JAN 38510 program - namely quality,
reliability, interchangeability, and standardization.
Scope of Appli ed iVt fort.
Thle spei tice tasks inc luded in tis Qf fortL are thle chiaracteriz a L ion andSpeCif iCaltionl of the I I lowin l eneri devietp
* lPeriphierail Drivers* Core Driverso Mltiplyinlg ')ACS
Or ig i nal l, sense ampli fi ers and Li n driver-6 werk2 also planned to rcharacter izat ion. Lack of vendor interestL and support plus discontinu~edproduct ion by oake vendo r, Led to ca ance lit ion of thiat effort and addi tion ofthe multiplying, flA et ort.
Backgrou-nd
General B Loctr ic Ordnainec Systemis, one of 166 operat iag product departMent-s ofthe Genieral Electric Company, develops and produces precisionie Le t romuchain ical suin cl cot conic rnil ita rv Systems. ,u r rent a-ct iv iti es inIcI(IdedL!e1 lk-ilLn, des iin an:d product ion oi rirte contral 1 and guidance systems I orC ie N1avy's TRi )IKNT F Ice t Balisti t" issile program, Lt' 1K 73 Gun and G'ui ludMlissile2 Director (TARTAR), the MK 80 Director (AEGIS), the PHiALANX close-in
weapon sys Leo-, M1K 45 Gun Mounts, turrt drive anid stabilization sys teimi- forthe Armv's Infantry Fight ing Vehicle, advanced torpedo propuls ion, an(I jet
c ;I§ ie Icocntrmols.
As; ul ;ers of ml croci rcui ts for i,.il ita ry systemis, Ordnance Systems has a I 5)
J-e inforMed electrical characterization of certain- linear, digital, andinterlace, microci rcuits for I-- 10sp~ec if iction Under prev ions cont mr~CL.tto Rome Air iDcve loprient Center. These specificat ion acit ivi ties date back to
1971 an1d i!1c I de se veinteen sepa ~crite- cont mits.
acone raL !Vie c Lr ic began this cur rent ef forL in >11--8S>Pi o citsonfamnunry oif 198(), liaving ptrevimoisly completedi similar characterizat ion and
Speciticatioli contracts; in 197b 1979. Philosophies tor establishing
ipa ranoeors , limits, anld test ci rcu ii tfor Conventitonal dev ices like op amps,compiritors, logic devices and data coiv(2rtecs were devvlopel and coordinated
stiiRADC, DES, and the device manutacturers.
Tb i a current effort extended past efforts to o ne(-w class ot devices,poripliec;il drivers and memiory core, drivers, and thusl- estAHi shed iMportant
-;roudwork in tie development of auitomaitic tests andi sped iica tions for
high-speed , h i 1,i-vo ILtAge/ cti rrent logic drive r,-
Current I ',there are approximately tliirty completed and in-processtillnear!interface slash slieets in thle MI L-IM-35 510 prog ran. Six sla;shi sheets
aredeotd o p apsI c ud n the bi pmolar "standa rds, followers, Li FTs,(uads, hi-sc -a , an 10-1 pOLr .ind 10-noise B LI'.s. Compa rato0rs,
trans is tor arrays, and prec is ion th icrs are conta mned in four s lasik sheet s, as
a re CM( S anod A LT I aTalo swIithes. Voltage regupklators are specifijed in six
separtte slash sheet-, and preci sion voltage rete rencu in tvo others T Th roeo lash sheets are devoted to 1)/A converters,, and' one eaich to A/ID converters,sa Lmpl /o. ho 1,d circuits, pe ri phe ral1 dr iverCs, memo rv core drivers, and fi l(drivers and lint, receivers.
0e ; 1,ni a of l sash Shokee s
A procedtirc ior de ye lopIi: l ew ssh sWetS to >1 .a,-1 has evolved throughnlvzgOt ut" ion1-s aa ong all conce rnec, parties. Device -;elect ion is i nfluienced by.kiso r needs, which is de termnvnd tc oiin the -. a rke t place and f Con organizedC c717 it t teeS , such .1s t \Ij Li to r-; a rts Coot ro I Groop ( M1PCAG ) a t DESC, the G1 I
Soli S~te PA levi'011 oiiitee- --nd the irolrnisProject GroupJ 01.Ic t r, ilcs Systemis Commit.O te) Ii AI A. Thiese recormmendit ions are ha lanced
witoma~taeurrrecoineiidaitions obta toed viai the IC-4l Corimi ttee onl Lineair>1 ic coc i ruit s. Devices Of recent vintalge, hai op ' hlit1 pusemlti pl'ca-pp Lcation potential in military systems, prove ii pt Cl c miance , and two or :no re
souirce.s ire gi vcn priori ty. Si u'ele-source.d dev ices ;ire acceptable, espuciall1.- YIbrid devi es al oiii cuIt 1[Apie t sor c i re p r,, <red Av; lihi t':0
dfC V iCeLs , 1o exptressedi :.Ial n! ac; "t kir r lilt cre ii2 11 tU. pt r t i g 1:i1) huie td. V ye opne' at arIC add Lit iona 111 imIpo rtLan1t c o:is; ie r.t I i 1. Montii I it ar 41 1' 1 V L Vl i i Vreccrxineiid dvvices i or sIas; sh , ee t aIct i 0 1 in 11 - i tnh tte I nIltI enl '. 1 ra
J G- S bc L t-o o 1)r -paI Lt io 1 'L Cii slsl 1 o . Ii: etr>, I io t Id L -
Ic- I r obkoi.. t 1rp
1toe nlis t r\ 'i ut shect tf ia the basis f or tiEli a Ii tar1.e -t)L' s 1e ii LCtt iol
;),Ira:ietezrs a nd Il iitS. Tp ical IvI such daita shIeets dot not spec ift% all I f tilec
C.uc5iV 1), 1C, t-i 1, 6C tile nl I i ti rv tnp 0-1C ; t aire ranget aind ove'r tIL common
103e volt."k a;. ci n'e The AC- I~ Subcommnittee, or thle device man I act ore r
Ioso;al - prepi res arpoe spec whic-h conta ins More informa. tion than the
Lds Zv Iata ;1Shet. Goof LICieti o item Is are. negotiated in corm ittees or viadirect otuet iliirnuai.:ctllrers.
jie IiotL'r base for determining, paraimeters; and Ii mits. Devices for
Ltes-t ;ire ptlrcha)se.d iron dtstr iboto rs and are aliso obtained I rom manutacturers
iiLi : A)C recqtes t. TleSt c i rei ts , conpat i ble with auitomat ic test sy stems , are
j1I,))tod. 'File devices ,ire testeud on a Tektronix S32fb3 Autom.at ic Test S's temi
at (;I'. Ordoance S%- tens Fi-ct Coiic Tos t Center. Data obtained at -55 0 C , +25 0 C,
a nd + 1250C ambient is corCo lateh to bench or vendor test data, analyzed,
red need and docome it ed in data iii nd hooks. Recommnended l imi ts are comipa red totil t 1t St e sin;)le dataL~; pa ramot er limits w'hich are pros siy inconsistent
wi tii thie dat;i are rcadi ly identified.
- pecuit irat imi ad di tions,,ci es, and alternate approaches are di- sinsed athel, committe level. DevI' ic 1111atlieS are ident ifiled in lab bench tests.
T., [lr odes air(e alSOiitifed User caution notes are added to thesnee ifC icat ion it- it is dc-,-ud appropriate.
Ijiri-in ci rcli ts are nsua rscommiended by tie ma nofactulre r a nd evalu ated by'kAi1' anid/or (;i J> S oiLte a vi i ab le- test samples. An o bje ctivye i s to miifm izethle nuirler 01 ext,-lill components while stressing the devicie near its l imits.
R'ough klrai t copiLes of the fi inal slash sheet are prepared at GEOS and areforwaraed to RADC for review. DLSC distributes copies of this Spec torxanufacturers and users for final comments. Following assessmrent of thecommients bv all concerned, parties, DESC prepares and issues the slash sheet.
Characterization Data
D~ata obta iked diring, device characterizat ion is usually publi shed in handbooktrnsepairate from this document. Samples of the data sheets, histograms, and
plotS, arc incladeOd in this report. The followjing data handbooks werepuk-blished during this contract ef fort:
Characterization Data for Ml,-M--385tJ/1 29, Peripheral Drivers(Commercial Types 55450 - 454, 55460 - 464) Jan 81
Characterization Data for '-!,,M-3851o/I27, CMOS Multiplying DACs(Comaeircial Types 7520, 7521, 7523, 7541) Jani 81
ru ina1 MetigsAt tended (Cl- internal mecet ing s not included)
JC-41 Committee on Linear ICsCehb. 5, 6, 19809 - Phoenix, AZAine 10, It , 1980 - Washi ngtLori, DC
it7, 8, 198t, - Burlington, UA
R 'it"lMetings
Jan. 25, 198() Contract Plans, Pittsfield, MIA>tIar. -4, 19809 Contract Status & Plans Rome, NY
Au,,. 13, 1980
S ECT 1, 0:, 1 L
AUT'OLATIC TEST D "V ;"Lo'!L'
TABLE OF CUNTENTS
2.1 Introduction .......... ......................... .
2.2 Tektronix S3270 Test System Featurcs ...... .............- i
2.3 Tektronix System Accuracies ......... .................-
2.4 Correlation ............ ......................... 1-
2.5 Data Reduction ............ ........................ .
00
'1 I
- - - --i
SECTION I I
ATOMAT [C TEST )E-VELOPMENT
2.1 Introduction
The Interface 'iL-roclrcuits & linear characterization efforts requiredthe accumlat ion and subsequent reduct ion of vast amou.nts of test data.For both of thLLse tasks, C made extensive use of a Tektronix S-3271)test iyst.i aad a Tektronix software development system. This sectionwill Cescrib -hIl test. sv'sterl and the general ipproaclh to expaniding itscapabilities. A tcw displays of raw and of reduced data, which have hctnideve1,) ped io c tie dCVic' ova Inuntions, will also be shown. Al t houglihseveral .)l the data displavs ;ire somewhat standardized, many of thLlinear device tvpes required the development of unique data displays inorder to effectively illustrate device performance in an easilydigest ib e, fa)rm.
Tet-ovitx "-127:, T ;t Sv'steLi Featores
"Ltoot s'.' tWn i. I CLy Ujui ;ped to preivide a state-of-the-arten.,,inekring tool lor device characterization. The CPI102 S-'steneoritrcl [or has the !)atc./Time Option that gives the abiiitv to store dttand ti.:ne information in the directory and data files. Systemperipherals; include a 4014 Graphics Display Teminal , two CH II DissDrives, a CP22' u Reader/Punch, and LA180 Decprinter I and a 4631 HardCopy U"nit.
For volt. ge and cirrtci t reca ourenent and device stinnulotion, the s\'stenCoiiti i-Is :
l:i:14 ii ,. " Stat i'm, wich contains many test functions and allelecLconics to interface the device under test (DUT) to the system.
.19-3/h4: Clock ;e;erators, e.ich provide 10 driving and 4 comparingrogr a:n~ ole phases.
)pt i n 2', >v,-ocr, Di;iti cr, which provides the capabilitv ofconvertin-., 11aI00 points on a w,-,veform to 10-bit digital values.
Once the waveform it- tiros st)red in emory, software can be usedto determine such thiics is rise time, overshoot, settling time,etc.
Six progrannable vol tage sources.
TW() irog.ra-rmabl' ckorrent sources.
i
i 4 -
4
- " . . . " " : -
-: " i- : -r •" - ' : ,- - ' '
Tempt roaix 4 50A Tenpe ra Lure Cha!-iber , which al2 lows programnabh IDUT tempe ratutres from-. -60 deg- C to + 160 deg C.
ILFFI Bus Inte rface Card, which al lows ,he additLion of 466Leernpat ihie equipment to thek system.
,i h t hesae ha~rdwa ro coo .i)o iie atsa, t he tl?; cat ' e asth ai wn
featk~res:
Acconilodi t c up to 1 23 i yie i ias (bn4 pat e4 OUtp1utIFunct junal testing it 2( Xilz; re eu[.rmLs and .,Lrc-
at 20 Mhiz
XC [es: Di ftecre it t uz a. I:, k,, a: *Le-i , aasforce' I , :wasurc V
funct ioni I pre-CO1ci it EWaL;t,
(;()/'4*0-(( and 111i 11vtLiCa11 t oat oiiIiL
On-Ii no into r c t i e progrxi dev cc op!.w! at
'c,,, ~i ave Zero inalysis ( apl Icsoic
WV Tnv iroane ntt control (-t),; dog C to 1 60 de,; C)
Dati leggad redcccrt i011. Computu L r *rplo ipa
2.3 Ttiktronix Syvstem-. Ac curacy
Th. linear teat prkeg rams we re de ye 1 ped to OtLLIiZe thle i aternaiTLiNtron i x as1emn/i mlu ardwaro as fled. I.; vs SSi efor mmyl neasurem,,entL , the Tekt ronix svs ten Could nut IWru\'11 d.Irequitred accuracy. In the-e cas, Sc ciure adcura tc external e;u ~,.aaUt Hii izd Vii th I LiK 418 BuIS. Two iisadvantages in using i t o,
eq1 LIi JMV 11nt a re:
a) ad d i' io)nalt c ore, i s rt-q uti red to ast a r C theI 4 K; h ucontrol rout ines and,
2e xe t ion t ime for extornalI funct inns is sioni ic antlylu nge r thI an t i ei t o exe uLte i n t er na L. Te ktro n ix t unIC t ion a1S
i-2
Table 2.1 lists instruments which are available for use with the
S-32b0/70.
Table 2.1 IEEE-488 Interfaced Instruments.
Manufac t ure r Model Description
Fluke 8502A Precision Digital MultimeterHewlett Packard 3455A Precision Digital VoltmeterHewlett Packard 4262A LCR Meter
Hewlett Packard 5328A Universal CounterFluke 51)OA Calibrator
Kepco 488-122 Power Supply ProgrammerICS Electronics 4880 Instrument CouplerHewlett Packard 2240A Measurement and Control ProcessorNorth Atlantic 225 Phase Angle Voltmeter
Figures 2-1 through 2-13 illustrate the accuracies of the internalTektronix measurvrent and sLiMulus functions. Also, for certain internalfunctions, the accuracy of the external equipment that provides the samefunction, is displayed for comparison.
On many occasions, neither the internal Tektronix equipment nor theexternal equipment had sufficient accuracy, or response time. These
cases required test adapter circuitry to interface the device under test(DUT) to the test equipment. These cases will be described in theappropriate chapters covering the individual linear device types.
2.4 Correlation
Testing linear devices on the Tektronix system has required theimplementation of many new test techniques. Each new technique, whetherin the form of adapter circuitry or software, must be verified asaccurate. In general, the first step of verification was to determinethat the technique is designed to provide a measurement that is at least10 to I times more accurate than the tolerance of the parameters. Forinstance a parameter of 5.0 volts plus or minus 107 must be measured bya meter that is at least accurate to plus or minus I% when measuring 5.0
volts.
I
I' . 1-3
Vrificat ion of accuracy also included comparison of data taken by thenew technique to data takeni by an alternate method - usually on a benchcircuit. When data from tile two techniques did not agree, an analysisof error contributions was performed and corrections made if it was feltthat tne error was significant.
Correlation ot Te,,tronix test data for peripheral driver devices tobench data uncovered some disc repancites. One discrepancy involved theinaccurate specification of worst case test conditions for output-4itching times. Correlationl unCovered the discrepancy and led to
recomimended changes to thle slash sheet.
.5 Dta Reduction
The pre.sen1tationl Of Lest results is extremiely important in anycharacterization ef fort. Raw daita printouts are required for recoird,but arc usualIly not organized ii a manner that emab Ic', one to scan them,to assess general paramieter trends.
Fort' hR' 1 inir devices , thL hI irs t stun 7. do to reduic ion wa,. or1 Z iAziig
raw data into tables. Figure 2-14 and 21-15 illustrate two variations o',daitaabes Figure, 2-14 iIlustratus do la tA~e n -roni multiplying D/Adevices. Figuire. 1_-5 is the torn of table used for the Peripheral:)r i ve -r de v ice s. The 'left hand entries indicate thle test parameters andtest Condit ions. Iii Figure 2-14 the data from~ a particular device isen lt red in thau en loon be neathI the t empe ratuore at wh ichi the data Wast I N.U.. In l- igure 2'-15, the data taaenr for f ive devices at a particular!em pe ra t ur4,, is! e ntevred1 in c o lmn s. ' no te thI at i n bo th f igu r us theit lowtest specif icolt iu limit for each parameter is on the left of the devicedata and the. hig-h spec if [cat ion limit is on the right hand side of thedata. Th1is enables thc read r, to m,.ore easi ly determine if a mleas urerlenton a devic,- Iics inathamiat ic1il Ly between tile specit ication limlits.
D~ata Summaries, Line Graphs
Data tables, for thle Multiplyinlg D/A with its largve number of datapOinTIS ore too volumninous t or a reader to mentally reduce and detectt rends . ThereforeL th0 lair:.'e quantities of data mu-st also be presentedin a s;urra r i zd I urm.
Figure- 2-1f) is- .1 plot of lineairity error (in L.Slis) tor all codes betweenil anid 801). The pl(L iS, one (it five sheekts developed lor cacti 752C,
multiplying 1)/A device. The Linearity plots were very instrumental inverifying the effectiveness of an abbreviated linear itv test for 7520mu i1p1vi ug D/A dl. vices. A\lt houghl two se peraot sheets werme roll iii redifor eacni fltVije uinder each set of operating conditions, one set ()Sheets allows onle to quicklY aissess qualitativelv, the linearity error
1 024 codes.
iiistograns
TeKtronix software included a basic histogram routine which was modifiedby GE to provide the variations shown in Figures 2-17 and 2-18. Figure2-18 has grouped thirty devices according to hFE. The histogran differsfrom the basic ,tektronix histogram in that the bars are filled in andare separated by a narrow non-darkened region. Figure 2-18, anotherhistogram variation, groups the codes from a single multiplying D/Adevice, according to the magnitude of each code's error. This typ" otplot is very useful in comparing general linearity error characteristicsof one device, to another.
qI
- ' ' ] / ! . ' - " .. .. . . . . . ' . . " ,,
;#v~ iai of #,Io, .24eYv 5ev20 :V 060j'.E~i~4V .e
.0v 00ev :y :OV My
;.ie 2).. .32" . -S i~'e Thnded Yz.ltag'e Accuracies
if *A 3 Vt I.Ror -20v' SONV
*v -14:' f Itdooq .2vp Saov
_______________________ v *-10.1s% of hadze4 -ley No5v
t No I v I *
1ev IVe INV- W
7:1:'~e'.~s ','c _ta~e *Vcc'irqcies
TT-
.I
"4V21- ".' . .
Figure 2-3a. S32bC/-3 - Din. Meas. s. F.uke 5502 D. Accuracies
FLUKE DMM 8502Al
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-ne kc j r ac es Pesolution
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Figiire 2-3. S 0 - Cloc Cycle Accuracies
;4qm kcufac I" fnasr
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0 If
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Fi~ir 2-9 3'26,7' -)' Pin~ Electrorics Card Accuracies
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* - PCENT EPOR
*S2.of Settingq 4.mal .11
L. 11 1 .4 11 till
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SECTION III
PERIPHERAL DRIVERS
TABLE OF CONTENTS
3.1 Introduction III-I
3.2 Description of Device Types 111-2
3.3 Test Development 111-2
3.4 Test Results and Data 111-17
3.5 Discussion of Results 111-18
3.6 Slash Sheet Development 111-19
3.7 Conclusions and Recommendations 111-19
4
Section II
(Characterization of Peripheral Drivers)
3.1. Introduction
Devices for interfacing between TTL logic Lid the outside .-orld havebeen a requirement in military systems for as long as TTL logic hasbeen employed in these systems The devices selected for characteri-.'ation provide great flexibilitv in application. The devices can be
used as high-speed logic buffers, power drivers, relav drivers, lampdrivers, MOS drivers, line drivers, and memory drivers. Table 3-1 givessome specilics on the devices tested and their relationship to the
military slash sheet device types.
Table 3-1, Table of Device Types Specified.
Military ceneric Manufacturer Peripheral
)2vice I)evice Symbol )riverType Type Description
12901 55450 N,T Dual NAND gate and transistor(separate)
12902 55451 NJT Dual AND, gate and transistorconnected
12903 55452 - Dual NAND gate and transistorconnec ted
12904 55453 N,T I)ual OR, gate and transistor
connected12905 55454 - Dual NOR, gate and transistor
connected12906 55460 - nigh voltage 55450
12907 554 i NT )nigh voltage 5545112908 554b2 - High voltage 5545212909 55463 N High voltage 5545312910 35464 - High voltage 55454
N = National SemiconductorT = Tezas Instrunents
The manufacturer symbol column reflects the source of the deviceswhich were characteri;,ed.
4.4
€ ITI-l
'-- - , i d "
i i i i,,t . -' , r, - - " -'
'< ~ ~ ~ ~ " - l th, )cIt~ ' ,,4 ti A ll/ SC+, series 01 devices ',,hiCh h10[11ed
S ,f 1 L-, Itti 'at i a i a P)il tar, Ak vi' e Lvp s are is
to 11• . t A .i
.I I l t I:1 : I I i It .1 , i Lill1,t Io n
d ci I- l - I: L , i t I VO r ;11' ,"
t i r !its ire Sho.,i in i:u4rc 1-2
;/ d A-t- i\,ec t I I-rI o i r t ki l. i.ti S
, t U ,I, t I I. I l e
,i .I c t li !1 J O Ai 0r0, V\"
SI. It iLt , L h SO'ne !; or
I t C I I
(T.. . '+ ,I. . i Iij ' ! V)i ,I (I I ,
,t .,. - '' , , >& ,,, , 120 , 1 1!!, it !l, jriliiltfl:
"t " r i IL I 1 ' ,i[ lola! Irjvt I"frivol- l
.t 1 1 k'' I 1, 1 1 1, : IO I , ti I h.' i , l-,, . ;! t ! , , i t L 0, ' ,tk , , , , V t a ' s
:+. +, t t tC S t S t CI ,l tl . l
I. . .; a Itti
-s I + I t pro id the
I 'it , ':i , 1Et. , L tl, '. .' i tc I i L (:1I1 ;t11l ll S- 127w1
q
Ii-'
Device Device Device Device Device
Type 01, 06 Type 02, 07 Type 03, 08 Type 04, 09 Ty,7e 05, 10
Ucc Ai. YZ Be C2 E2 Sul3 C Uc02 Al Vi ~~SUY AaeB3MORAzva Ail R11 1 11 !111 9 1 1%5 j !? .6 Ls 1 1 is ' Is 17 is i
14~~ 403I
S al YI 13 74 I isi *a At V1. It C1 ft QND At 11 V1. Q at It V1 Go at #I V!GI t go 1 N S
igure 3-1 )eripiiral Driver il.ock Diagramr
Device Ivpe 07TDevice Typc 0-
Device Type 01
Device TYpe 08
Device Tvpe 05
Device Type 02
Dev~~Dvic Type 00...9 ^
Device Type 06 Device Type 0
Figure 3-2 Peripheral TDri.er Schematic Ciruits
III-3
cup
wf
U,7C
'Zi'
-A I
I ~~ I T-4 - -
test syste.i. The adapter has the ability to test all static and staticpulsed parameters required for characterization of the 55450 and 55460peripheral drivers.
The adapter consists of Op Amp and transistor circuitry used to forcethe proper pulsed conditions on the DJFr, while stimulated by theS-3270, Actual signal paths to the DUT are implemented by relaycontrol and routed to the S-3270 for testing. All other static testsare performed using the S-3270 driver and measurement system capability.
h1FE Tests
Within the "static" test parameters, measurement of hFE was the mostdifficult. manufacturers' data sheets specify a tw = 300 us with aduty cycle < 2%. Bench testing indicated that hFE testing could be,lccuratelv performed with t = 100 us and a duty c\'cl, of 2. 1 hedata sheet speci i icat ion a I Yows time I or tht, serVo cIrcuit useJ ijeasutj remet 'S Lo reac 1 its Iiliz va I V .I \ iIna ) r cofl'er 1 S f) ;Wa ito ) 21-
Mi t 1aC L'! I tCiL 0 1 C0 V iCu L -2 1 1 ~,. iL i arI :2 r 71C s:411r : L
The FotrarJ Current Transfer Ratio (h FE) of the 55450, 55460 peripheraldriver is automated usinc the circuit shown in Figure 3-4 in con-junction ,-ith the S-3270 an] the Tektronix 'aveform Digitizer option20 ( ,FW
F_ 7-
- 2-, ] -.....
L
L j
-- . - -A
i me 1 -117 hci est Circuit.4
4Ill-
The criteria for measuring hFE is to force VCE and IC to predescribedlevels -Iile servoing the base current, Ib to achieve these levels.
The Forard Current Transfer Ratio hFE becomes
hF =. IC/Ij with VCE constant
The VCE pulse level from the S-3270 is applied to ine input of the basedrive and comparator amplifier circuit, Al, while the other input toamplifier Al monitors the VCE level of the DUT. The output of amplifiercircuit Al servos the base current 1B until the DUT's VCE voltageequals the input stimuli from the S-3270. The collector current IC isforced to the proper level by the relationship of (Vcc - VC)/RC, sinceVGC and RC were fixed,
Buffer anplifier A2, senses the voltage drop across resistor RB, whichis proportional to the base current Iio. The buffer amplifier A2 wasconfigutred in a differential mode to reduce large common mode voltagespresent on: Rg andI to Orovide increased gain for sinule-ended measure-ment capability need by the !N'FD.
i,< t - illustrates a digitized volta:c pulse from across Rg.
too i T I
!b4OA -
aeO -
600
S I I I I .I. I I I .,
400 -
0 2" 4I 6" see Me
icure 3-5. hFE measurement waveform.
111-6
- ---- --- --- - - - .- -- C- - * ,-,
The voltage translates to 4.370 mA of current. Since the collectorcurre-At was at 300 mA, hEE is therefore 68.6.
The pulsed measuremnent techniques were used vith VC of 3 V at cur-rents Ic Of 100 mA and 300 mA.
VBE and vCE'(SAT)
The Base to Emitter Voltage (V1EE) and the Collector to EmitterSaturationi Voltage (VCE(SAT) pulsed parameters are measured by usingthe circuit of Figure 3-6 for S-3270 and WFD option 20.
R~ CML~ce ~CURRBENT CXT.
I + F5
-3210 7
.rR cE I DI.
L- J
DUT
+ 0. 7V
S-370DD22c? 2
R. Jj
Figure 3-6. VBE, VTI:(SAT) test circuit,
The requirements for these tests are to force a given base drive andcollector drive current undar pulsed conditions, white measuring theresultant base-to-emitter and collector-to-emitter voltages. These
111i-7
i~. rT I I i
V,-e(sat) 1 162.3 mVIc = 100 mA
- b = 10 mfA
400
e a. su r. C Beai e f oe.
Ise" I- I I I T
-Vbel 632 mV
lb . 100 mA
L I
irP3-7 V a .surernent <..avet orm
are accomplished b\- appivinev an S-3270 programmed volta,.e Vj to oneinput of comparator amplifier A2, The other input to amplifier A2monitors the voltaige V'located a one end of resistor RB, causino" theoutput of A2 to servo the voltag.e Vj ' until it exactly equals the inputstimul1i voltage \T,,, applied from the s-3270. W<hen these conditionsare met, thle IJtT base current has been~ forced to the proper drive cur-rent level b,, the relationship of
since Vi andI Rb are ceuistants.
The collector current (I(,) is force.- to the proper cond it ions iiini muchthe same wa\y as Th , vith the except ion~ of a IMuch hicler cUrrenlt r r-ovidod2by amplifier Al. The rolationshin of S-3270 input stimuI'li \'~toforc ing 'ircent I , becomes
Fir-ure 3-7 iillus trates dite \vfI of i sv~~V;eters for a t,,p ical 3 4 0 device tusinc. a base c:urrent 1 10 ' I\ an.!i
collec:tor :urrent of 10,) '7t respec tivelv.
I1 1 Treshold
Input Vjj thrcsho id tests are *Jc!ve loped for the S-32;0U Lest swstemn todeterminne the mar.jin bctwv.een cuaranteed VIL ma:* .S an] theactual V1 1_ input sv.'itch in " point,
Referrlic to *'cic3-8 , the tests wer, imp leenedbypuil mi)iput A,while sa pl inc the outpuLt for a change c state,
Device 'IV _
Input
I I ~4A.4 I I A (sequential 4step)
-. Output Lr*~j.~
Figuo 38 71L Threshold rest.
1 11-9
The initial level starts at + 2.0 V and eah succeeding puls2 I ;docrenieuted by -10 Wi. During the Low level of the pulse, ettc devicC
output is sampled for the VOL state, If the output fails to switch
durin, the sampling time, the input pulse is returned to +- 2.0 V ani a
new pulse, with a level lowered by - 10 m is applied to input A. This
process is repeated N times, until the output switches to \rOL , at which
point the VIL value is recorded
The input \ri l threshold tests are performed in a similar manner to the
IL threshold tests with the exception of the initial pulse level anithe delta increnent (refer to Figure 3-9).
_ zl.3V Frog. Level
23A N (sequential a step)
Devl :e 0.':'V _ Initial LevelInput I
ft--1--A I b
IV H
.evice Lutput CL
Note: i. A ti-ne device output is Swmpled for swtched state.
Output
•'i.ure 3-9. Vrif Threshold Test.
Thc initial level starts at +- 0.8 V and eachi succeeding pulse isinc re-etedl by +- LO mV° Durin. ' the hi,4h level of the pulse, theSdcvicc output is sampled for the \'()
F-1
U--ruCl
Lni
ol T
en 0en
ro V
rn ~) l
This process is repeated N times, until the output switches to VOll, atwhich point the V-1 I value is recorded,
TtlI, TtllL, TPLI[, TpIIL
Transition times and propagation delay times for device types !. -10)were measured using the S-3270 test system, the Tektronix high Per-
formance Option (IWlO) and a specially constructed test adapter.
The [P11 option provides for high accuracy time .neasurements, skew time
corre:tions, low device pin capacitance (<18 pF) and buffered scope-
type compensation on all device output pins connected to the S-3270svsten. A simplified 1-1O circuit diagraii is shovn in Figure 3-10,indicating the different signal paths, attenuators, and output compen-sating networks to provide high accuracy measurements, Correctionfactors such as skewq tim, between S-3270 sector pins, comparatoroffsets and output compensator networks are all handled uadar separateS-3270 calibration procedures to ensure integrity of the system.
.Ambiguities can occur as a result of time measurements dependency onsupply voltage, temperature, load circuit consideration, layout andtest equipment inaccuracies.,
Figure 3-11 is the schematic of the load circuit for TTL gates thatwas proposed b,- JC-41o
: ,,'c C
._
IiL!cure 3-11. wc-41 load circuit for T'L gates.
This circuit is used to simulate 10 standard TTL loads. Comparison ofoutput waveforms obtained with this circuit loading the 55450 "gate"output versus 10 stan.lard TTL satei loading the same gate showedsimilar results. (See Fi,,ure 3-12A, B).
.. _: 1ITI-12
A -.-- -I•
Figure 3-12AAE EPTPLI usin= C-41 load circuit
Figure 3-121,
TPLH using 10 TTL gate loadingVCC = 4,5 V
The JC-41 load circuit, however, does not simulate worst case loading.The 400a resistor only gives 10 times the nominal IOL at VOL. Noprovision was .nade for simulating Toll loadinu, CL isn't high enough toreflect the maximum input capacitances fron a TTL gate (approximately5 pF)-
The JC-41 load circuit also increases the ambiguity in propagationdelay time measurements.
Propagation delay times are measured at the 15lt points on the inputand output waveforms. The flat region in the output waveform occursnear 1.5 V. Propagation delay times can vary by as much as 4 ns as aresult of placing the output decision point on the low side or thehigh side of the flat region in the output waveform. This i 3 clearlyunacceptable,
The circuit shown in Figure 3-13 has been used as the load circuit fortesting the TTL gate portion of the peripheral driver ICs.
TIT-13
'fo Output L
Ci,-50PF 6 K VB 25t.
Figure 3-13. Recommended TTL gate load circuit.
This circuit eliminates the ambiguity in propagation delay measurementsand also stimulates worst case loading. CL was raised to give arealistic value for ten TTL gate input capacitances (5 pF/input). R,
was added to give 10 x IIHMX . R2 is selected to give 1o = 10 x IILMAX
at VOLMAX .
Figure 3-14 shows the output waveforms that result after changing theload to the recommended configuration.
Figure 3-14
TPLH using recommendedload circuit
VCC = 4.5 V
This additional load capacitance increases TPLH, and the flat regionpreviously noted is eliminated because reverse recovery in Dl occurs
through a higher effective impedance. This eliminates the propagation
delay measured ambiguity.
Switching time measurements for the output transistors and for thecomplete peripheral drivers were also measured with a CL = 50 pF toreflect a more realistic value of load capacitance.
A
Supply voltage variations from 4.5 V to 5.5 V have resulted in vari-ations in switching time measurements of up to 2 ns. The majority ofdevices exhibit slowest switching action at V c 4.5 V so this hasbeen selected for these measurements.
111-14
efer to Figure 3-l5 tor a graph of LVpical variation in switching.paraneters with VCC.
Tthl Cl=SOPfd Iol=200ra Rl-SOohmskQLL TIME '
14 .
13E-
L
4 . 4 ,2 4 .4 4 ,6 4 .8 SA0 S. .4 .6 =, .
D': VOLTS
i igure 3-15 vs V
Transition time tests were the most difficult to implement, since theyinvolved switching times in the order of 10 ng or less. Careful con-sileration to the test adapter layout, inductaice, capacitance andgrounding were critical to ensure that clean output switching waveformscould be azhieved.
Figure 3-16 shows typical output transition waveforms from three dif-ferent vendors.
It should be noted that the output transitions are different in the8%"/ - 100'/, and 07, - 2;3% regions for each vendor,
Correlation of S-3270 transition and propagation time data to bench
data wa:3 verified by using three independent methods. These verifi-cation methods are as follows:
1) Measure data on bench circuit using oscilloscope.
2) Measire S-3270 test alapter on bench using oscilloscope.
3) Measure S-3270 test adapter on S-3270 test system using
oscilloscope,
-iT-15
VenJor A
T TLII
Figure 3-16,'
vcnidor
TTLI
vendor C
TFT IJ
3.4 Test Results and Data
A total of 85 peripheral drivers were tested on GEOS' Tektronix S-3270.Each device was sequentially tested at 25C, -55C and 125 0C.
A typical data sheet for a group of 55450 devices is shown in Table3-4. Data for up to 5 devices is displayed on a single sheet, Thismethod simplifies comparison of different devices at a single tempera-tures,
The data was also recorded in the form of histograms for selectedparameters at three temperatures. (A sample histogram is given inTable 3-5.) Included were the following:
55460 tTIIL tPLHtTLH tPllL
tPHLl tDtPLH2 tR
tStF
hFE '1,2 VCBOIVBE 1,2 VCERIVCE 1,2 VBEO
55451 tTHL tPLHtTLH tPI{L
55453 tTHL tpLHtTLII tPHL
55461 tTIIL tpLI
tTLII tPHL
55463 tTIIL tPLHtTLH tPHL
This data was published in January 1981 for RADC in a 211 pg handbookentitled:
Characterization Data for MIL-M-38510/129Peripheral Drivers
111-17
(55450, -451, -452, -453, -454
55460, -461, -462, -463, -464)
Sample data sheets and histograms have been included in the .Appendix.
3.5 Discussion of Results
Most of the test data taken on the 55450/55460 family of peripheral(rivers was within the limits proposed by the Jc-41 Comittee. Theexceptions were the result of changes in test conditions (for example,
changing the load circuit for timing tests). Although data on anumber of parameters fell within a relatively tight spread relative tothe test limits, no attempt was made to tighten the test limits due tothe relatively small number of device samples. The exceptions arenoted below.
Short-circuit output current I
As originally specified, the IOSMIN specification was tested at VCCAX.!ut IoqlN is lower at V 'C\IN. To ensure that lOS would be within thetest limits over the full supply voltage range, IOSMIN is tested at\.xj lfl and I is tested at Vcc>X
Threshold Voltage (VT)
Threshold testing of the peripheral drivers gave results that werewithin the expected range of values. The nominal VE was approximatelv1.3 volts at TA = 25°. with a d VT/dTA approximately -3 mV/CC. Thisagrees well with measured VT values tor standard TTL.
Ireakdovn Voltage, VCBO, VCER, VEBO
in all devices tested, VCgO was greater than 17 volts (or nearly 50',)above the minimum breakdown limit. For VCER, all of the devices were_reater then 22 volts above the minimum test limit.
Vendor A showed slightly lower VEBO than Vendor B (approximately .5volts low.'er on the average).
There w re no significant trends observed in breakdown voltages versusterye rat Lire.
All breakdown voltages were taken with the substraits pin floating.
A
[II-1S
Static torward Current Transfer Ratio (hFE)
The JC-41 Coirnittee test conditions specify that hFE is to be measuredunder pulsed conditions with tw = 300 us and a duty cycle < 2Y,. Thedevices were tested over a range of values for tw with the duty cyclefixed at 2'%, with negligible changes in the measured values. T, waschanged to t w = 100 us to simplify test hardware.
At TA = 25', all measured hFEs' exceeded the minimum test limit by
greater than two to one. As expected, hFE tended to increase withincreasing temperature over the full temperature range. In all cases,
the devices tested exceeded the minimum test limit by a reasonablemar-g in
3 6 Slash Sheet D~cvelopment
The military specification (MIL-M-38510 slash sheet) on the peripheraldrivers was developed in parallel with the characterization effort.
The majority of the slash sheet Table I parameters and limits were
recommended by the JC-41 Committee on Linear Integrated Circuits, The
major changes occurred in the switching time test load circuit and the\C specification for the switching tests, As a result, the switchingparameter test limits were relaxed as needed to accommodate the newtest conditions, Also, the IOS testing is now specified at bothextremes in supply voltage in order to have the test data reflect theworst case.,
3,7 Conclusions anJ Recommendations
85 generic 55450/460 peripheral drivers were tested on tEOS' S-3270 to
characterize their clectrical parameters. Bench data was taken tovalidate S-3270 operation. With the exception of switching timeparameters, the devices were well within the test limits,
The switching time of the devices was slowed as a ., .- It of the revised
test conJitions. The test limits for these parameters have been
,idened to accommodate the test changes.
1111-19 i
*"-
APPENDIX -SECTON III
PERIPHIERAL DRIVERS DATA
SHE~ETS AN) HISTOGR\NS
11I-20
I IT '
U') IfC;U ,
4, in rin -t J
Lq r -X
e 1$) 1, I w
) e. e- r~f 1; CA r L 1
M 0' w" 'I wi (.) (LO (- -
i*t -*- .-..- ' r -) Ri j I
WLm lt -r t Im
'.1 1- L;
fu mL~ (PCI m" r' (U
LU
uj DI-4cli L -, K C
U) I - L - f m
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VL - .. - 3 q. .) I
L&J~~~~~~~~ Tf A Iii E '32)1~( ' ~ U
4L l >-; 11115 U.. 3l l~
kv 44l f%) klGA4e (SD, 4S U) in (. eD if U)t
I f . tp LA ) U) LPX "I ~ C-.. A L W S I (71,(0(04.(v r.)P ',U. 11 Am L U 4- W j ru f 1-c3 kjL
0 A . -n"It o'.-14 IV to4 f.)C in Of I (U
r:4. T- (0_0 Yl r Y-Ir-
to~~( r..,. (\.U4I
r-1 jlC1c L n
CL f.4 1 K- 1; 11 U, 1L* 1.4K (1> cfl ,UK t.,( U.' L LA -) t
LA VfI r- M1( M. ((I) ru a;I) ,I40 (n lu
Y- IF U)- 1. 17' 107Ul
Ki oj co4)n C
.4'l I I I
Cy~~ ~ ~ t m cu m~ nUA WO) C-P Ku in cu r- X6m0 - ,90
T -T j -j x -1 3q : -
kf Cl U. U LI) L , U, in 0 '2 I0 1A C. I
I. i ( i
Iii a . a I I
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4- 44 1- 14 4- 4 - - 4 -4 4- I -
tr u- 0
Ulf ' ) 2' ~ '7 ~ 2' 2 ' 2
o c-. I(L
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UI) c~ MC) m0 (D OD 6 i) Lt. 0 A%. I u)) U)l A c
v.~ w~' L' q-w --D .
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'w ~ CU Ii'! i 6 tA L IC-C F111 cU I) U)v)'- r5
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I I L
a F_ 0n en '73 r nM D, v -1> ci fUY C Q tflc
N- ~ I-W i r It'*,I o o i'
D LL L<iW ;~ , j00 0 - ~ ~ ~ 'w Io cu w 'lI C
011 1 .. rum ,-rum r, CU' c- rm - Q eni- m(Ulm -mf Ica
_r CI) L) 3: X j~ _j _j
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LI) k11 Li) U) Ln V' U)U;
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(7 m Ir ","
W DC- W . f--- r- DW LA o C
V I~ k7 E F-Tk VCI) nG mI IV I, li I-o - r, ii
(n -I.ulco m v i 1
w&C' WC- WWo w , -r- co wW I' cju u I
Cu N.IC 1116 (fU O,,~ i. u
not ( , mU Ctli
f- W~ W LIW I J w KIkn C', r-)l Wc-, m N In (.0i C.)~ in i 4
(DN WU~ r-.u ('i -U C M
In Li I t; (r- ) Lor I, i (I; ) - J I
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(t*K. 1,c .t. 2-i L
<T I
Iii (-4 c) (.) C? 6)
In 61 -, I-) ...; t -t i
CI
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11 mt L'q LOG 1 U 1 - '
*n ('-() 0. .n 4wC~ AJ. chr' ODD
C, - r-- r 0% MO (Oco C,3 M 0g um mm
C> LA-, cD n A L n es c*r- Fnm (u Ln r6v C
Or- -r- ir- w w r- r- t~w w M(7 U lO u Mm
t (Di - lEEVr.
00 n CL (Q A- If
41' toC Its> to ()(n <D, s. e EIn f' u 01-a 'n" r-C .U 'a' C
U1 jmm mC.) (vW mu ine7>. C
(c) LA LA LJ( (I ) q.- I't-- CC
r- 00 - - -(D to "0 - -. (af
Z>W~~~ I AU C D L
C) M ( ) LA L Cu ;u (n 0 C) e )
CDR
22- t) <r <t Kt Ct
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a- - U) a. <
cuI :> 2>
17, I. 11. ur- -,~ I -. slp I
"'s, t. o L ; e
R.j ruu) co .- -v wqo 'r-
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U) U) UILfl WW ( 0 - r- co Goa)U, mm~ Mm v
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V) m (!> - W- -T r D L
Dm GZK moo t-t F00 c 7 Lc
(0T LA( C7 t' -O OW O CW W) LA I
LL r-L-,n- C-r r-C cl)-:4h wm -D to W- . r 0
ww w_- - D 1- r- 1. oc M_ U (1o
t- ru -
LA OU mm lf n LA0 L.ru 00 mm) WL tL C
* . cocoL UI I L t- C ((. ILA m( (1 m ..~I ;; Q- ,O 1O -"l
Lb u) U)U r-'- in.- o'- )CU ( nl)~ '
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co* m.. m v 0.5 . l( * ~ ; r OJ 'r)"u C
V) lu fl - - v I U- -. ~zz (!l)~
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(A -4 ~ .
CL u I ~ r
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t i L, W '
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SECTION IV
MEMORY CORE DRIVERS
TABLE OF CONTENTS
4.1 Introduct ion IV-1
t 4.2 Description of Device Types IV-I
4.3 Test Development IV-4
4.4 Test Results and Data IV-4
4.5 Slash Sheet Development IV-14
4.6 Conclusions and Recommendations IV-14
-a.
TV-i
S I IoN l\'
A'.IEORY CORL 1W. 1VERS
-4. 1 tit odiC L Loll
Ilir 3> 32 / 326/327 iixiiily of nicvlicry core drivtcr i , llt- I if. L iilc OL
Core drijxrs Lo Lit ciairccrLc-d lor RADC. i"'-c Il u ii rrvciuii>
uiii;itui L i L:,u 1 1c-urL dCIVLiCCS- ill il iLary uYsc-i.,ut t
iisLruiuruLs alnd FiirCiLd S>rMjitndLCiLuircuFi 1-C1 i1litd t ic'dziib- I i I 5- Jr\' c, . It i- c xpc LtCd, Icc-jl.Vt V, LilIL W -, c 1 L II U.c i i i
-y ru will 1t oli I doctllc. j i i-4-L cjt ptc i I i c oll Lill-
i vir LrLc_d anld Li It i V hItII Luil-lSi i tct LhL' ImiliLt ivy I i- c
[ab Ic -4-I I'Lihlr cI Pr V iCc 'yjlt2 S Sp CiiltCd
D rv i CcL "- 2citc ric I itI zIi cI Ic L ,I kt 1, 1 ) t p t
~YPt iypr c-ibI C I t iir i
I M1-O[ 5 )3 2) D, Diiil Ui c ind dtil1 3t'-(i 1 ) C Quiad - in
13 -()3 ) N-17 I, t Quid sc I: Cc
F CI i Ii-Cih i[d SCM i~ lcu IC Lu0 1 kd it -Iu~t 1 LC O il I 1iI
lic 1ii,1 li it I i~ t ~ l~ I rer boL c I111111 rc( 1. LicC Cu4 Lllcs u ;0 c; I- iS t i
-I wcl v, it 1 ht, cjLiC ( L'1i. Od . cItl r Crlduc>' illt ucbUt \'crc iittL Lic ltdtcd ill ltt ChIiaiCLcrt iiil I I rl)t inc- i ic 't d Id
,11 l~i t i' Q~A A , lli id ii t tI c I~t i.-L ' IIt' I C ,ill iJ,, ci I LI ccl t i,
Ucc 1 Vct ti)o I Ic, iL Ii c 1,1I ~c ti v i -cld
iO i ) OW) 32o/ 307 ii- -, I dry icc- protdtc 00 niL\ ;tu ci.-- c c -iIl
*-CiJt,iitil it V 1 0- rcmc-V c'1, C-i IV- tIjj11tCcIL ioiiS lu. ci ii-juiud of
til l. ;IF LOWl tic V iCC, l> ii 1 Lit FP Lc -c '4-1, 1nti tO L1ii cik iciu~ i
Fn 1 1 i 11 ',1 c -, VIic input c:ircit ic -t I iIL , r L \t -c r
I cilt c(' ti i- ii 01, iii , st Laidarcl it ['FL t, Lr' * uc-cc iC, t htr tlrii
p I c d L, c v anti Lit -itLpkit. SLI~wc 11-c dru' i llcd i l crc-ut l\' i ) I c rt
t I i.iiihti litcl )ilt- tt't pricic rr tiintit L>
I-
iJ
ZI'~i
r-'~flI7 --
Zzi21 I
4m.~inmm -i
I~7~i> ~~ ~
II -
Z~ _---L~~
I U I
I 1
-,r-r - -
* II
C)* I
t I I I
-4 '4~ V C >~*-'. 4-- C) C
V * I.
- '!~-<4K~y \T
I-,
U
EC)-zU
* I
-;~ ~
I -~I----. *- -~---* * C______ --.4_____________ S * C)
s.~j -~
*j Y * i C)(I
I - C)
'-, -'-I
flhe pr imaty di te r(ncL btCwen the 55325, 55326 andc th. -55327memotryh IL coret drFi Vers is t I W ir Ok I p Lit arr angt-me nt . Thv 55325prvdstwo sotirce. and two sink ou tpu ts . The 55326 furnishie.- 4 sink outpu,'tsand the 55327 has 4 "source outputs".
4.3 Test Dce Iopin L
filhe test- developmntl icc memory core drivers was si-milar to the benchtestL development for peripheral drivers (see Section 3.34. V'I f VI L
IK V [ip Ifl f t ItI CC (o ff)' , CC I and ICC2 are te Sted inl muIch thetsame way as they' are for standard TTL gates.
All other test- parameters require special consideration, however,s ince theV LInVo), lye plse eauemn techniques or hligh speed switch-inl ofi the dev ices; under test.
A simp lifted schemiatiL tor theL - tat ic Lest circuit is inc luded in'iur ,-3, (Thei acttnal test box developed contained all of its own
l~asdi tve S r iaIis an d power supplies.
Sclilritic-s at the switching time test circuits are included intiigures 4-4, -4 5, 4-k) and 4-7. AuIWtmatic tests were not implementedlor characterization of this device family.
,s les PesoI tsInd D)ata
A total of 24 memory core drivers were bentch tes ted at T4\ 25 0 C.Sample test data of devices parameters is included in Table 4-2.Les t in iie 55325 family of devices is straighitforward, requiringimplt: loa;d circuits and TTL type test conditions. Testing is
COTIityl tted , jiuwever , by lte large combination of input aInd outpute u ti t rat i us requifred by the device unde r test.
Te sts tha:t rtCikqu ire 1 nusn'lte niq ties are de scr ibed be low:
a ti tj' '11 It a e' u
V1 (SA F) j :vea >1red us i nt pulse, tecchniqite s The ma tnufac tore rs data
iht-cL tsp-c if ie that tW 200 uis with ai duity cyc le of ! -I ."teii vkcet were me aisnredl over a range o i re pe titilon rates and dii ty
c It . ILi is i U C ij( 5pA) was relatively inisens itilye to chiangesin !),ih to>-, cond it ions . (Rter to figuire 4-8.
i> pa rame Lel r Mm t bhe mleaIsured at the D171 p ins, to minimizeins remcitiL erior-.
-
.-~~~r -- 4 N D C
c'I -,o :c
DON C, T
7.1
0-E ! I-A < - -s- I II T
4.. 1 7 -p 2
k f®3
Notes: rei a's are . the i-ener7ired oositior.
2. R! = '-O ohms -S carbon.
3 R2 39 oms t carbon.4. P3 = 22 Dnms % carbon.
I"',ixre ' -3 S imp[ified Stoitic Test Circuit Diagram for
q YNemory Core DriversSIV-6
WIIt6 1 0 .14 --- ,3 12 10 A I
90 It I
IP T I
'00
Notes: 1. The pulse generator has the following characteristics:
PRR = 0.2uS, tO = 200nS, Zu t - 5) A.
2. R, = l]oh, 5 carbon.
3. CL t5pF 5%, including probe and jig capacitance.R 3o3 ohms * 5-a carbon.
Figure 4-4 Switching Time Test Circuit tor Device lype 01
' IV- !
: 4
4t. 1 2 il 1
.4 C 2.H
:o.sT.e2u_- -eeao 0a th olwnUnrceitc
-4 7 04 -u
I V- 8t
oLL
5C, pf
Device Type 02
De.ice Type 03
-- -
Notes: 1. The cuise ,enerator snail have the following characteristics:
N -out z 5 ) orms - For testing 11 (after switching)
PRR 2. Hz, o - - Forila other tests.PRP . ,t 2QC'0.
2. C- F" (including 'i; and proce caacitances)..3. L carbon for V'- tests. For all other tests
.- "caron.- .. ect "to ".eCa:.o) f cr evice tyre '2. For le ice t-,me "
connect ,) to "JO2
o ros ev i - e t, .7 e .3 nLD.? b., -K 4evc ' only).
-, Switchini'. I m, rest circu t for Device Types (2 and 01
1 V-9
9 rr
0 .1
i-V 10
V(SAT) = .3 B b
Rep Rate 10
Duty CyCl1' 2>
V (SAT) = .389mVxRep Rate =10 n)
Duty Cycle = TO/
V(SAT) =.3 tW"*Rep Rate =10
Diuty Cycle = 2 0
Figure 4-8 SALurat io 0 'n
sVJ itc tii k i cI, t t C v i> I, i I V
The fo IlItwing ,,i ide I in s were ii-; I! t I i i , I'll 'A i I' I eu i Ic
switchIIing L inei ncIsiicm:
I,'rt ciruit were bujiL 11il.e Ill lliinil'. iiluckd
[huise throught real Fl-url). cI ' Iljl j l ( I I indiir lt i
High fireqIOenCY Wir ilig tLChl(l i-'s 5>1 ,; I LII-u 11il
2. AI I powe r s upply \'n tn np I iiF I > c ice to ti
delv ice tilder teSt (DV[) 17ih 1 p CIi> eF
the [i'l .lecked for litnise w it it illI
t3. NThe- tont zi bandI Iw id th I i. he fi tn 11n o, Iill 1 Fi, ,hr, in
Ili( probes, work- t [Cc ted ulk1 I II i IL I, i- ( I n lit w'IIl
_'1 \ ll probces were adjiLl ted ioi .u r c 5
Pi. th ine ,kuw betwceln ClIblul e ' :[ ' ,-I IL
H)[ie i nl)u t I IIIs I n t LIn I W. i r I I .1 1 1. L i lI
t-(?IC t inns,' IhU Inpi t I1 :1.......Ct. H
[)n -si 1)1e tn 110rie V t '11 LICe t I :A i l: 1 11 m I.I
*re f1 IuC t innls InLght n)cumI I
7. ", ppy1 VoI tcigL, - c 1-c C:1Fec I l:IV I> c I t. , I st cIi
L Llad !11C;Ic l~iilk.II 'i> IV ts I SII
ol'it- aruniamly was- dis;COVered inl I Jil ':2. s Ii t I Z n1ll c nnLpu t
Lnr theit ~3 dtv i I. A,, -,homn 1 1 1 n 1 it , , II w i Iii W it-
pit Ltrsi t inn shw-s .i VeiV lhiI~i i II >, uhl Iitnnut t i)pro\ jl.TALL Lv [I() ii itte I t, i it- 1 . 11 liIlli I tijll. LL inn.,
F II Fil)or t ip t -)2-
t K
\c idor B
Olne poss ib I t exp I anation Lor tb j i i t i2, nvoIvc.- reversc re, )v,2 1-\
action in the output tLC
A ~~~~As Shouwn ill [Li EC-i)c 1 Ii Lh, . P
d1~~- b\ iih I' Li. t AL -: i LL dc J r w' v' ~iL t I-
CQ 1 - l 'c UI L . . 1. L t 1111c I 1, 1( . I _L . I 1 I I I :
Luxt 11L t) 11~~- I- 0 i I 1i p-1 t-U ' 1 :1i
LII t' o Pt iii ld 1) Lu L
I
c 0' u ' 1 Pd I IC L-' ' 1 1 L -
t t It :1 M6g
As the totem pole driver (consisting of Q2, Q3 and Q4) changes state,the bias voltage across the emitter junction of QI changes from theforward direction to the reverse direction. Reverse recovery actionbegins in the emitter of QI, tending to discharge C1, rapidly through
the emitter of Q1 and through Q2. After recover, Q, is cut off and
CL is left to discharge through RI.. Hence, the output of the coredriver shows a two slope transition. The steep initial transitionis due to discharge of CL primarily through QI, and the flatterportion of the transition occurs as Cl, discharges through Ri .
A similar effect could occur with emitter breakdown of Q1 during ahigh to low output transition. Further work is needed to investigatethe exact cause.
4.6 Slash Sheet Development
The military specification (MIL-M-38510 slash sheet) on memory coredrivers was developed in parallel with the characterization effort.As the test circuits and procedures were proofed out in the takingof device data, they were also incorporated into the slash sheet.With few exceptions, the proposed slash sheet Table i parameters and
i'LL:its are the same as in the manufacturers data sheets. Limitc:.anges were made only to switching parameters. An anomaly wasobsurved in FTH{ at the source outputs for the 55325. Furtherinvestigation is needed to fully understand the cause,
".7 Conclusions and Recormmendations
Twenty-four generic 55325 series memory core drivers were bench testc, .at ;EOS. The devices tested in a predicatable fashion and withinmanufacturers limits except for selected switching time measurements.
The data and slash sheet parameters and limits will be reviewed byinterested manufacturers prior to issuance of MIL-M-38510/130.
IV- 14
SECTION V
cMoS MLT 1LLrPL~YiNG D/A\ CO'Ay URTUK.ls
MIL-M-38 5 10/ 127
Table of Contents
5.t I n tro-duc tion -
5.2 Description of Device Types
5 3 Test lON >len(nt V
S~t -; 4l 1CS I C> . 4
5.5 Di ;cuss ion' it
5.7 (-(C I uiWIS .I 1d RE1')MCil~d t .0-
-7 AD-AI02 841 GENERAL ELECTRIC CO PITTSFIELD MA ORDNANCE SYSTEMS F/6 9/SELEC TRI CAL CHARACTERIZATION AND SPECIFICATION OF PERIPHERAL DRI--ETC(U)
MAY 81 J S KULPINSEI. T HACK. T SMNEN F30602-8O-C-0OS7
UNCLASSIFIED RADCTRIZN
SECTION V
MIL-M-38510/ 127
5.1 Introduction
CMOS multiplying digital to analog converters were initially introducedin late 1973 by Analog Devices. Since then these devices have been usedin many applications and several other manufacturers have incorporated:hem into their product lines. Table 5-1 shows the CMOS multiplying DA
converters to be specified in MIL-M-38510/127.
Table 5-1. Table of Device Types Specified.
MultiplyingDevice Generic Manufacturer D/A Converter
Type Type Code * Description
AD7523S A,M 8-bit res., 8-bit fin.02 AD7520' A,'1, ,N 10-bit res., 10-bit lin.03 AD7521; AMI,: 12-bit res., 10-bit lin.04 AD7541T A,I 12-bit res., 12-bit lin.
05 AD7541T A,L 12-bit res., 12-bit lin.**06 DACIiZOLD N 10-bit res., 10-bit lin.07 DACI220LD N 12-bit res., 10-bit lin.
08 DAC1118LD N 12-bit res., 12-bit lin.
09 DAC1220LD N 12-bit res., 12-bit lin.**
*Manufacturer CodeA = Analog Devices'.1 = Micro Power
I = IntersilN = National Semiconductor
**Best fit linearitv. All others are specified with end-point linearitv.
Later deleted in slash sheet per agreement reached at JEDEC IC-41meeting, 12 Feb 81.
-7| "t... .. . .'-- - --
\ recol:unendation for characterization and possible slash sheet actionwas nade, by the JC-41 Committee to RADC. Some device features whichshould sustain this recommendation are as follows:
t. Fit'. t io)io lithic 10-bit D/A converter. (AD7520)
2. lkiny potential applicat ions ind uscr options.
3. ('u-t effective with other competing process technologies.
4. lk.\icc is sourced by several mianfa cturers.
. pW , r dti ss i pa1t ion .
i: ni Iitarv systems is high.
.2 I ,,-r rpt ion )x L)ev icc Types
,. . ties milt iplyvin ,, )/A converters are fabricated with at- i t 01, t n Allt ill-, ladder ivt - I C, OS int,*vrated circuit. A
tilt ina1 - .11., t 0! , pc. : ;r,-ti t it; showii in Figure 5-1.
I h 1- 1 O 1 O
06 11k 6k
Si I S 3 1N
Sly 1 MS8I BIT 2 SIT 3 BIlT N iLSS)
DIGITAL INPUTS tiTL, TIL CMOS COMPATISLE|
10: , , ultiplying ,. Converter
',I ] .! rv!d'l" l' " tot's colisist-s ol i ic -,|r r u material
.,r ,, .,, t-) pro\,idt, tlIL' lIctw(l)r , 11W1 N )T I ll [ 1 on ' vendor's design,ti.: .r,. .tr 1 1.1ve, linrina walluv'; M I (,€ K ohims and .10 K ohms
t -i{ ,Ill ,(hso)I~t ti t , c perat rt, Ct' l I icie t 01 approximately
-i'>, -,, i/)t nd ,i t rack inii ttprt - C )e t fic ientL of bette'r
S, voltai.t' is ppl d to the t, -1'erence teriina o OIL' ktruiture,
t!,c, irt'cisiori of the' binary division of r r C . ov erned by OILIrtcin ,, of the resistors and the drop across th associated switches.For proper ,per on the output tnrlv inals Komtl and lot2 shouldt, ',,; Close to lid reference as rossible The 010S switches of the
intt rted cir ructore are shown schematically in Figure 5-2.
V-
--- ..... -- 7 - - - - -- -. .- '- * " 7 --* " ". . .
I 3 TO LAOI|A
OrL/TTLIcFMOS
Figur 5-2. r,(>)S Switch Schematic
With the application of a DTL/TTL/CMOS compatible logic signal, two
CMOS inverters assume the proper states to drive their respective
output switches such that one is "ON" and the other "OFF". The end
result is that the same ladder current is steered in either direction.
A logic "high" input results in an loutl switch position anid current
flow.
Most applications of these R-2R ladder and switch networks involve an
external operational amplifier configured as a current to voltage
converter. The feedback resistor for this op amp is one of the
deposited thin film resistors. Figure 5-3 shows how both devices are
connected together to form a voltage output multiplying DAC. Thedigital input word determines the states of all of the bits from the
MSB (Most Significant Bit) to the LSB (Least Significant Bit). All
of the binary currents gated through logic "I" positioned switches flow
through the feedback resistor to the op amp output. Therefore,
Eo = -loutl * Rfb
The current loutl is the product of the reference voltage and thedigital binary fraction divided by the R-2R ladder input resistance.
lout = D * Eref/Zin
where
D - Bl*(I/2) + B2*(l/4) + B3*(1/8) + ... BN*(1/2 expN)
BI thru BN are 1 or 0.
V-3
ANALOG 1001V R-10k 501V R-10k 2.51V R=I0k 1.26V R-Ok 0O2VINPUT .--4
0 5mA 0.25mA 0.125mA 0.0625mA IVA
2R 2R 2R 2 20 2R 2R
20k 20k 20k , 20k 20k 20k
10mS 10mV 10mV 10mV 0.6mV
RoN RON Roi R ON
2011 401! 80- - 1601 " ±z TERMINATION
DIGITAL IINPUTS I
SIT.-I , ,IT 3 48T4 BIT10
IMSB) I 2 ILSB)
2 1OUT 1 10 RFREDAACK
E0 . I OUTI IEF.ACK
+ EXTERNAL WHERE NGITAL 100101
OP AMP 'OUT, ' 102 4 1 Ok.- I
Figure -3. Typical Voltage Output MDAC Application
ior the ore common 2-quadrant multiplication application of an 8 bit
dU.vice as shown ia Figure 5-3, the relationship between digital input
a;id analog output is as follows:
)j,;i ral input Analog Output
1111 1111 -VREF * (1 - 1/2 exp 8) = - VREF * (255/256)
loo (.0001 -VREF * ((1/2) + (1/2 exp 8)) = VREF * (129/256)
1 oiu( 0000 -VREF * (1,/2)
. non njwil -VREF * (1/2 exp 8) = -VREF * (1/256)
tjIh00060 0
V-4
1 - - --I *'-- "..i r- .
This current mode DAC has an output impedance which varies withthe input digital code word. Parasitic output capacitanceinteracting with this variable output impedance can result inpoor closed loop response (either reduced bandwidth or
ringing). A compensating capacitor across the output amplifierfeedback resistor is recommended. Since the output impedance
varies, the noise gain of the output op amp will result in avariable gain to noise and offsets. The op amp should thereforehave low offset, low offset drift, and low noise. Also grounding
techniques should be given careful consideration.
5.3 Test Development
A variety of devices were procured from three manufacturers as shown inTable 5.2.
Table 5.2. Device Types for Characterization.
Generic Manufacturer Quantity Date Code
Type
AD7523UD Intorsil 10* 7947AD7523TD Intersil 6* 7947AD7520UD Intersil 11* 7947AD7520UD Analog Devices 15 8006AD7520UD Analog Devices 10 8019AD7521UD Intersil 12* 7947AD7521UD Analog Devices 7* 8030AD7541KD Intersil 15* 7949AD7541TD Analog Devices 10 8038,8021DAC1218 National 10* 8045
*Data was submitted with the devices.
Much of the test development for the CMOS MDAC characterization originatedwith the work done in characterizing the AD562 D/A converters. Many of thetest techniques are similar.
CMOS MDAC Test Parameters
At a JC-41 meeting in August 1979 the manufacturers presented a proposed
CMOS MDAC Specification. A list of parameters is shown in Table 5-3.
V-5
II
-- "- -.y.
Table 5-3. Test Parameters for Characterization.
ItenNo Symbol Test Parameter
I Icc Supply Current
2 Irer Reference Input Current
3 ILL Digital Input Leakage Current (logic 0)
4 [IIH Digital Input Leakage Current (logic 1)
5 ZS Zero Scale Current (IOUTI at logic 0 input)
6 dIZS/dT Zero Scale Current Drift
7 IZS' Zero Scale Current (IOUT2 at logic I input)
S -t-dVFS Gain Error (Full Scale) with +IOV Reference
9 -dVFS Gain Error (Full Scale) with -lOV Reference
10 dVFS/dT Gain Error Drift
11 +PSS Power Supply Sensitivity (+ IV change)
12 Ps' Power Supply Sensitivity (- IV change)
13 Linearity Error (End Point)
LE(BF) Linearity Error (Best Fit)
15 ,ICU Major Carry Error
1 il, Feedthrough Error
17 tSLU Output Current Settling Time (low to high)
113 tSHL Output Current Settling Time (high to low)O.
19 Co Output Capacitance
20 en Noise (broadband)
V-6
A
Test parameter items 1 through 15, except LE(BF) were setup to be measuredon GEOS' S-3270 Automatic Tester. All of these parameters are static.The static test circuit is shown in Figure 5-4. This circuit is verysimilar to the one used in testing the AD562 D/A Converters. There were,however, several essential differences which had to be made. Since theCMOS multiplying D/A's use a variable reference, it was decided that datahad to be taken for several reference voltage conditions. These conditionswere chosen at + 10 V, - 10 V, and + 1.25 V. A Fluke 5100B was used togenerate the different reference voltage levels. The 16 bit reference D/Aconverter was remotely located from the adapter through a ribbon cable sothat it could be used with other test adapters. In order to maintain voltageaccuracy at the adapter U6 error amplifier, the reference D/A output bufLferU4 has its output to feedback conection made at the error amplifier output.Also a ground driver U2-U3 is used to force the DUT and adapter groundto be at the same potential as the external reference D/A. The IOUTIcurrent output of the DUT is converted to a voltage by means of op amp U5.Since a millivolt of op amp offset voltage at 10 volts full scale causes a0.01% linearity error, it is important that this offset be trimmed out.In other words, lout.l and lout2 must go to virtual ground and outputground for proper operation. The offset adjustment of U5 is done withrelays KI and K4 energized. For any digital code word between zero scaleand full scale, the test circuit and software are mechanized so that nearlyequal and opposite voltages are generated by the reference D/A at the outputof U4 and the DUT at the output of U5. The differences between thesevoltages is amplified by U6 with a gain setting of 100 V/V and appears atadapter output pin 21.
Since the reference D/A is accurate to 16 bits, it is assumed perfect andany error is charged against the DUT. The inverted voltage output of theDUT D/A at U5 is determined indirectly as follows:
EDUT = Eo/G - EREF D/A
EDUT = -Eo/100 - l0(N)/2 exp B
where
G -100 V/V is the error amp gain
N - decimal equivalent of the input digital code word
B - number of bits
An inspection of the static test circuit shows that if the measured outputvoltage is positive, EDUT, although negative in polarity, has a greatermagnitude than EREF D/A. Consequently, the DUT output has a positivescale error with respect to the Reference D/A.The imaginary non-inverted value of the DUT D/A can then be written as
EDUT' = Eo/100 + IO(N)/2 exp B
V-7
M'.
41i
Cd 0 "0-
-
0 Cd k-4 0
-40. J4 J > w
Ii 41 -,-4
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4
4 V48 to 4jI'
If a 12 bit MDAC at full scale had a measured adapter output Eo of 0.1
volts,
EDUT' = 0.1/100 + 10(4095)/4096
EDUT' = 0.001 + 9.99756 V
EDUT' = 9.99856 V
The full-scale error of the device in % can be determined from
+dVFS = [(-Eo(FS)/G)/9.99756] x 100%
+dVFS = [(Eo(FS)/100)/9.997561 x 100%
+dVFS = 0.1 Eo(FS) % VFS
+dVFS = (0.1)(.1) = + 0.01' VFS
In millivolts the full-scale error is + dVFS = 0.011, of 10,000 mV I lV.The linearity error of the DUT output transfer characteristic from zcroscale to full scale is perhaps the most important parameter to be measured.For characterization, GEOS's procedure has been to measure the adapteroutput error for all digital input codes. Thus for a 12 bit converter _o9hdiscrete measurements are required. Automatic calculations are then doneto determine the deviation of each DUT output point from a straight linebetween the DUT's zero scale and full scale end points. Figure 5-5 showsthe transfer characteristic of a hypothetical poor device compared to an
ideal device.
AnalogOutput Actual CurveVoltage Ideal Curve
.. e rfe c :.,, ert nc 2 Lillo
n 000000000000 illiilili
Applied Digital Input Code
Figure 5-5. CMOS MDAC Transfer Characteristic.
4 v -9
A_.L_ am. -
C3LL
w <Ehi ) 72zz
U)C LL
. w )
tJ Ta
C>)
-- q
At ter the linearity error is determined for each point the 0.,La can beautomatically plotted as shown in Figure 5-6, or it can be summarized byIis t ing the individual bit errors and the worst case positive and worstcase negative bit errors and associated address codes.
By comparison the rem-.aining parameters to be meiasured with the statictest circuit are determined quite easily. Relays M! and K3 are energizedto measure the zcro scale currents at IOUTI and IOUT2 using U5 as acurrent to voltage converter. Input reference current, whichn is a functionof the IOV reference and the impedance of the R-2R ladder network ismeasured directly by energizing K2 with all bits high.
Feedthrou,-; Crror, settU n,, tino and output capacitancc were determinedWith, separate test f ixturoi. as~ sitown ;-iguIr s 5-7, 11-8 arid 5-9.
i+$15V
Fiue -. FedhruhEro Ts irut
07-li 1IM
VC(O
MC.4
D L) SVW
(ipracct it i2daa .a :lae oi twenty 10-hit devices froi-i twovelado ra anid f it Leon I -it Leie fromA throe vendors. Each device
yS(I- uo 11 t i~i V1II% ' ti td falo I TirametLers a t 25)oC, -5 5oC and 125oW.Tie i ,a1ta %,as recorded in severa-l di tterent forms as follows:
1.A dedicated !iaieet 10r each device showing all parameters
2. A conpairi on ot i ai, ; rane ters of ten devices at one temperatureon a1 Sliktt
5. ('rrHtr 4r ;Ot Al de'vices at each temperature.4. a: t d icc hjit lincoiri te error vs applied digita l pu t
I. lid i 11id i ,1.c2 dv c i.- stacrans of hl, tIineILa r ity e rro r vs f requen 1c y
iii 't1 letv ci Lt ian at djata cas- i'ublished by GEOS in a hand bookt' i I cdi
(1i1irict cri /.at jin 1)iti tort '!1 I-R-38,5l0/l127 CMOS Mutl t iplyingOA kiite r crs (\ ;2 DA C 10 2( Se r ies)
4d
Representative data sheets are shown in this report as follows:
Table 5-4 Typical Mfr. Code A Device Data Sheet
Table 5-5 Typical Mfr. Code B Device Data Sheet
Table 5-6 Typical Mfr. Code C Device Data Sheet
Table 5-7 Mfr. Code A Data (10 devices at 25oC)
Table 5-8 Mfr. Code B Data (10 devices at 25oC)
Table 5-9 Mfr. Code C Data (10 devices at 25oC)
Figure 5-10 Histogran of Gain Error (20 devices)
Figure 5-11 Linearity Error Distribution Histogram
Figure 5-12 Linearity Error vs Input Code Plot
Figure 5-13 Linearity Histogram at VREF = + 10 V for S/N 2
Figure 5-14 Linearity Histogram at VREF = - 10 V for S/N 2
Figure 5-15 Linearity Histogram at VREF = 1.25 V for S/N 2Figure 5-16 ?inearity i1ot, at Icc --I VFigure )-17 Linearity Plot at Vcc- V
v-13
5-5 Discussion of Data
The characterization data in all forms was reviewed to see how well
it compares to the original limits proposed by the JC-41 Committee.A discussion of this data on a parameter by parameter basis follows:
Power Supply Current (Icc)
The power supply current is much less than the indicated 100 uA limitswhen the digital inputs are at 0 V or Vcc respectively. GEOS' datafor these conditions is wrong because in making the measurements,full-scale was set at the 100 uA recommended limit while the actualcurrent was typically less than I L. As a consequence the machineaccuracy and offset error swamped out the reading to be measured, Thisdata was retaken on the bench and, except for one device, all valueswere less than 1 uAo When the digital input levels were set at the0,8 V to 2,4 V rTL compatible levels the supply current increased:-3tuiiicantlv, thus indicating more leakage in the OFF transistors ofCMOS sv.,itches. At -55'c several vendor code 13 devices just exceededthe 2 vi\ i:axi.mim limit. GEOS recommends that the -550C limit beraisesl to 2>5 ,mo
Rc---nck. Current RIEI + f-L-2
All of the data was between 0.8 and 1,3 mA compared to the 0.5 to 2 P.-Alirijt:;. This current reflects the value of wor -, ,2 -.
'L. itaL [iput Leakage Current (IlL' IIi)
Ihe individual device sheets were set up to indicate PASS or FAIL tosumiarL' u the results if any of the ten or twelve digital inputs hada failure No failures were recorded and the histograms indicated aspread betw. en 0 and 43 nanoamperes.
.,crO Scale Current (I/S, IZS')
Typical device data was much less than the recommended limits of/- 2'-tA nA Except for one maverick device which measured -149.5 nA,
at 1.23'1C, all other data was between -11 A and 0. GEOS recommendsthat the limits be reduced to - lO nA. It is believed that the singleIt .'tvpical value could be a measurement error because it does not agreevwith submitted vendor data.
V-i
Zero Scale Current Drift (dIZS/d)
A review of the data indicates that limits of +/- 400 pA/C would bereasonable. There was no JC-41 recommendation on this parameter.
Full Scale Error _(+ dVFS.- dVFS)
The distribution of data between - 45.6 mV and 17.6 nV was well withinthe - 1 100 mV recommended limits.
Full Scale Error Drift (dVFS/d.)
All of the data is within the :1 10 ppm VFS/V limits.
Power Supply Sensitivity ( PSS, - PSS)
The distribution of data is very much tighter than the recommendedlimits of 100 ppm VFS/V. GEOS recommends that these limits bereduced to 1 50 ppm VFS/V
Linearity Error (LE)
Linearitv error is one parameter which cannot be negotiated. Thelinearity has to be within 1/2 LSB to meet the stated accuracyrequirement. Most of the data is well within the ± 1/2 LSB limits.Figure 5-12 shows how the linearity for a typical device varies withits input coJe. Figures 5-13, 5-14 and 5-15 show the linearityhistograms ol onu device (S/N 2) with VREF = + 10 V, - 10 V and+ 1.25 V respectively. Because of the apparent independence ofreference voltage level the specification requirement to test at all
three levels may be reduced to testing at + 10 V only.
Feedthrough Error (PTE)
All of the data for devices from vendors A and B were under 8.5 mVpp.These devices are within their 10 mVpp limit. Vendor Code C deviceshad ieedthrough errors as high as 19 nVpp. These devices satisfytheir 25 mVpp limit.
Output Current Settling Time (tSLH, tSHL)
All devices had data values within the recommended 1 usec maximumlimit,
jutp Ut 2a ,'.citaukce (.:o0)
- All- 'cvic * G&ar .1!ti;i:>i." t ,, -+. m7 nK te'., r'tco.-l;l:yhea limits.
4
:'h,, ;iash ohce,, MIL-M- 36,51/127, was cevloped a a joint effort of GEOSand thc. jc-41 .J D ttL.c Jubsonmittee. The majority of the test parameterswere 2'L;ablI,;hed eazly in the ;lash sheet development in a JC-41 Subcom-mittee meeting. One major change has been the deletion of +5V as a rec-commended operating .upply voltage. All-codes data taken on a 7520 devicefrom vtndor A showed exceo;sive linearity errors and differential linearityerrors, !pecially at +12')OC. A comparison of one such sample of datataken at ,wo supply voltages is shown in the Appendix, Table 5-16 andTable 5-17- G20.S' recommendation to limit operating voltage to +15 voltswas adopted by th- JC-41 committee.
A major goal of the characterization was to develop an abbreviated testfor linearity. Initial all-codes testing of the 7520 linearity errorshowed that the abbreviated test used for the 562 12-bit D/A Converterspecified in MIL-M-38510/121 was invalid for the 7520, since it did notCind the wors:t case codes having maximum Linearity error. The followingapproach to an abbreviated test was developed by GE and is proposed forthe slash sheet;
1. Measure all combinations of the four MSB's with the lower orderbits OFF.
2. Measure each of the lower order bits with the four MSB's OFF.
3. Determine the code word with the most positive predictable errorbased on the above tests, and measure that error. Repeat thismeasurement but with all lower order bits complemented one at atime.
4- Repeat the third group of tests above, but with the most negativepredictable error codes.
This abbreviated test is done in Group A at three temperatures. An all-codes test at three temperatures is also required on a sample basis in theslash sheet.
This device is used as a multiplying DAC in many applications. Therefore,it is also necessary to test its ability to convert digital inputs with anegative reference voltage applied. GE has characterized the 7520 deviceat three refence voltage levels: +1OV, - OV, and 4 1.25 V. Linearityerrors are comparable at all three reference levels, although in many casesthe- error is slightly greater at minus ten volts than at plus ten volts.In order to guarantee the performance for both polarities, the abbreviatedtest is also required to be run at both plus and minus 13 volt levels,and at , 1.25 volts, "hi.; requirement will be further negotiated with theJc-4l committee.
Table I, Electrical Performance Characteristics, MIL-M-38510/127, isincluded in the following for reference.
! v-16
5.7 Conclusions and Recommendations
The 7520 10-bit DAC(and the 7523 8-bit DACuwhich is manufactured using the7520 chip) has been characterized and is judged suitable for use in mil-itary systems when procured via MIL-M 38510/127. Device manufacturerswill review the characterization data and proposed slash sheet beforethe issuance of the final slash sheet.
The 7541 12-bit DACs have not yet been fully characterized at the t imeof writing of this report. That effort will be completed andintegrated into the final released specification.
V1
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MIL-M-38510/127REV - ORIG.
DATE- 1/26/81
Table I. Electrical performance characteristics. I/
Conditions:Characteristic Symbol Vcc = + 15V, Vref - + 1OV, Device Limits Units
paragraph 3.4 and Figure 7. Type Min Max
Supply current Icc All digital inputs at OV All - 100 uA
from Vcc All digital inputs at Vcc All - 100 uAAll digital inputs at 0.8V All - 2 mAAll digital inputs at 2.4V All - 2 mA
Reference input Iref All digital inputs Vref= IOV All 0.5 2 mA
current at VcclOUTI and IOUT2 Vref= -1OV All -2 -0.5 mAgrounded
Digital input IlL All digital inputs at OV 01-05 -1.0 1.0 uAleakage current All digital inputs at 0.8V 06-09 -200 1.0 uA
IIH All digital inputs at Vcc 01-05 -1.0 1.0 uA
All digital inputs at 2.4V 06-09 -1.0 100 uA
Zero scale IZS All digital inputs at 0.8V All -200 200 nAcurrent IZS' All digital inputs at 2.4V All -200 200 nA
Zero scale dIZS/dT All digital inputs at 0.8V All (later) pA/°C
current drift
Full scale +dVFS All digital inputs at Vcc, All -1 1 %VFSerror IOUT2 at OV. Vref = +IOV
-dVFS As above with Vref = -10V All -1 1 %VFS
Full scale dVFS/dT Change in +dVFS from -250 C to All -10 10 ppm
error drift 1250C and from 250C to -550 C VFS/°C
Power supply +PSS, All digital inputs at Vcc; All -100 100 ppm
sensitivity at -PSS IOUT2 at OV VFS/Vfull scale from VCC - + 14V to +16VVcc. Measured at IOUTI and Rf
4
- - _ ':7 -:: - : ,TT -T.. .. ... .
MIL-M-38510/127REV -ORIG.DATE - 1/26/81
Table I. Electrical performance characteristics. I/ (continued)
Conditions:Characteristic Symbol Vcc = + 15V, Vref = + 1OV, Device Limits Units
paragraph 3.4 and Figure 7. Type Min Max
01 -0.2 0.2 %VFSLinearity error LE Measure the following:(end point) 1. All combinations of the
2/ most significant four bits 02 -.05 .05 %VFSwith the lower order bits
turned off.2. The individual lower bits 03 -.05 .05 %VFS
with the most significantfour bits turned off.
3. The code word with the most 04 -.012 .012 %VFSpositive combination ofbits in groups I & 2 above.--------------------
4. The code words derived from 05 -.012 .012 %VFSgroup 3 with all lowerorder bits complemented ---------
one at a time. 06 -.05 .05 %VFS5. The code word with the most
negative combination of
bits in groups I and 2. 07 -.05 .05 %VFS6. The code words derived from
group 5 with all lower
order bits complemented one 08 -.012 .012 %VFSat a time.
7. Groups I through 6 withVref = -IOV. 09 -.012 .012 %VFS
8. Group I through 6 withVref = 1.25V.
9. Group A sample - allcode combinations of thedigital input bits.
Bit linearity LE (BF) If any end point linearity 05, -.012 .012 %VFSerrors tests fail, certain devices 09(best fit) may be tested to a best fit
criteria. The vendor shallspecify the criteria (i.e. 3/4or 7/8 scale adjustment) andrepeat all of the linearitytests.
4
- .. 4, , " - : , . " :
Table I. Electrical performance characteristics. 1/ (continued)
Conditions:Characteristic Symbol Vcc - + 15V, Vref - + IOV, Device Limits Units
paragraph 3.4 and Figure 7. Type Min Max
01 -0.4 0.4 %VFSMajor carry MCE The difference betweenerrors adjacent codes at all 02,03 -0.1 0.1 %VFS
(differential major transitions. 06,07linearity) (i.e. from 01111111
to 10000000) 04,05 -.025 .025 %VFS
08,09
Feedthrough FTE Vref-20Vpp, 100kHz and all 01-05 - 10 mVpperror digital inputs low. TA-250 C,
Group D only. See Figure 8. 06-09 - 25 mVpp
Output current tSLH All inputs switched simul- All - 1 usecsettling time taneously, low to high and
(to 1/2 LSB) tSHL high to low . TA-25 0 C. All - 1 usecSee Figure 9. 3/
Output Co All digital inputs at Vcc
capacitance See Figure 10. Co at IOUTI All - 200 pFTA = 25°C Co at rOUT2 All - 75 pF
Output Co All digital inputs at OVcapacitance See Figure 10. Co at IOUTI All - 75 pF
TA - 25°C Co at IOUT2 All - 200 pF
Noise en The single source of noise All 6.5 40 Kohmis the resistor network,which characteristically
has Johnson or thermalnoise. 4/
Notes:1/ See definitions as described in 6.5.2/ Linearity is specified to be within +/- 1/2 LSB. Thus
an 8 bit device with a 1OV reference must have end point
linearity to within 1/2 of (I00%VFS/2exp8) - 0.195 %VFS or 0.2 %VFS.3/ For each device type, output current settling time is the duration
from the digital input transition until the output for a 1OV analog
ir,put rransl*iun -s within 1/2 LSR of final value4/ Tre R-2R resistor network has Johnson or thermal noise. Noi-.e at
the DUT output is related tt ttie noise resistace value according toen - SQR(4KTRn(BW))
* where K = Boltzmann's constant - 1.38*E-23 Joules/°KT - Absolute temperature in OK
4 Rn - Rf(1+Rf/Ro) changes with Ro and the digital code word4BW - Bandwidth in Hertz.
S,2,
MISSIONOf
Rome Air Development CenterRAVC Ptn6 and execute6 'Le~weah. devetopment, te~t and,6etected acqUiiLtiOn p4og4=a6 in 6ctppoitt o6 Conwmnd, ContAotCormuncation6 and In-tettigence IC31) adtivitieA. TechnZ catand engneeing Auppot'zt wLthin a'~eA. oj technicat compe.tenice"6 p'tovided to EsI) P4og4am o66ice,6 (P0s) and ott ct ESVetement6. The p'tZnciZpat technica2 mZa6&Zon a'Lett a~ecOmmuncatonA, etectAomagnetic guidance and contitot, 6ut-veiilae oj qtound and aeAo6par-e obiect&, intettUgence datacottection and handtzng, indo'tmation sy,6tem technotogy,ionoapheic ptopagation, .6011. atate 6cienceA, micAouxwephy&Zc. and efecttoniz 4e11.abitit, mait.inabititg andcompatibiLtt.
T :4 1