eel3701 menu look into my - mil.ufl.edu plds, cplds.pdf · 9-jul-18—5:52 pm university of...

9-Jul-18—5:52 PM

1University of Florida, EEL 3701 – File 21

© Drs. Eric M. Schwartz

PLDs, CPLDs

EEL3701


© Dr. Eric M. Schwartz

Menu• Programmable Logic Devices (PLDs)

>Programmable Array Logic (PALs)>Programmable Logic Arrays (PLAs)

• PAL/GAL 16V8• CPLD: Altera’s MAX 3064 & MAX V

Look into my ...

See examples on web: Lam Ch 6 PLD figs, PAL/GAL info,

m3000a.pdf, max5_handbook.pdf

• Read Roth: Sections 9.6-9.8(Sections 16.4-16.6)

• (Optional) Read Lam: Sections 6.4

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Programmable Logic Devices and Programmable Logic Arrays (PLA’s)

• In conventional MSOP design, a function of 10 inputs and 8 outputs can be expressed as:

> Zi = f (x0, x1, ... , x9), i = 0, 1, ... , 7

See Lam Section 6.4

X0

X1

X2

X3

X4

X5

X6

X7

X8

X9

Z0

Z1

Z2

Z3

Z4

Z5

Z6

Z7

Xi’s Zi

...

...

...

......

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PLDs, CPLDs

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PLD Shorthand NotationLAM Fig 6.9

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LAM Fig 6.10

PLAExample

Simplified Schematics

PLA

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PLDs, CPLDs

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Simplified Schematics

LAM Fig 6.11

PLA

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Programmable Logic Devices and Programmable Logic Arrays (PLA’s)

Q: Any problems with MSOPs? A:_______________________

Q: Any advantages? A:_______________________

PLA’s are not a new theory, but a systematic technique for realizing combinational logic in 1 package (IC). This allows us to take advantage of LSI (Large-Scaled Integration).

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PLDs, CPLDs

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More PLA’sZ0 = A*/C + B Z1 = A*/B + /A*B

LAM Fig 6.11

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NInputs

PLA Block Diagram

Inv / Non-Inv Buffers

2*NAND Array

(K AND terms)

K

OR Array MOutputs

• PLAs OR gates share AND gates, i.e., have access to all the AND gates

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PLDs, CPLDs

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NInputs

PAL Block Diagram

Inv / Non-Inv Buffers

2*N

AND Array(KM-1

terms)

KM-1

OR

OutputM-1

AND Array(KM-2

terms)

KM-2

OR

OutputM-2

AND Array(K0 terms)

K0

OR

Output0

• PALs do NOT share AND gates, i.e., each PAL OR gate has its own AND gates

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PLA Options• PLA’s provide you with three options:

> Manufacturer programmable (like masked ROM)> Field programmable (by blowing fuse links) PLAs (FPLA)> Electrically erasable (reusable or recyclable) PLAs (EEPLA)

• Advantages> Small board area, less cost/wires/solder, less stocking costs,

reliability, flexibility, secrecy• Disadvantages

> For FPLA’s, just 1 chance, initial cost (programmer required)

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PLDs, CPLDs

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82S100 FPLA• 16 inputs (I0 – I15)• 8 outputs (F0 – F7)• Tri-state enable,

CE(L) controls all outputs

Lam Fig 6.14

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82S100 FPLA• 16 inputs (I0 – I15)• 8 outputs (F0 – F7)• Tri-state enable,

CE(L) controls all outputs

Tri-state enable

All ANDs are available to all ORs

Both activation-levs of all inputs are available

Lam Fig 6.14

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PLDs, CPLDs

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Programmable output activation level• If CE = 1, then can select the desired

activation-level of the output

Si(L)

Si(H)

Xi = Vcc

Xi = GND XOR[0, Si ] = Si

XOR[1, Si ] = /Si

• Not driven inputs are high (Xi )Lam Fig 6.15

X 0 = X and X 1 = /X

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Tri-state outputs• If CE = 0, then output is tri-stated• If CE = 1, then output is not tri-stated

Si(L)

Si(H)

Xi = Vcc

Xi = GND XOR[0, Si ] = Si

XOR[1, Si ] = /Si

Lam Fig 6.15

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PLDs, CPLDs

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PAL14H4• PALs do NOT

share, i.e., they have their own ANDs

• 14 inputs• 4 ANDs per OR• 4 outputs (ORs)

Y = ABC + A /B +/A /B /C

Z = A /B + /A B C +B /C

Lam Fig 6.16

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PAL Abbreviations

The X in the AND all inputs connected, i.e., Z = A*/A*B*/B = 0AND gate is not used

Nothing in AND or connected to AND no inputs connected, i.e., Z = 1So what is the output of this OR gate? ___

Lam Fig 6.17

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PLDs, CPLDs

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Programmable Array Logic (PAL)

• PAL is a special case of PLAs• PALs have have a fixed OR array (instead of the

programmable OR Array for the PLA), i.e., PALs do NOT share (each OR needs its own ANDs)

• PALs are cheaper than PLA, but less flexible

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PAL 16V8

16V8B_PAL.pdf

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PLDs, CPLDs

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PAL 16V8

16V8B_PAL.pdf

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16V8 Combinational Mode Option

16V8B_PAL.pdf

gal22v10.pdf

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PLDs, CPLDs

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16V8 Registered Mode Option

16V8B_PAL.pdf gal22v10.pdf

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MAX 3064 CPLDs

m3000a.pdf

• MAX 3064 (m3000a.pdf)> Device Features: Table 1 (page 1)> Device Block Diagram: Figure 1 (page 5)> Device Macrocell: Figure 2 (page 6)> Shareable Expanders: Figure 3 (page 8)> I/O Control Block: Figure 6 (page 11)

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PLDs, CPLDs

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MAX V CPLDs

max5_handbook.pdf

• Ours is a 5M570ZT100C5N (Figure 1-1)> 5M ==> Max V > 570Z ==> 570 Logic Elements > T ==> TQFP (Thin quad flat pack) > 100 ==> Pin count > C ==> Temp range 0 to 85 degrees C > 5 ==> a speed classification (not as fast a 4) > N ==> Lead free

• MAX 5 Handbook> Device Features: Table 1 (page 2)> Device Block Diagram: Figure 2-1 (page 2-2)> Device Macrocell: Figure 2 (page 6)> Shareable Expanders: Figure 3 (page 8)> I/O Control Block: Figure 6 (page 11)

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MAX V CPLDs

max5_handbook.pdf• MAX 5 Handbook

>Device Features: Table 1-1– Each of 570 Logic Array Blocks (LABs) have the

following10 Logic Elements (LEs), each with an carry chainsLAB control signalsA local interconnectA look-up table (LUT)…

– Flash available (8k bits = 1K bytes = 512 x 16 bits)>Device Block Diagram: Figure 2-1>LAB Structure: Figure 2-3>Logic Element (LE): Figure 2-6>LE’s can be used as RAM

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PLDs, CPLDs

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The End!

eel3701 menu look into my - mil.ufl.edu plds, cplds.pdf · 9-jul-18—5:52 pm university of...

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