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EELE 367 Logic Design Module 6 Computer Systems Agenda 1.Memory 2.Von Neumann Architecture 3.Sequence Controllers 4.Processing Units & Register Modeling

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Module 6: Computer Systems 2 Memory Memory Types Notes on definitions: 1) The word "RAM" is now used interchangeably with R/W memory. Formally, most types ROM are also Random Access 2) ROM memory typically refers to storage that can't be written during program execution. It can hold program and data information, but under normal operation a CPU doesn't use it for variable storage. As Flash EEprom gets faster and more reliable, Flash may become used as RAM

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Module 6: Computer Systems 3 Memory - SRAM Static Random Access Memory (SRAM) - SRAM is volatile memory (i.e., if the power is removed, the information is lost) - SRAM uses an inverter loop to store the digital information - two NMOS transistors acting as switches are used to Read and Write the stored data - we call the circuitry to store 1-bit a "cell"

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Module 6: Computer Systems 4 Memory - SRAM SRAM Addressing - we configure the cells into an array - we address each cell using: Row Address - a row decoder produces a "Word Line" - this gives a "Row Select" (RS) signal Column Address - a column decoder produces a "Bit Line" - this gives a "Column Select" (CS)

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Module 6: Computer Systems 5 Memory - SRAM SRAM Addressing - The Word Lines are used to address a row of cells - The Bit Lines are used to address a column in addition to reading and writing - There are two bit lines per cell, BL and BL' - This allows a difference amplifier to be used to distinguish between a 1 and a 0

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Module 6: Computer Systems 6 Memory - SRAM SRAM Reading - The capacitance of the Bit Lines can be very large due to multiple cells being attached - This creates a problem during a READ because the small cell will need to drive this large capacitance - To reduce the amount of charge that the cell has to drive during a READ, pull-up transistors are used to "pre-charge" the lines to V DD

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Module 6: Computer Systems 7 Memory - SRAM SRAM Reading - In order to design a usable SRAM cell, we must meet the condition that: "Reading the value does NOT destroy the contents of the cell" - Let's look at what happens during a read to see how to meet this condition Reading a '0' - Initially V1=0v, V2=V DD - M3 and M4 are turned ON - this allows the Cell to drive BL and BL' - The voltage V2 will be the same as the pre-charged BL' line, so no current will flow through M4

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Module 6: Computer Systems 8 Memory - SRAM SRAM Writing - when writing to the SRAM cell, we inject full swing digital signals onto BL and BL'. - when we assert the Word Lines, M3 and M4 will open and attempt to change the state of the cell.

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Module 6: Computer Systems 9 Memory - DRAM Dynamic Random Access Memory (DRAM) - A volatile memory storage device even smaller than SRAM - DRAM uses a capacitor to store the value of the digital information (instead of an inverter loop) - one NMOS transistor is used to address the storage element - the one-transistor configuration is known as a 1T DRAM

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Module 6: Computer Systems 10 Memory - DRAM DRAM Operation - When the cell is addressed, the charge on the storage capacitor (C S ) is dumped onto the bit line (BL) - To reduce the amount of charge the cell has to provide, the bit line capacitance (C BL ) is pre-charged to V DD /2 - When the NMOS switch closes, the two capacitances will share their charge and settle to a readable level by amplifiers

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Module 6: Computer Systems 11 Memory ROM Nonvolatile Memory - SRAM and DRAM and attractive due to their speed - however, they are volatile which means when the power is removed, the data is lost - for a microcomputer, we need a nonvolatile storage device so that upon power-up, the computer knows what to do. - currently, the most popular semiconductor ROM is Flash (or EEprom) - before looking at the details of a Flash transistor, lets first look at the different types of ROM arrays and addressing modes

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Module 6: Computer Systems 12 Memory ROM ROM Arrays - There are two basic types of ROM arrays 1) NOR-based ROM 2) NAND-based ROM NOR-based ROM - All Column Lines are pulled-up using a PMOS transistor (or resistor) - The Row Lines are connected to the gates of NMOS transistors at the intersection of Row and Column Lines - The presence or absence of the NMOS transistors dictates whether a 1 or a 0 is stored - If the NMOS transistor is present, it will pull down the Column Line when its gate is driven high by the Row Line - if the NMOS transistor is absent, the Column Line will not be pulled down, so it will remain pulled up by the PMOSs

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Module 6: Computer Systems 13 Memory ROM NOR-based ROM - In order to Read from the array, the Row line is asserted and the desired Column line is observed - a NOR-based ROM is similar to a Hex Keypad

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Module 6: Computer Systems 14 Memory ROM NAND-based ROM - NAND-based ROM is a different array architecture - it uses a depletion-load NMOS as the pull-up transistor - the Column NMOSs are connected in series with the column lines (i.e. a NAND configuration) - If an NMOS exists in the Column line and the Row line is asserted, the NMOS will pull the Column Line down and represent a stored 0 - If an NMOS is absent on the Column line and the Row line is asserted, the Column Line will remain pulled high by the depletion NMOS and represent a stored 1 - since all of the NMOSs are in series, in order to Read from a Row, all other Rows much be turned ON - this means in order to distinguish the Row we are asserting, we write a 0 to it

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Module 6: Computer Systems 15 Memory ROM NAND-based ROM - In this configuration, if an NMOS is present, it will represent a stored 1 since in order to address its location, the Row line is driven to a 0 and the NMOS not turned on. This leaves the Column line pulled HIGH - if an NMOS is absent, it will represent a stored 0 since all of the other Row NMOSs are turned on and will pull the Column Line LOW - this gives the opposite behavior as in a NOR-based ROM NORNAND NMOS present 0 1 NMOS absent 1 0 - it also gives a complementary addressing scheme NOR NAND Address Row Line by driving: 1 0 All other Row Lines driven to: 0 1

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Module 6: Computer Systems 16 Memory Flash Flash Memory Cells - a novel breakthrough in ROM memory was the invention of the floating gate transistor in 1984 by Toshiba - this transistor is constructed such that the threshold of the device can be changed in-system - if the threshold can be raised and lowered, this allows the transistor within the ROM array to either be: present i.e., Normal Row addressing will turn the device ON (V Row-HIGH >V T,n ) or absent i.e., Normal Row addressing is not high enough to turn the device on (V Row-HIGH

Module 6: Computer Systems 21 Memory Flash Flash Memory Cells - If we position the threshold voltage at a normal CMOS level (~1v), then the transistor can be turned on using a standard signal level at the gate (i.e., V gate =5v) - If we position the threshold voltage at a raised level (>V DD ), then a standard signal level at the gate will NOT be able to turn on the transistor

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Module 6: Computer Systems 22 Memory Flash NAND/NOR Flash - we can use Flash Cells in a NOR or NAND Array to implement a EEprom - the Flash Cell requires one additional line on the Source of each transistor in order to accomplish the programming and erasing.

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Module 6: Computer Systems 23 Memory Flash NAND vs. NOR Flash - Flash implies that blocks of memory are erased at a time - this is a specific type of EEprom and is cheaper to fabrication due to less programming circuitry NOR Flash - slower erase and write times - allows access to any address which makes it truly Random Access - this is suitable for uP ROM applications such as BIOS or Firmware in which the uP needs to access memory locations individually NAND Flash - faster erase and write times - smaller chip area which creates higher density and lower cost - more erase cycles than NOR-Flash - not Random Access, data must be read/written in large blocks, not suitable for uP ROM - it is well suited for thumb drives, iPods, and secondary storage in microcomputers (i.e., hard drives, CDROMS)

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Module 6: Computer Systems 24 Memory in VHDL Memory is described in VHDL using the keyword array The array keyword defines a 2D vector of information. type memory_type is array (0 to 255) of std_logic_vector(7 downto 0); This defines a data type which is a 2D array that is m x n (256 x 8) This data type can then be used to define either a signal (for RAM) or constant (for ROM) Arrays in VHDL require integers as their indeces. This means a type conversion must be used when access the 2D array since the address lines will come in as STD_LOGIC_VECTOR (i.e., conv_integer(address))

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Module 6: Computer Systems 25 Memory in VHDL RAM in VHDL entity ram_256x8_sync is port (clock : in std_logic; data_in : in std_logic_vector(7 downto 0); write : in std_logic; address : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0)); end entity; architecture rtl of ram_256x8_sync is type ram_type is array (0 to 255) of std_logic_vector(7 downto 0); signal RAM : ram_type; begin memory : process (clock) begin if (clock'event and clock='1') then if (write = '1')) then RAM(conv_integer(address)) xCD", 3 => x"80", : begin memory : process (clock) begin if (clock'event and clock='1') then data_out x"AA", 2 => xCD", 3 => x"80", : begin memory : process (clock) begin if (clock'event and clock='1') then data_out x"AA", 2 => xCD", 3 => x"80", : begin data_out x"AA", 2 => xCD", 3 => x"80", : begin data_out

Module 6: Computer Systems 29 Memory Mapping Address Decoding - Address decoding can be accomplished within the model for the RAM/ROM/IO memory : process (clock) begin if (clock'event and clock='1') then if (address >= 0 and address