Effective Linear Programming-Based Placement TechniquesSherief RedaSherief Reda

UC San DiegoUC San Diego

Amit ChowdharyAmit Chowdhary

Intel CorporationIntel Corporation

Outline MotivationMotivation Modeling of cell spreadingModeling of cell spreading Linear programming (LP)-based placerLinear programming (LP)-based placer Applications of LP-based placerApplications of LP-based placer Experimental resultsExperimental results ConclusionsConclusions

Motivation Linear programming has been shown to be Linear programming has been shown to be

effective in modeling timing objective during effective in modeling timing objective during placementplacement– Static timing can be modeled as linear constraints Static timing can be modeled as linear constraints

using the notion of differential timing [DAC 2005]using the notion of differential timing [DAC 2005]

Linear programming can effectively model Linear programming can effectively model wirelength as half-perimeter wirelength (HPWL)wirelength as half-perimeter wirelength (HPWL)

Cell spreading not modeled in linear Cell spreading not modeled in linear programming yetprogramming yet– LP has been restricted to incremental placementLP has been restricted to incremental placement

Main Contribution In this paper, we model cell spreading using In this paper, we model cell spreading using

linear constraintslinear constraints

Designed a global placer based on linear Designed a global placer based on linear programmingprogramming– Efficient modeling of timing and wirelengthEfficient modeling of timing and wirelength– Uses relative placement constraints to spread Uses relative placement constraints to spread

cells graduallycells gradually

Our LP-based placement approach can be Our LP-based placement approach can be used asused as– Global placerGlobal placer– Whitespace allocator (WSA)Whitespace allocator (WSA)

LP-based Placement Approach Place cells using an ideal or exact HPWL Place cells using an ideal or exact HPWL

model of wirelengthmodel of wirelength Use this initial placement to establish a Use this initial placement to establish a

relative orderingrelative ordering of cells of cells Transform Transform relative orderrelative order of cells into of cells into linear linear

constraintsconstraints – Solve the corresponding LP problem to spread Solve the corresponding LP problem to spread

cells while maintaining relative ordercells while maintaining relative order Iterate till cells are spread outIterate till cells are spread out

LP-based Placement Approach

Placement after iteration 1

Placement after iteration 3

Legalized placement

Placement after iteration 2

Placement after iteration 4

Initial WL-optimal placement

Modeling of wirelength leftxleftx, , rightxrightx, , lowerylowery and and

upperyuppery variables defined for variables defined for every netevery net

HPWL model of wirelength HPWL model of wirelength usedused

For every cell at location For every cell at location ((xx,,yy)) connected to netconnected to net

Length of this net isLength of this net is

lowery

uppery

Net

leftx rightx

yupperyyloweryxrightxxleftx

)()( loweryupperyleftxrightxl

Lower bound on wirelength Length of a net has a lower bound based on the Length of a net has a lower bound based on the

area of cells connected to itarea of cells connected to it

Lower bound on each net spreads out cells Lower bound on each net spreads out cells – Helps in defining relative order of cellsHelps in defining relative order of cells

Overall wirelength objective isOverall wirelength objective is

u uAreal

nets lHPWL

Modeling of timing Various aspects of static timing analysis can be Various aspects of static timing analysis can be

formulated as linear constraints of cell formulated as linear constraints of cell placements [DAC2005]placements [DAC2005]– Delay and transition time for cellsDelay and transition time for cells– Delay and transition time for netsDelay and transition time for nets– Propagated arrival timesPropagated arrival times– Slack at cell pinsSlack at cell pins– Timing metrics Timing metrics

worst negative slack WNSworst negative slack WNS total negative slack TNStotal negative slack TNS

Defining relative order For each cell v, define four sets corresponding to

the cells to the left, right, upper, and below v– Quadratic time and space complexity

Reduce space complexity to linear using transitivity– Still quadratic time

We use fast heuristic methods that capture a good amount of the relative order relationships– Q-adjacency graph– Delaunay triangulation

Q-adjacency Graph• Simple Idea: Establish an adjacency between each

cell and its closest cell in each of the four quadrant

Complexity is O(M.logM + k.M), where k is a constant that depends on the input placement

Delaunay Triangulation• Capture adjacency using Delaunay triangulation

Voronoi diagram Delaunay triangulation (dual of the Voronoi diagram)

• Voronoi diagram • Partitioning of a plane with n points into convex

polygons such that each polygon contains exactly one generating point and every point in a given polygon is closer to its generating point than to any other point

Example of Delaunay and Q-Adjacency

• We use relative order from Q-Adjacency as well as Delaunay triangulation

DELQ-ADJ + DELQ-ADJ

LP Modeling of Relative Order

u

vu

v

u

v

2. if u and v do not overlap

make sure a non-overlap does not turn into an overlap

1. if u and v overlap in the current placement then next separation = current separation +

minimum additional separation to remove the overlap and make sure u and v relative positions stay the same make sure the amount of overlap reduces

For each adjacency {u, v}:

LP-Based Placement TechniquesOur LP-based placement approach can be used in

several ways

1. Wirelength-driven global placement

2. Whitespace allocation

3. Timing- and wirelength-driven global placement

1. Wirelength-driven Global Placement

Relative Placement

MidX - Spreading

Legalization

Detailed Placement

Final Placement

Unplaced circuit

Benchmark statistics

CircuitCircuit #cells#cells #DH #DH cellscells

#nets#nets #IO #IO PadsPads

WS%WS%

WFUB01WFUB01 2093520935 270270 2190121901 97089708 53%53%WFUB02WFUB02 1181911819 356356 1278012780 78517851 55%55%WFUB03WFUB03 76737673 587587 85428542 75227522 36%36%WFUB04WFUB04 13081308 146146 19351935 22142214 52%52%WFUB05WFUB05 1605616056 363363 2000220002 84048404 49%49%WFUB06WFUB06 1859218592 539539 2273722737 1507315073 41%41%WFUB07WFUB07 1478014780 554554 1596015960 92719271 27%27%WFUB08WFUB08 1821718217 507507 1952519525 92199219 43%43%WFUB09WFUB09 1649116491 292292 1781717817 1647316473 54%54%

• Circuits chosen from a recent microprocessor

Comparison with Other PlacersCompared results with other placers

• Capo 9.3 (UMich)• Better of FengShui 2.6 and 5.1 (SUNY)• APlace 2.0 (UCSD)• Better of mPL 4.1 and 5.0 (UCLA)

All placements were measured using the same HPWL calculator

Results of comparison

CircuitCircuit Our Our PlacerPlacer

CapoCapo9.39.3

FengShFengShuiui

5.15.1

APlaceAPlace2.02.0

mPLmPL5.05.0

WFUB01WFUB01 888888 927927 failfail 882882 10531053WFUB02WFUB02 574574 562562 883883 539539 651651WFUB03WFUB03 326326 325325 456456 failfail 349349WFUB04WFUB04 9494 9393 131131 failfail 128128WFUB05WFUB05 106106 109109 136136 107107 110110WFUB06WFUB06 114114 123123 117117 118118 119119WFUB07WFUB07 693693 673673 765765 652652 699699WFUB08WFUB08 804804 821821 891891 802802 872872WFUB09WFUB09 111111 106106 190190 110110 117117

Average%Average% 0.00%0.00% 0.71%0.71% 32.05%32.05% -1.34%-1.34% 10.90%10.90%

Comparison of Placers

-505

101520253035

Average HPWL % Diff

MidXCapo9.3FengShui5.1APlace2.0mPL5.0

Placements of different placers

FengShui5.1

HPWL = 891

HPWL = 881

mPL5.0

Capo9.3

HPWL = 823

HPWL = 804

Our Placement

APlace2.0

HPWL = 802

2. Whitespace AllocationIn an existing legal placement, we redistribute white space to optimize wirelength

Global Placement + Legalization

MidX – Whitespace Allocation

Legalization

Detailed Placement

Final Placement

Unplaced circuit

Whitespace Allocation: Example

Input global placement: HPWL = 9.43

After MidX and legalization: HPWL = 8.81

After MidX: HPWL = 8.76

3. Timing-driven global placement

Timing-optimal Relaxed Placement

MidXT - Spreading

Legalization

Detailed Placement

Final Placement

Unplaced circuit

Timing-driven global placement• Start with a timing-optimal relaxed placement obtained using our differential timing-based placer [DAC 2005]

• Identify timing critical cells from a static timer

• Spread cells using MidXT with a combined objective of• Minimize total wirelength of all nets• Minimize total displacement of all timing-critical cells

• We are working on integrating the static timing constraints in MidXT placer

Timing-driven placement: Example

Input Placement:TNS = -13.99

Relaxed placement: TNS = -8.82

After MidXT:TNS = -9.40

After legalization:

TNS = -10.34

Conclusions Extended LP-based placement approach Extended LP-based placement approach

to model cell spreadingto model cell spreading– Relative order amongst adjacent cells Relative order amongst adjacent cells

are transformed into linear constraints are transformed into linear constraints

Presented a powerful LP-based global Presented a powerful LP-based global placerplacer– Gradually spreads cells while Gradually spreads cells while

maintaining relative ordermaintaining relative order– Benchmarked against academic placers Benchmarked against academic placers – Models timing and wirelength very Models timing and wirelength very

accuratelyaccurately