EFFECTS OF N-TYPE SUBSTRATE ON EPILAYER QUALITYFOR TWIN TUB CMOS TECHNOLOGY

SOOKAP HAHNSiltec Corporation423 National AvenueMountain View, CA 94043

JOHN O. BORLANDApplied Materials, Inc.3050 Bowers AvenueSanta Clara, CA 95054

c..c. DANIEL WONGIntegrated Devices Technology3236 Scott BoulevardSanta Clara, CA 95054

Improvements in silicon epilayer quality have been achieved through the application of a modified three-step pre-epitaxial intrin-sic gettering technique to n-type substrates. A systematic comparison was made between epilayers grown on lightly phosphorus-doped, heavily phosphorus-doped, and heavily antimony-doped substrate wafers processed through a simulated Twin Tub CMOSfabrication flow. Inhibition of oxygen precipitation and microdefect formation in the bulk of n-type substrate wafers was observed inboth heavily phosphorus- and antimony-doped wafers. Microdefects formed at the epilsubstrate interface were observed only inheavily phosphorus doped wafers. They might explain the better quality in the epilayer grown on heavily phosphorus doped substratesthan that on heavily antimony doped wafers.

INTRODUCTIONOne of the inherent limitations to CMOS device per-

formance is latch-up. Susceptibility to latch-up increaseswith increased device packing density as CMOS circuitsare scaled down to the micron and sub-micron levels. Amethod to eliminate latch-up in CMOS devices is throughthe use of silicon epitaxial structures [1-5J. Improvedlatch-up immunity by reduction in substrate resistance(Rs) can be obtained through the use of n-type epilayersover heavily doped n+ substrates [6,7,8J. Although theuse of n on n + epitaxial structures improves CMOSlatch-up immunity, the quality of the epilayer also directlyaffects other device parameters and yield [9,10J. One ofthe major concerns in using epitaxial structures forCMOS technology is the interaction of substrate materialproperties on epilayer quality.

The application of intrinsic gettering techniques tosilicon epitaxial processing has mainly focused on bipolardevices using n on p epitaxial structures [11,12J. Since up-coming CMOS technology is mostly based upon n/n + orp/p+ structures, it is very important to understand theinteraction of heavily doped substrate material propertieswith oxygen precipitation gettering mechanisms. To ourknowledge, a rather limited number of scientific reportshave so far appeared in the literature on this subject[13-15J. In this investigation, we examined the effec-tiveness and durability of intrinsic gettering techniquesfor various n/n + epitaxial, structures by monitoringminority carrier lifetime and defect distributionthroughout simulated CMOS Twin Tub Process cycles.

EXPERIMENTALN-type silicon crystals for this investigation were

grown in a Siltec 8600 model furnace under the samegrowth conditions. The details of the growing parametersare described elsewhere [16J. Dopants were antimonyand phosphorus and resistivity was in the range of0.01-0.02 ohm-ern. The growth direction was < 100>.Crystal diameter and length were 100 mm and about580 mm, respectively. For these heavily doped wafers, nodirect measurement of oxygen content was possible bythe IR method due to free carrier absorption. However,in the growing process used to produce these crystals,oxygen content of lightly-doped materials ranges from 13

to 18 ppma (with the conversion factor of 4.9). Recentstudies by Japanese researchers indicate that heavilydoped n-type materials generally exhibit lower oxygencontents than lightly doped materials grown under thesame conditions [17,18J. High resistivity (n ") wafers(10-12 ohm-ern) were included in our tests as a controlgroup. Interstitital oxygen content of these waferstypically ranged from 16 to 18 ppma. Carbon concentra-tions were <0.5 ppma. Prior to epi deposition, some ofthe wafers were subjected to a high-low-medium, three-step pre-epitaxial intrinsic gettering cycle. This getteringcycle was chosen based on the results from earlier investi-gations [5J. First, a protective oxide was grown at 950°for 45 min. in a dry O2 ambient. This was followed by a4-h denudation cycle at 1150°C in N2. Nucleation wasachieved by a 16-h anneal at 700°C in N2. Finally, a 24-h

1. Non·gettered, after Ini. Ox.2. Non·gettered, after Gate Ox.3. IG, after Ini. Ox. //- ---t:;'4. IG, after Gate Ox. -z-:

5 1018 ;-,-- ;-

~/

//

Z /

0 //

~ 4/a: Il- IZ IW I 20Z 1016 I

0 IIo Ia: Iw I

a: Ia: I~ I0 I

//

/

10140 4 8 12 16 20 24

DEPTH (Jtm)

Fig. 1. Typical doping profile of non-gettered and IG n/n + (P)epitaxial structures during simulated CMOS cycles.

2

1020 1. Non·gettered, after Ini. Ox.2. Non·gettered, after Gate Ox.

e- 3. IG, after Ini. Ox.E 4. IG, after Gate Ox.u

~Z 10180~ Aa: II-

4/zw0 IZ I0 I0 1016 I

Ia: ,w

"2 3'0: Ia: I< / 10 /

10144 8 12 16 20

DEPTH (j.tm)

Fig. 2. Typical doping profile of non-gettered and IG n/n + (Sb)epitaxial structures during simulated CMOS cycles.

anneal was carried out at 950°C in N2 to induce oxygenprecipitation and microdefect formation inside the bulkof the wafer. N-type arsenic-doped epilayers, 10 to15 ohm-ern, were grown in an AMC-7810 radiantlyheated barrel reactor. SiHCl3 was used as the source gas,and deposition occurred at 1100°C with a growth rate of0.75 /-tm/min. Epilayers grown over lightly phosphorous-doped substrates and heavily antimony-doped substrateswere 15 /-tmthick while those over heavily phosphoroussubstrates were 18 /-tm in thickness. The heavilyphosphorous doped substrates were oxide backsidesealed prior to epi deposition. After epilayer deposition,wafers were subjected to a simulated CMOS Twin Tubprocess. For this study, wafers went through the front-end temperature cycles (up to gate oxidation) withoutreceiving any implantation and masking steps.

Two wafers of each group were pulled after (i) initialoxidation, (ii) n-well drive, and (iii) gate oxidation forminority carrier lifetime, doping profile and defectdistribution measurements. To measure minority carrierlifetime, wafers were stripped and a 1000 A gate oxidelayer was grown thermally at 950°C. AI-Si dots (2 mmdiameter) were then sputtered on the front surface toform MOS capacitors. Wafers were annealed at 450°Cfor 40 min. in forming gas before profile C-t measure-ments. Changes of epi/substrate doping profile duringthe simulated CMOS cycles were checked by spreadingresistance probe (SRP) measurements. Planar and cross-section defect distribution for various epilsubstrates werechemically delineated by Wright etchant for 3 min. foroptical microscopic observations. The planar defect den-sity was determined by the 9-point counting method [19].

RESULTS AND DISCUSSIONI. TRANSITION REGION WIDTH

By tailoring the epi/substrate dopant transitionregion width and epilayer thickness to a given CMOSprocess, latch-up hardening can be greatly enhanced. Asharper transition region has been known to improvelatch-up hardness [5]. Besides latch-up, transition regionwidth is an important parameter for the determination of

SooKap Hahn, John O. Borland, Ci-C. Daniel Wong

104

UCIIen3w:::!:~ 103Wu..::::ia: IG n/n + (P)w IG n/n + (Sb)0:a: n-<0 102 IG n/n->I-0: n/n + (P)0z~ n/n + (Sb)

101 n/n-AFTER INITIAL AFTER WELL AFTER GATE

Ox DRIVE Ox

Fig. 3. Variation of minority carrier lifetime in epilayers grownon various n-type substrates during simulated CMOS cycles.

DEFECT DENSITY (#/cm2)

WAFER STACKINGTYPE ETCH PITS FAULTS

n- O 0n/n : 314 105IG nIn- O 523nln + (P) 698 87nln + (Sb) 1343 140IG nln + (P) 314 0IG nln + (Sb) 419 52

Table 1. Radial defect density of various n/n - and n/n + epistructures, and n - substrates based upon the 9-point countingmethod.

epilayer quality since it affects the doping level inside theepilayer. In this study, doping profiles of n/n + epi struc-tures were measured. Typical SRP profiles for non-getteredand intrinsically-gettered (Ie) n/n + epi structures duringCMOS cycles are shown in figures 1 and 2. Our dataclearly demonstrate that n/n + (P) exhibits a much widertransition region than n/n+ (Sb). This is not surprisingsince the diffusion coefficient of phosphorous is muchhigher than that of antimony. Therefore, CMOS devicesfabricated on n/n + (Sb) epi wafers are expected to bemore latch-up resistant than those on n/n + (P) epiwafers. We also noticed that Ie n/n + epi wafers alwaysdevelop a lar*er transition width region than that of non-gettered n/n epi wafers.II. MINORITY CARRIER LIFETIME

Minority carrier lifetime is sensitive to thecrystallographic perfection and chemical purity of thematerial (20). The variation in minority carrier lifetimefor various epi/substrate structures during the simulatedCMOS cycle is shown in figure 3. The results show thatthe minority carrier lifetime of epilayers on Ie n +substrates is higher than that of layers on non-getteredn + substrates. Also, carrier lifetime of epilayers on n +(P) substrates is generally higher than that of layers n +

Effects of N-type Substrate on Epilayer Quality for Twin Tub CMOS Technology 3

4(b). 5.

Fig. 4. Cross section optical photomicrographs for (a) non-gettered n/n + (P) and (b) non-gettered n/n + (Sb) epi structure after the gateoxidation cycle (Vertical scale is 5 times horizontal scale).

Fig. 5. Cross section optical photomicrograph for a lightly phosphorous doped (n -) wafer after the gate oxidation cycle (Vertical andhorizontal scales are same as Fig. 4).

(Sb) substrates. Beneficial effects from pre-epitaxial in-trinsic gettering cycles mostly occur after the n-well drivestep rather than after the initial oxidation. After then-well drive step, minority carrier lifetime drops quiterapidly during the tail end of the CMOS process cycles.At present, the cause of this rapid drop is not understood.III. DEFECT DISTRIBUTIONS

A. RADIAL DISTRIBUTIONS

The radial defect density of the epilayer during theCMOS cycles was measured (based upon the 9-pointcounting method). The density of etch pits and stackingfaults in various n/n +, n/n - epi structures and n "substrates is summarized in Table I. It was noted thatlightly phosphorous doped (n -) substrates are free of anycrystallographic defects even after the gate oxidationcycle. In the case of heavily doped substrates, the defectdensity of epilayer on IG n + substrates is significantlylower than that of layers on non-gettered n + substrates.Also, the defect level of epilayers grown on heavilyphosphorous-doped substrates is generally lower thanthat of layers grown on heavily antimony-dopedsubstrates.

6(a).

B. CROSS-SECTIONAL DISTRIBUTIONS

Oxygen precipitation and microdefect formation inthe bulk of n-type substrates is strongly suppressed byhigh doping concentrations of phosphorous and anti-mony throughout the simulated CMOS cycles as shownin figure 4. This is not evident for lightly phosphorousdoped wafers as shown in figure 5. In contrast to non-gettered n/n + epi structures, IG n/n + epi structuresdevelop a rather well-defined denuded zone with somenoticeable amounts of precipitates inside the bulk shownin figure 6. Even though the behavior of heavilyphosphorous doped substrate was similar to that ofheavily antimony doped substrate, there exists anoticeable difference. In the case n/n + (P) structures, arather pronounced defect layer close to the epi/substratetransition region was observed while no such layer waspresent in n/n + (Sb) structures (see figure 7).

The type of these microdefects is still under investi-gation. These microdefects in the epi/substrate transitionregion might explain the higher quality in the epilayergrown on heavily phosphorous-doped substrates com-pared to that on heavily antimony-doped substrates.

7.

Fig. 6. Cross section optical photomicrographs for (a) IG n/n + (P) and (b) IG n/n + (Sb) epi structure after the gate oxidation cycle(Vertical and horizontal scales are same as those of Fig. 4).Fig. 7. Cross section optical photomicrograph of a defect layer found at the transition region of an n/n + (P) epitaxial structure after thegate oxidation cycle (Vertical scale is 5 times horizontal scale).

4

EXPERIMENTAL STEPS

CRYSTAL GROWTHn -, n + (P), n + (Sb)

1PRE·EPI INTRINSIC

GETTERING CYCLES

TEPI DEPOSITION

1INITIAL OXIDATION

IL

N·WELL DRIVE

Ii

GATE OXIDATION

Ii

END

SIMULATEDTWIN TUB

CMOSPROCESSCYCLES

DOPINGPROFILE

!MINORITYCARRIERLIFETIME

LDEFECT

DISTRIBUTION(Planar &

cress-seeucra

SUMMARYIn this study, the effects of n-type substrate doping

level and species on epilayer quality for a CMOS TwinTub process technology were investigated in variousn/n + epi structures. The following is a brief summary ofexperimental observations: . .1. Oxygen precipitation and microdefect formation In-

side the bulk of n-type substrates is inhibited by highdoping concentrations of phosphorous or anti~on>-:.

2. Through the application of a three-step pre-epitaxialintrinsic gettering technique, a minority carrierlifetime in epilayers equivalent to that of lightlyphosphorous doped wafers can be maintain~dthroughout the simulated CMOS process cycles Inheavily phosphorous- and antimony-doped wafers.

3. A pronounced defect layer in the epi/substrate transi-tion region was observed for n/n + (P) epi structures.This might explain the better quality of epilayersgrown on heavily phosphorous-doped substrates ascompared to that of layers grown on heavilyantimony-doped substrates.

Previously printed in VLSI Science and Technology /1985,Proceedings of the Third International Symposium onVery Large Scale Integration Science and Technology,Volume 85-5, The Electrochemical Society, Inc., 10South Main St., Pennington, N.J. 08534-2896.

©Applied Materials, Inc. 1985

SooKap Hahn, John O. Borland, Cv-C. Daniel Wong

ACKNOWLEDGMENT

The authors wish to thank Dean L. Bender, LoriCoates and Terry Fish for technical assistance.

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