Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

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Efficient Layout Design of CMOSFull Subtractor

Harmeet SinghME Scholar, Department of Electronics and Communications Engineering

National Institute of Technical Teachers Training & Research, Chandigarh, Indiaharmeet_s_d@yahoo.co.in

Abstract—Arithmetic circuits and for that matterCombinational circuit design is very important part of VLSIdesign process. The pertinent issues involved are layout areaand power consumption. The main aim of this paper is todesign a full subtractor using 90 nm technology. Theproposed full subtractor has been designed and simulatedusing DSCH 3.1 auto-generated design and using Microwind3.1 simulation software for semi-custom design. The resultsobtained show that the semi-custom design is area efficientthan the auto-generated design. On the other hand, powerconsumption in the later is more as compared to the auto-generated design.

Keywords—Automatic,Full Subtractor, Semi-Custom, VLSI

INTRODUCTION

Advances in CMOS technology have led to a invigoratedinterest in the development and methods of basicfunctional units for digital systems. Increased usage of thebattery-operated portable devices, like cellular phones,personal digital assistants (PDAs), and notebooks demandVLSI(Very Large Scale Integration) is the technology, andULSI i.e. Ultra Large-Scale Integration designs with animproved power-delay characteristics. Fullsubtractors/adders, being one of the most fundamentalbuilding block of all the aforementioned circuitapplications, remain a key focus domain of the researchersover the years [1], [2]. Due to this, technology scaling andenergy-efficiency of functional units is of increasingimportance to system designers. VLSI is the technology forcreating an integrated circuit by combining millions oftransistors in a single Integrated Circuit. Themicroprocessors used in DSP operations e.g. in imageprocessing applications. Before the introduction of VLSItechnology, most ICs had a limited functionality. ICs havethree key advantages over digital circuits viz. size, powerconsumption and speed. This leads to layout design and itssimulation so as to get very near to an implementablecircuit design on silicon wafer. So far several technologieshave been used to design full subtractor cell to improvearea and power consumption [4]-[8]. Design of fullsubtractor by using conventional CMOS design style hasbeen presented. To study the performance of reducedtransistor circuit count design, a transistor level design ofCMOS full subtractor containing a total of 17 PMOS and17 NMOS transistors has been implemented. It is requiredto adjust the transistor dimensions individually to getoptimized time domain performance of the circuit. Here,all NMOS and PMOS transistors used in this circuit havethe same W/L ratio. This leads to a semi-custom design.

SUBTRACTORHalf-SubtractorA half subtractor is a circuit using combinational designprinciples that performs a subtraction between two bits asshown in Fig.1. The circuit performs its function using twoinputs A, B viz. minuend, subtrahend and two outputs, onebit for result of subtraction viz. Diff , and an outputborrow Bout [9].

Fig. 1 Logic Diagram of conventional Half Subtractor

Full Subtractor1- bit full Subtractor is a circuit based upon combining twohalf-subtractors that performs subtraction between twobinary bits. This circuit performs its function using threeinputs keeping account of a previous borrow and twooutputs. The three inputs are A, B and Bin and Boout andDiff are two outputs[9]. Logic diagram of 1-bit fullSubtractor has been shown in Fig.2. The correspondingTruth Table is given in Table 1.

Fig. 2 Logic Diagram of conventional 1 bit Full Subtractor

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

41 NITTTR, Chandigarh EDIT-2015

Table 1:

From the Truth Table,we find the logical expressions forthe full subtractor as follows:Bout = Bin (A’B’ + AB) + A’B

Diff= A ⊕ B ⊕ Bin

In subtraction process on two bits, a minuend and asubtrahend, and also takes into consideration whether a 1has been borrowed by the previous adjacent lowerminuend bit or not. As a result, there are three bits to behandled at the input of a Full-Subtractor, namely the twobits to be subtracted and a borrow bit designated as Bin.There are two outputs, namely the Difference output Diffand the Borrow output Bout. The Borrow output bit tellswhether the minuend bit needs to borrow a 1 from the nextpossible higher minuend bit.

III. LAYOUT DESIGN SIMULATIONIn first method the schematic of full subtractor using twohalf subtractors is designed using DSCH. UsingMicrowind software auto-generated layout of full-subtractor is created, and then it is simulated for analogsimulation. In the present design, 90 nm foundary isselected. Figure 3 shows the auto-generated layout. Thelayout is checked for DRC so that the errors if any areremoved, and then it is simulated for Timing Waveforms.Generated waveforms are verified for logical /functionalcorrectness. Also Power and Surface Area are measured bythe simulation results[10].Figure 4 shows the timing diagram of auto-generatedlayout.

Fig. 3. Manually designed Layout of XOR/FS

Fig 4. Analog Simulation of auto-generated FS

Here, the Power consumption is 1.295 µW. Area requiredfor this particular layout is 1810.3 µm2. In the secondapproach i.e. semi-custom approach, we prepare layoutusing manual approach; an xor design using lesser numberof transistors is used but the designer uses lambda rules asa whole. Figure 5 shows the layout thus generated.

Fig. 5. Manually designed Layout of FS

The semi-custom layout is checked for DRC so that errorsare removed. The circuit is simulated and timingwaveforms are generated. The timing waveforms areverified using Truth Table for logical correctness. Fig. 6shows the results of this simulation.

Fig. 6 Analog Simulation of Semi-custom FS

Here, the Power consumption is 1517.7 mW. Arearequired for this particular layout is 393.6 µm2. In thesecond approach i.e. Semicustom approach, we preparelayout using manual approach; an xor design using lessernumber of transistors is used but the designer uses lambdarules as a whole. Figure 6 shows the layout thus generated.

IV. PERFORMANCEThe performance of proposed full subtractor layout iscompared with semicustom approach when the auto

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

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generated design is the reference. The performanceparameters are area and power. From the results obtained,a comparative study can be done between three designapproaches Table II shows the comparative analysis.

S.No.Performance parameters

Designmethod

Area(µm2) Power(µW)

1

2

Auto-generated

2054.3 393.2

Semi-custom 16.683 1517.7

From the above table, we observe that there is a reductionof 99% in area with autogenerated layout. Simultaneouslythere is 74% increase in area with the semicustom designapproach.

IV. CONCLUSIONSFrom the above analysis it is clear that the semicustomdesign is significantly more efficient in terms of area. Sothis design can be implemented where area reduction is themain consideration . A large number of application aboundwhere this is required as in portable devices like smartphones, remote controls , tablets and so on. There is somedegradation in logic levels during simulation which shallbe worked upon and improved upon in the continuingresearch effort, by the authors,in this particular area.

ACKNOWLEDGEMENTSThe authors would like to thank Director, National Instituteof Technical Teachers Training & Research, Chandigarh,India and Director, Sunrise Group of Engineering andTechnology for their constant inspiration and supportthroughout Research Work.

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