ekv compact model extension for high-voltage lateral dmos transistors

EKV Compact ModelEKV Compact ModelExtension for High-Extension for High-Voltage Voltage Lateral DMOS Lateral DMOS TransistorsTransistors N. Hefyene (1)

C. Anghel (1)

J.M. Sallese (1)

A.M. Ionescu (1)

(1) EPFL, Lausanne, Switzerland

Contact: [email protected]

Outline

· Investigated HV devices

· Intrinsic-Drain voltage concept

· MESDRIFT structure

· Drift resistance modeling

· EKV Model extension to HV DMOS transistors

· Model Parameter

· Model vs. Measurements

· Optimizing Strategy

· Advantages & Limitations

· Future Developements

MOS-AK, 5th May 2003, Crolles, FranceMOS-AK, 5th May 2003, Crolles, France 11

• INVETIGATED STRUCTURESINVETIGATED STRUCTURES

EXtended lateral DMOS architecture (XDMOS)

n-channel transistor

Lch= 4m

not self-aligned

0.7 m HV-CMOS technology from Alcatel Microelectronics (AMIS)

K-point(VK)

Intrinsic channel

Drift region


• INTRINSIC - DRAININTRINSIC - DRAIN VOLTAGE CONCEPTVOLTAGE CONCEPT

Systematic inspections of the K-point potential

(VK) in all regimes of operation reveal…

Numerical simulationsof XDMOS

architectures

VK < 10Vfor: VG 12V

VD 100V

Intrinsic DMOS channel behaves like a low-voltage MOSFET

model the intrinsic DMOS channel with a standard low-voltage MOSFET model (like BSIM or EKV)

separately model the characteristics of the drift region

VK (VG, VD)


• MESDRIFT : MESDRIFT : a new test structurea new test structure

MESDRIFT structure :

n+-implant near the channel - drift region delimitation

high-impedance voltmeter to monitor the VK potential

Features :

small dimensions of the K-contact compared to the global device width (10 200 m)

minor influences on the global device characteristics are expected

“Upper view”

n-well

p-substrate

- +

VMU (VK)

VS

K-contact

Channel region

VG

VD

-implant n +

Drift-region

- + - +

“Cross-sectional illustration”


• XDMOS XDMOS vs.vs. MESDRIFT : MESDRIFT : DC characteristics DC characteristics ((W = 40 W = 40 mm))

“ID (VG) @ # VD” “ID (VD) @ # VG”

increased leakage currents in the sub-threshold region

overall good match between XDMOS and MESDRIFT characteristics

slight shift in VDBR for the MESDRIFT test structure at low VG (<5%)

( ) MESDRIFT vs.

( ) XDMOS


• MESDRIFT : MESDRIFT : typical extractedtypical extracted Drift characteristicsDrift characteristics

VK potential evolution with external biases as predicted by 2D numerical simulation

VK VD

VK VG

Drift resistance evolution with external biases : RD = (VD – VK) ID

in agreement with 2D numerical simulations (better at high VG , due to the formation of a

drift accumulation layer beneath gate oxide)0.1

1

10

100

0 5 10 15 20

VD (V)

RD =

(VD -

VK) /

ID

VG = 2, 3, 4, 6, 8, 10 and 12V

“RD(VD) @ # VG”

0

5

10

15

0 10 20 30

VD (V)

VK (

V)

VG = 3V

4V

5V

6V

12V

“VK(VD) @ # VG”


• DRIFT RESISTANCE MODELINGDRIFT RESISTANCE MODELINGThe proposed The proposed quasi-empiricalquasi-empirical drift expression… drift expression…

rrD0D0, rrD1D1, 00, 11, 00, 22, 11 & 00 room temperature parameters (T0)

mm and nn temperature dependence parameters (T)

Features :

limited number of parameters… 10!

good accuracy over temperature… 25°C up to 150°C

unique expression for different drain architectures (p- & n-channel XDMOS)1.E+02

1.E+03

1.E+04

1.E+05

0 5 10 15 20 25 30 35

-VD (V)

RD

(O

hm

)

VG = -2V

T = 25°C 75°C 125°C

-5V

-1 2V

p-channel DMOS

1.E+03

1.E+04

1.E+05

0 5 10 15 20 25 30 35

VD (V)

RD

(O

hm

)

VG = 2V

T = 2 5°C 7 5°C 15 0°C

4V

12V

n-channelDMOS

Drift expression vs. measured RDrift expression vs. measured RDD (V (VDD, V, VGG) :) :

( ) Measured vs. ( ) modeled characteristics

nmV

1

0

VVVV

G0

1D0DGDD

D0G1

2G2D0G1

T

T1eln

1Vγ

rr)T,V,V(R


• HV-DMOS MODELINGHV-DMOS MODELING Two possible approaches :

MACROMACRO - modeling…

discrete elements tied together to form a circuit (e.g. MOSFET, JFET, diode, capacitor, Resistor… etc.)

COMPACTCOMPACT - modeling…

consider the device unity

Expression continuity in all regimes of operations

a set of self-consistent expressions able to predict and reproduce specific phenomenaVS

VG

VD

VB

JFETnMOS pMOS

Diodes

accuracyaccuracy

simulation timesimulation time

parameters nparameters noo & & extractionextraction

VS

VG

VD

VB

Drift model nMOS

std. MOS + drift model parameters

circuit complexity

no of nodes

►►

no of elements

►

model complexity

no of device phenomena to be considered


• MODELING WITH MODELING WITH EKVEKVAssumptions long-channel approximation (i.e. short-channel effects are neglected)

eff (i.e. simplified mobility dependence on 2D field-effects)

rfD ii

I

Ii

0

S(K)

t

)K(SPS(K) q-ln

U

VVq

2

1

2

t

)K(SPS(K) U

VVq

2

S(K)S(K)f(r) qqi 2

ImplicitImplicit expression

Can only be solved Numerically

Simple Analytical solutions

Simplified expressionStrong-Inversion

Complete expressionWeak & Strong-Inversion

ExplicitExplicit expression

(2nd order polynomial)

GV,DVKGVPD V,VfI


Strong Inversion expressionsStrong Inversion expressions

Effective mobility :

Current expressions :

*DSDTGG

0eff

Vθ)VV(θ

μμ

t

)K(SPS(K) U

VVq

2Charge expression :

ox

CHsi

C

Nε2qγ

Quasi-empirical drift expression

DGDDDK V,VRIVV

δ

VVVV TG

Dsat*DS

F2ψ2

γδ

K2

KS2

S0rf*

D qqqqIiiI

S2

S0fDsat qqIiI

η

I

IIsF

Dsat

DDsat

Dsat*

DD IFs1IFsI

Smoothing function (i.e. linear to saturation transition)

Total current expression

,

),T,N,C,L,W(fI effchox0


• MODEL PARAMETER:MODEL PARAMETER:NAME PARAMETER TYPE

VT Threshold voltage Extracted parameter

o Low-field mobility Extracted parameter

VFB Flat-band voltage Extracted parameter

NCH Channel doping Extracted parameter

TOX Gate oxide thickness Extracted parameter

G Transversal mobility degradation factor Fitting parameter

D Lateral mobility degradation factor Fitting parameter

Smoothing factor Fitting parameter

rD0 Drift parameter Fitting parameter

rD1 Drift parameter Fitting parameter

0 Drift parameter Fitting parameter







• COMPACT- MODEL COMPACT- MODEL vs.vs. MEASURES : MEASURES : Fitted on a standard 4 m n-channel XDMOS device, using the simplified drain expression.


IIDD-V-VDD characteristics (T characteristics (TRR))

0.E+00

1.E-03

2.E-03

3.E-03

4.E-03

5.E-03

0 10 20 30 40

VD (V)

I D (

A)

= 3V

= 4V

= 6V

= 8V= 9V

= 5V

= 7V

VG = 10V

1.E-06

1.E-05

1.E-04

1.E-03

0 10 20 30 40

VD (V)

gds

(

-1)

VG = 4V

VG = 6V

VG = 8V

VG = 10VVG = 9V

VG = 3V

VG = 5VVG = 7V

ID(VD) @ # VGgD(VD) @ # VG


0

2

4

6

8

10

1 2 3 4 5 6 7 8

VG (V)

MA

X &

RM

SE

rror

%

3 4 5 6 7 8 9 10

For ID(VD) curves

0

2

4

6

8

10

1 2 3 4 5 6 7 8 9 10 11

VD (V)

MA

X &

RM

SE

rror%

10


IIDD-V-VGG characteristics (T characteristics (TRR))

0.E+00

1.E-03

2.E-03

3.E-03

4.E-03

0 3 6 9 12

VG (V)

I D (

A)

= 1V

= 2V

= 3V= 4V= 5V= 6V

= 10V

VD = 20V

= 9V

= 7V= 8V

ID(VG) @ # VD

0.E+00

2.E-04

4.E-04

6.E-04

8.E-04

1.E-03

0 2 4 6 8 10 12 14

VG (V)

gm (

S)

VD = 2 to 10V / 1V step& 20V

gm(VG) @ # VD

For ID(VG) curves

** Errors calculated for G 3V


DGVPD2DGD I,V,VfT,V,VR

T,DV,GVDGVPD1D R,V,VfI

1000

10000

100000

0 5 10 15 20 25 30 35

VD (V)

RD (

)

VG = 4, 6, 8, 10 and 12V

n-channel DMOS

• GLOBAL OPTIMIZING STRATEGYGLOBAL OPTIMIZING STRATEGY

simplified ID formula ►► explicit expression ►►

since:

GDSD V,V,VfI

depend on known quantities (i.e. VG, VD and measured ID)

0cRbRa D2

D

( ) Extracted (calculated) with RD(VG, VD, T)

“Rdrift(VD) @ # VG”

( ) Measured on MESDRIFT structure


(i) Performing standard extrinsic I-V measurements on the HV DMOS transistor;

(ii) Extracting VT and 0 parameters;

(iii) Calculating drift resistance characteristics according to : ;

(iv) Fitting, with the quasi-empirical drift expression the calculated drift- resistance in (iii);

(v) Injecting the drift parameters, together with the extracted VT and 0 values,

in the simplified drain current expression+

optimisation of the set of injected parameters to fit the desired DC measured characteristics

NOTE: In case weak and moderates inversions have to be modelled, optimised parameters from (v) can be used as initial guess values for the more complex implicit expression of the drain current.

The modelling strategyThe modelling strategy can be sequenced as follows:can be sequenced as follows:

DGPDDGD I,VV,VfT,V,VR 2


Model Advantages :

a total # of (8+4) parameters for room temperature model

simple and fast extraction of intrinsic MOS parameters (i.e. VT and 0)

a modeling strategy and an extraction procedure, independent on the MESDRIFT architecture

a charge based model; adequate and more convenient for AC modeling!

• ADVANTAGES & LIMITATIONS ADVANTAGES & LIMITATIONS

Limitations :

limited accuracy in the weak inversion region (to be improved)


• FUTURE DEVELOPEMENTSFUTURE DEVELOPEMENTS

including the temperature dependence for the intrinsic channel part (under development)

Replacing the simplified EKV model by a more complete version (e.g. EKV 2.6)

implementing model equations into simulator using Verilog-A code (under development)

AC-modeling with a charge based approach (under development)

complete model implementation into simulators (e.g. SPICE or SABER)

Acknowledgements:Acknowledgements:

This work was supported by the IST-1999-12257 ‘AUTOMACS' EC project and the Swiss OFES no. 00-0009.


ekv compact model extension for high-voltage lateral dmos transistors

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