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ELAN RII CPU Macro Assembler v0.20

18 April, 2003

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ELAN RII CPU Macro Assembler

1. Source Files Assembly source file (*.asm) should be written with this assembly language and can include files written in the same language. Each statement line in the source file should adhere to the following format: [Label [:]] Mnemonics [Operands] [;Comments] Blank lines are treated as comments. Blanks or tabs separate elements of the statement line. All symbols are case insensitive. 1.1 Label

Label name must start from column 1 of the line and may be terminated by a colon (:). The label and the colon can be seperated by blanks. Labels must begin with an alphabetic character or an underscore (_) or (@) and followed by alphanumeric characters or underscore(_) or (@). The max label length is 32 characters including ‘:’. If the label field has a colon sign, then the mnemonic can follow immediately without space to seperate characters. Assembler directives INCLUDE, DEFINE, UNDEF, PUBLIC, EXTERN can start from column 1.

1.2 Mnemonic Assembler instructions, directives, and macro calls must begin after column 1.

1.3 Operands Instruction operands or macro parameters: Multiple operands must be separated by commas(,). Operands start with a pound sign ‘#’, which means immediate addressing .

1.4 Comments Comments must start with a semicolon (;) in a line or in a block enclosed within /* and */.


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2. Output Files The output files after assembly become List file (*.lst) and Object file (*.obj) from the source file.

2.1 List File The List file is generated after a source file is assembled successfully. The starting address shown on the List file begins at 0x00 no matter how user sets the absolute address, i.e., by CSEG directive or otherwise. For the instructions with labels (ex: jmp, call), the operand part of the object code will always be 0 due to the linker relocated property. The final result of a project after a link process will show in MAP file. The MAP file is generated after linking and it will show the absolute code location and the object code with absolute operand in opcode.

Format: Line1:Version information (ELAN RII8000 CPU Assembler version X.XX List file) Line2: Filename (C:\program files\project\test.asm) Line3: Assemble date and time (Mon Apr 24 12:00:00 2000) Line4: Space Line5: Indication title (Line No Loc ObjCode Source) Line6: Space Line7+: The contents LineN-1: Space LineN: The final line shows the result of assembly

Description: The numbers in decimal under “Line No” show the line numbers of the corresponding

line. The number of the line from Include file is followed by an ‘I’ and the number of macro expansion line is followed by an ‘M’.

The numbers under “Loc” shows the address of the corresponding line in code segment. The “Loc” number starts from 0x0000 from every CSEG regardless of whether user writes the absolute address or not.

The numbers in hexadecimal under “ObjCode” shows the object code of the corresponding statement. If the source is an EQU definition, the value would be shown with a ‘=’ prefix. Because of relocation, the instruction with label will show the label value as 0.

The texts under “Source” show the corresponding original text line in the source file.


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List file format example:

ELAN RII8000 CPU Assembler version 0.00 List file C:\Progeam Files\project\test.asm Mon Apr 24 12:00:00 2000 Line No Loc ObjCode Source 1 INCLUDE <xxx.def> 1I ;Include line 1 2I ;Include line 2 3 00000 =0002 A1 equ 2 4 00001 A501 MOV A,#1 5 MACROCALL ; macro, defined anywhere 5M 00002 0000 NOP ;content of macro 5M 00003 0000 NOP ;content of macro 6 00004 A502 MOV A,#2 7 MOC A,#3 : Xxx Error(s), xxx Warning(s)

3. Numeric Presentation

Decimal 0d(D)<digits> or <digits>d(D) or <digits> Hexadecimal 0x(X)<digits> or <digits>h(H)

if started with A~F, must add ‘0’ first, ex: 0fH for fH. Octal 0o(O)<digits> or <digits>o(O)

Binary 0b(B)<digits> or <digits>b(B)


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4. Arithmetic Operators and Precedence in Expression

( Left parenthesis ) Right parenthesis ! Logical NOT - Unary Minus (Negative) ~ Complement * Multiplication / Division

% Modulo << Left shift >> Right shift + Add - Subtraction > Great than < Less than

>= Great than or equal to <= Less than or equal to == Equality != Not equal to & Bitwise AND ^ Bitwise XOR | Bitwise OR

&& Logical AND || Logical OR

5. Assembler Directive

5.1 END: End of program, all codes after END directive will be discarded. Syntax: END

5.2 EQU: Define a constant Syntax: <label> EQU <expression>


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5.3 DEFINE: Define a label Syntax: DEFINE <label> [<expression>] Description: Label is used for IFDEF/IFNDEF directive. If no expression is used, the label is set

to 1.

5.4 UNDEF: Undefine a label Syntax: UNDEF <label>

5.5 INCLUDE: Include additional source files Syntax: INCLUDE <filename> or INCLUDE “filename” Description: Used to Include files containing symbol definition, macro or procedure definition,

etc. An Include file can include other Include files and the maximum include depth should not exceed 8 levels. Filename within <> are searched in the path set by include path option or by the assembler executing path. Filename within “” are searched in the path where the source file is located.

5.6 PUBLIC: Specifies the label as a global label that may be referenced by other program.

Syntax: PUBLIC <label> [,<label>]

5.7 EXTERN: Imports external symbols from other files. Syntax: EXTERN <label> [,<label>]


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5.8 CSEG: Begin a code segment Syntax: [<name>] CSEG [<start address> ] Note: If ‘name’ or ‘start address’ are used, they must be in the same line as CSEG. Description: The CSEG sets the next statements in the designated segment of program ROM

until another CSEG or DSEG is encountered. A segment may be broken into pieces within a single source file or in different files. The broken pieces will be grouped together in memory according to the sequence as they appear. Segments with no ‘name’ specified are designated as ‘__defaultcode__’. The ‘start address’ is used in setting absolute address of this segment. If no ‘start address’ is set, linker will assign an address during linker execution. Linker links the segments under following rules: 1. Linker links files according to the sequence given by IDE. 2. If there are more than two segments with the same segment name, only the first

code segment definition can be set with a start address. The remaining segments will be grouped together one at a time according to the sequence they were defined. Otherwise, error is generated.

3. After the segments with ‘start address’ are allocated, the free program ROM may be broken into several fragments. If no fragment is large enough for allocation, the other re-locatable segment will generate errors. User needs to rearrange the segments.


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5.9 DSEG: Begin a data segment Syntax: [<name>] DSEG [<bank>, <offset>] Note: if ‘name’ or ‘start address’ are used, they must be in the same line as CSEG. Description: The DSEG assigns memory for the designated segment in RAM until another CSEG

or DSEG is encountered. The ‘bank’ and ‘offset’ set the address of this segment. The Data segment is not re-locatable by linker, that is, programmer must manage RAM allocation himself. A segment without the bank & offset specified will have the bank & offset assigned (by the assembler) from the previous data segment or start of RAM. The assembler treat the RAM as a linear area, thus the location after the end of one bank will be set to the start (0x80) of next bank. If unbank and stack bank are used, a warning message will occur. Only RES directive can be used in DSEG.

5.10 DB: Declare one byte data

Syntax: [<label>[:]] DB <expr> [,<expr>,…,<expr>] Description: Define byte in code segment only. Because of the 16-bit PROM word used, the byte

data are placed in the Low Byte, High Byte order in PROM. If odd number of byte is used, the final data are placed in Low Byte and the High Byte would be 0x00 if the next line is not DB line nor the first byte in the next DB line.

5.11 DW: Declare one word data

Syntax: [<label>[:]] DW <expr> [,<expr>,…,<expr>] Description: Used in code segment only.

5.12 TEXT: Declare multiple byte of continuous data Syntax: [<label>[:]] TEXT <”characters”> [,<”characters”>,…, <”characters”>] Description: Used in code segment only. The quoted characters are written in continues format.

The TEXT maximum length is 128 characters.


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5.13 RES: Reserve number of bytes memory in DSEG Syntax: [<label>[:]] RES <number> Description: Used in data segment only. ‘Number’ is the value of bytes to reserve. The label does

not record bank information when used in programming. User must set the correct bank himself while programming.

5.14 REPEAT, ENDR: repeat a block of statements

Syntax: REPEAT <constant number expression> [statements]

ENDR

6. Macro Directive

MACRO, ENDM: Macro definition statement Syntax: <label> MACRO [<param1>,…,<paramn>] <statements> ENDM Description: Macro must be defined before use. Calling other macro in a macro definition is

allowed. However, it is not allowed to define a new macro in a macro definition block or call the macro itself (recursive). The max levels of macro call is 8. Local labels in macro must started with ‘$’ and will be followed by a 3-digit sequencial number after expansion.

Ex: MAC1 MACRO

XXX

$LOCAL:

XXX

ENDM

$LOCAL will be $LOCAL001 in the first macro expansion and $LOCAL002 in the second.


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7. Conditional Directives

7.1 IF, ELSEIF, ELSE, ENDIF: IF conditional directives Syntax: IF <expression> <statements>

[ELSEIF <expression>

<statements>]

[ELSE

<statements>]

ENDIF

Description: The IF-ELSE-ELSEIF-ENDIF series directives cannot be used in MACRO body.

7.2 IFDEF, ELSEIFDEF, ELSE, ENDIF :IFDEF conditional directives Syntax: IFDEF <label> <statements>

[ELSEIFDEF <label>

<statements>]

[ELSE

<statements>]

ENDIF

Description: IFDEF is TRUE if the label value is non-zero, else FALSE.

7.3 IFNDEF, ELSEIFNDEF, ELSE, ENDIF: IFNDEF conditional directives Syntax: IFNDEF <label> <statements>

[ELSEIFNDEF <label>

<statements>]

[ELSE

<statement>]

ENDIF

Description: IFNDEF is TRUE if the label is zero, else FALSE.


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8. Branch

8.1 JMP: Jump to address Syntax: JMP <label> Description: JMP is used to indicate a branch and assembler will calculate the label address to

decide which jump command should be used.

8.2 CALL: Jump to subroutine Syntax: CALL <label> Description: CALL is used to indicate a function call and assembler will calculate the address to

decide which call command should be used. 9. Programming Note The final 32word address space in program ROM of each chip is reserved for test program and

code option. Be sure not to make code length extends to this area. For EPG3230, EPD3310; the first 32 word address space in program ROM have a special

application. Address Usage 0000 Reset vector 0002~000B 5 level interrupt vectors 000C-001F Reserved area (not for user use) 0020 User program

The instruction “RPT r” will repeat the next instruction content of register r times, but it cannot be followed by itself. All branch instructions are as follows: RPT, JBC, JBS, JDNZ, JINZ, JGE, JLE, JE, SJMP, LJMP, SCALL, S0CALL, and LCALL. The directives are JMP and CALL.


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10. Reserved Word A CSEG DB DEFINE DSEG DW ELSE ELSEIF ELSEIFDEF ELSEIFNDEF END ENDIF ENDM ENDR EQU EXTERN IF IFDEF IFNDEF INCLUDE MACRO UNDEF PUBLIC REPEAT RES TEXT JMP CALL ( ) + - * / % ! ~ == != << >> < > <= >= & ^ | && || $ # 11. Instruction Set

Remark: k : constant r : File Register addr : address b : bit p : special file register(00h~1Fh) i : Table pointer control

Type Instruction Binary Mnemonic Operation Status Affected

Cycles

0000 0000 0000 0000 NOP No Operation None 1 0000 0000 0000 0001 WDTC WDT<-0

/TO<-1, /PD<-1 None 1

0010 1011 1111 1110 RET PC<-(Top of stack) None 1 0010 1011 1111 1111 RETI PC<-(Top of stack)

Enable interrupt None 1

0000 0000 0000 0010 SLEP Enter IDEL MODE if MS1=1 Enter SLEEP MODE if MS1=0

None 1

System Control

0100 0011 kkkk kkkk BANK #k BSR<-k None 1 0100 0010 kkkk kkkk TBPTH #k TABPTRH<-k None 1 0100 0001 kkkk kkkk TBPTM #k TABPTRM<-k None 1 0100 0000 kkkk kkkk TBPTL #k TABPTRL<-k None 1 0010 11ii rrrr rrrr TBRD i,r r<-ROM[(TABPT)]

(*1,*2) None 2

Table Look Up

0010 1111 rrrr rrrr TBRD A,r r<-ROM[(TABPTR+ACC)] (*2)

None 2


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0000 0010 rrrr rrrr OR A,r A<- A.or.r Z 1 0000 0011 rrrr rrrr OR r, A r<- r.or.A Z 1 0100 0100 kkkk kkkk OR A, #k A<- A.or.k Z 1 0000 0100 rrrr rrrr AND A,r A<- A.and.r Z 1 0000 0101 rrrr rrrr AND r, A r<- r.and.A Z 1 0100 0101 kkkk kkkk AND A, #k A<- A.and.k Z 1 0000 0110 rrrr rrrr XOR A,r A<- A.xor.r Z 1 0000 0111 rrrr rrrr XOR r, A r<- r.xor.A Z 1 0100 0110 kkkk kkkk XOR A, #k A<- A.xor.k Z 1 0000 1000 rrrr rrrr COMA r A<- /r Z 1 0000 1001 rrrr rrrr COM r r<- /r Z 1 0000 1010 rrrr rrrr RRCA r A(n-1)<-r(n)

C<-r(0) ;A(7)<-C C 1

0000 1011 rrrr rrrr RRC r r(n-1)<- r(n) C<-r(0);r(7)<-C

C 1

0000 1100 rrrr rrrr RLCA A(n+1)<-r(n) C<-r(7);A(0)<-C

C 1

0000 1101 rrrr rrrr RLC r r(n+1)<- r(n) C<-r(7);r(0)<-C

C 1

0010 0010 rrrr rrrr SHRA r A(n-1)<- r(n) A(7)<-C

None 1

Logic

0010 0011 rrrr rrrr SHLA r A(n+1)<- r(n) A(0)<- C

None 1

0101 1bbb rrrr rrrr aaaa aaaa aaaa aaaa

JBC r,b,addr If r(b)=0, jump to addr (*3)

None 2

0110 0bbb rrrr rrrr aaaa aaaa aaaa aaaa

JBS r,b,addr If r(b)=1, jump to addr (*3)

None 2

0101 0000 rrrr rrrr aaaa aaaa aaaa aaaa

JDNZ A,r,addr A<- r-1, jump to addr if not zero (*3)

None 2


JDNZ r,addr r<- r-1, jump to addr if not zero (*3)

None 2


JINZ A,r,addr A<-r+1, jump to addr if not zero (*3)

None 2

Compare


JINZ r, addr r<- r+1, jump to addr if not zero (*3)

None 2


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0100 0111 kkkk kkkk aaaa aaaa aaaa aaaa

JGE A,#k,addr Jump to addr if A>=k (*3) None 2


JLE A,#k,addr Jump to addr if A<=k (*3) None 2


JE A,#k,addr Jump to addr if A=k (*3) None 2


JGE A,r,addr Jump to addr if A>=r (*3) None 2


JLE A,r,addr Jump to addr if A<=r (*3) None 2


JE A,r,addr Jump to addr if A=r (*3) None 2

0110 1bbb rrrr rrrr BC r,b r(b)<- 0 None 1 0111 0bbb rrrr rrrr BS r,b r(b)<- 1 None 1 0111 1bbb rrrr rrrr BTG r,b r(b)<- /r(b) None 1 0000 1111 rrrr rrrr SWAP r r(0:3)<- ->r(4:7) None 1 0000 1110 rrrr rrrr SWAPA r r(0:3)->A(4:7)

r(4:7)->A(0:3) None 1

0010 0100 rrrr rrrr CLR r r <- 0 Z 1 0010 0101 rrrr rrrr TEST r Z<- 0 if r<>0

Z<-1 if r=0 Z 1

Process

0010 0111 rrrr rrrr RPT r Single repeat *(r) times on next instruction, *(r) is the content of register r

None 1

0001 0000 rrrr rrrr ADD A,r A <- A+r C,DC,Z,OV,SGE,SLE

1

0001 0001 rrrr rrrr ADD r,A r<-r+A (*4) C,DC,Z,OV,SGE,SLE

1

0100 1010 kkkk kkkk ADD A,#k A<- A+k C,DC,Z,OV,SGE,SLE

1

0001 0010 rrrr rrrr ADC A,r A<-A+r+C C,DC,Z,OV,SGE,SLE

1

0001 0011 rrrr rrrr ADC r,A r<- r+A+C C,DC,Z,OV,SGE,SLE

1

Arithmetic

0100 1011 kkkk kkkk ADC A,#k A<- A+k+C C,DC,Z,OV,SGE,SLE

1

13


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0001 0110 rrrr rrrr SUB A,r A<-r-A C,DC,Z,OV,SGE,SLE

1

0001 0111 rrrr rrrr SUB r,A r<- r-A C,DC,Z,OV,SGE,SLE

1

0100 1100 kkkk kkkk SUB A,#k A<- k-A C,DC,Z,OV,SGE,SLE

1

0001 1000 rrrr rrrr SUBB A,r A<- r-A-/C C,DC,Z,OV,SGE,SLE

1

0001 1001 rrrr rrrr SUBB r,A r<- r-A-/C C,DC,Z,OV,SGE,SLE

1

0100 1101 kkkk kkkk SUBB A,#k A<- k-A-/C C,DC,Z,OV,SGE,SLE

1

0001 0100 rrrr rrrr ADDDC A,r A <- (Decimal ADD) A+r+C

C,DC,Z 1

0001 0101 rrrr rrrr ADDDC r,A R<- (Decimal ADD) r+A+C

C,DC,Z 1

0001 1010 rrrr rrrr SUBDB A, r A<- (Decimal SUB) r-A-/C

C,DC,Z 1

0001 1011 rrrr rrrr SUBDB r,A r<- (Decimal SUB) r-A-/C

C,DC,Z 1

0010 0110 rrrr rrrr MUL A,r PRODH:PRODL <- A*r None 1 0100 1111 kkkk kkkk MUL A,#k PRODH:PRODL <- A*k None 1 0001 1100 rrrr rrrr INCA r A<- r+1 C,Z 1 0001 1101 rrrr rrrr INC r r<- r+1 C,Z 1 0001 1110 rrrr rrrr DECA r A<- r-1 C,Z 1 0001 1111 rrrr rrrr DEC r r<- r-1 C,Z 1 0010 0000 rrrr rrrr MOV A,r A<-r Z 1 0010 0001 rrrr rrrr MOV r,A r<- A None 1 100p pppp rrrr rrrr MOVRP p,r Register p<- Register r None 1 101p pppp rrrr rrrr MOVPR r,p Register r<- Register p None 1

Move

0100 1110 kkkk kkkk MOV A,#k A<- k None 1

14


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110a aaaa aaaa aaaa SJMP addr PC<-addr; PC[13:16]

unchangd None 1

0011 aaaa aaaa aaaa S0CALL addr [Top of stack]<- PC+1 PC[11:0]<-addr PC[12:16]<-0000 (*5)

None 1

111a aaaa aaaa aaaa SCALL [Top of stack]<-PC+1 PC[12:0]<-addr PC[13:16] unchanged

None 1

0000 0000 0010 aaaa aaaa aaaa aaaa aaaa

LJMP addr (2 words)

PC<- addr None 2

Branch

0000 0000 0011 aaaa aaaa aaaa aaaa aaaa

LCALL addr (2 words)

[Top of stack]<-PC+2 PC<-addr

None 2

(*1) TBRD i,r: r<- ROM[(TABPTR)]; i=00: TABPTR not change i=01: TABPTR<- TABPTR+1 i=10: TABPTR<- TABPTR-1 (*2) TABPTR=(TABPTRH: TABPTRM: TABPTRL) *Bit 7 of TABPTRH is used to select internal ROM space or external memory space. Bit7=0: internal ROM space Bit7=1: external memory space *Bit 0 of TABPTRL is used to select low byte or high byte of pointed ROM data. Bit0=0: Low byte of pointed ROM data Bit0=1: High byte of pointed ROM data *The maximum table look up space is internal 8Mbytes and external 8Mbytes. (*3) The maximum jump range is 64K absolute address. That is, it can only jump within the same 64K range, i.e., 0~64K or 64K~128K. (*4) Carry bit of ADD PCL,A or ADD TABPTRL,A will automatic carry into PCH or TABPTR. The instruction cycle of write to PC (program counter) takes TWO cycles. (*5) S0CALL addressing ability is from 0x000 to 0xFFF (4k space)

elan rii cpu macro assembler - 義隆電子股份有限 … rii cpu macro assembler 1. source files...

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