elec 5270/6270 fall 2007 low-power design of electronic circuits low voltage low-power devices
DESCRIPTION
ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Low Voltage Low-Power Devices. Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 [email protected] - PowerPoint PPT PresentationTRANSCRIPT
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 11
ELEC 5270/6270 Fall 2007ELEC 5270/6270 Fall 2007Low-Power Design of Electronic CircuitsLow-Power Design of Electronic Circuits
Low Voltage Low-Power DevicesLow Voltage Low-Power Devices
Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor
Dept. of Electrical and Computer EngineeringDept. of Electrical and Computer EngineeringAuburn University, Auburn, AL 36849Auburn University, Auburn, AL 36849
[email protected]://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Fall07/course.html
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 22
CapacitancesCapacitances
In Out
C1
C2
VDD
GND
CW
Source
Drain
Drain
Source
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 33
Miller CapacitanceMiller Capacitance
In Out
C1
C2
VDD
GND
CW
CM
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 44
Before TransitionBefore Transition
In = 0 Out = VDD
C1
C2
VDD
GND
CW
CM
0 +VDD
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 55
After TransitionAfter Transition
In Out
C1
C2
VDD
GND
CW
CM
0+VDD
Energy from supply = 2 CM VDD
2
Effective capacitance = 2 CM
from pull-updevices ofprevious gate
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 66
Capacitances in MOSFETCapacitances in MOSFET
Source Drain
Gate oxide
Gate
BulkCs Cd
Cg
CgdCgs
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 77
Bulk nMOSFETBulk nMOSFET
n+
p-type body (bulk)
n+
L
W
SiO2
Thickness = tox
Gate
SourceDrain
Polysilicon
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 88
Gate CapacitanceGate Capacitance
Cg = Cox WL = C0 , intrinsic cap.
Cg = Cpermicron W
εoxCpermicron = Cox L= ── L
tox
where εox = 3.9ε0 for Silicon dioxide
= 3.9×8.85×10-14 F/cm
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 99
Approx. Intrinsic CapacitancesApprox. Intrinsic Capacitances
CapacitanceCapacitanceRegion of operationRegion of operation
CutoffCutoff LinearLinear SaturationSaturation
CgbCgb CC00 00 00
CgsCgs 00 CC0 0 /2/2 2/32/3 C C00
CgdCgd 00 CC0 0 /2/2 00
Cg = Cg = Cgs+Cgd+CgbCgs+Cgd+Cgb
CC00 CC00 2/3 2/3 CC00
Weste and Harris, CMOS VLSI Design, Addison-Wesley, 2005, p. 78.
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 1010
Low-Power TransistorsLow-Power Transistors
Device scaling to reduce capacitance and Device scaling to reduce capacitance and voltage.voltage.
Body bias to reduce threshold voltage and Body bias to reduce threshold voltage and leakage.leakage.
Multiple threshold CMOS (MTCMOS).Multiple threshold CMOS (MTCMOS).Silicon on insulator (SOI)Silicon on insulator (SOI)
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 1111
Device ScalingDevice Scaling
Reduced dimensionsReduced dimensionsReduce supply voltageReduce supply voltageReduce capacitancesReduce capacitancesReduce delayReduce delay Increase leakage due to reduced Increase leakage due to reduced VVDD DD / V/ Vthth
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 1212
A Simplistic ViewA Simplistic View
Assume:Assume:Dynamic power dominatesDynamic power dominatesPower reduces as square of supply voltage; should Power reduces as square of supply voltage; should
reduce with device scalingreduce with device scalingPower reduced linearly with capacitance; should Power reduced linearly with capacitance; should
reduce with device scalingreduce with device scalingDelay is proportional to Delay is proportional to RCRC time constant; time constant; RR is is
constant with scaling, constant with scaling, RCRC should reduce should reduce
Power reduces with scalingPower reduces with scaling
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 1313
Simplistic View (Continued)Simplistic View (Continued)What if voltage is further reduced below the What if voltage is further reduced below the
constant electric field value?constant electric field value?Will power continue to reduce? Will power continue to reduce? YesYes..Since Since RCRC is independent of voltage, can clock rate is independent of voltage, can clock rate
remain unchanged?remain unchanged?
Answer to last question:Answer to last question:Yes, if threshold voltage was zero.Yes, if threshold voltage was zero.No, in reality. Because relatively higher threshold No, in reality. Because relatively higher threshold
voltage will delay the beginning of capacitor voltage will delay the beginning of capacitor charging/discharging.charging/discharging.
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 1414
Consider Delay of InverterConsider Delay of Inverter
In Out
VDD
GND
C
R
t B t B
Charging ofC begins
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 1515
Idealized Input and OutputIdealized Input and Output t f
Vth
t B
0.5VDD
VDD
time0.69CR
INPU
TO
UTPU
T
Gate delay
t B = t f Vth /VDD
0.5VDD
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 1616
Gate DelayGate Delay
For VDD >Vth
Gate delay = (t fVth/VDD) + 0.69RC – 0.5 t
f
= t f (Vth/VDD – 0.5 ) + 0.69RC
For VDD ≤Vth
Gate delay = ∞
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 1717
Approx. Gate Delay vs. Approx. Gate Delay vs. VVDDDD
0.69RC
0.5t f
0.5t f
0 1 2 3 4 5
Gate
dela
y
VDD /Vth
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 1818
Power - Delay vs. Power - Delay vs. VVDDDD
0.69RC
0.5t f
0.5t f
0 1 2 3 4 5
Gate
dela
y
VDD /Vth
Pow
er
With leakage
~CVDD2
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 1919
Optimum Threshold VoltageOptimum Threshold Voltage
VDD / Vth
0 1 2 3 4 5 6
De
lay
or
En
erg
y-d
ela
yp
rod
uc
t
Delay
Energy-delay product
Vth = 0.7V
Vth = 0.3V
J. M. Rabaey and M. Pedram, Low Power Design Methodologies,Boston, Springer, 1996, p. 26.
Vth can be changed by varying doping level, oxide thickness and body bias.
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 2020
Low-Voltage InverterLow-Voltage Inverter Assumed always in saturation.Assumed always in saturation. Modeled as ideal current source.Modeled as ideal current source.
CL
ViVo
CL
Vi = VDDVo
K(VDD –Vthn)
K(VDD+ Vthp)
CL
Vi = 0 Vo
K(VDD –Vthn)
K(VDD+ Vthp)
VDDVDDVDD
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 2121
Power Supply ScalingPower Supply ScalingV
o V
olts
1.0
0.8
0.6
0.4
0.2
0.00.0 0.2 0.4 0.6 0.8 1.0
1.0
0.8
0.6
0.4
0.2
0.0
I DD m
A
Vi Volts
VDD= 1V
VDD= 0.5V
Vth ≈ 0.35V
J. Segura and C. F. Hawkins, CMOS Electronics, How It Works,How It Fails, IEEE Press and Wiley-Interscience, 2004, p. 116.
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 2222
Bulk nMOSFETBulk nMOSFET
n+
p-type body (bulk)
n+
L
W
SiO2
Thickness = tox
Gate
SourceDrain
Polysilicon
Vgs Vgd
Vds
+ +
+
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 2323
Transistor in Cut-Off StateTransistor in Cut-Off State
+- Vg < 0
- - - - - - - - - - - - - - - - - -
+ + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + +
Polysilicon gateSiO2
p-type body
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 2424
Threshold Voltage, Threshold Voltage, VVthth
+-0 < Vg < Vth
+ + + + + + + + + +
+ + + + + + + + + + + + +
+ + + + + + + + + + + + +
Depletion region
Polysilicon gateSiO2
p-type body
+-Vg > Vth
+ + + + + + + + + + + + +
- - - - - - - - - - - - - - - - - - -Depletion region
+ + + + + + + + + + + + ++ + + + + + + + + + + + +
Polysilicon gateSiO2
p-type body
Vth is a function of:Dopant concentration,Thickness of oxide
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 2525
Cutoff: Cutoff: IIdsds = 0 = 0
n+
p-type body (bulk)
n+
L
W
SiO2
Thickness = tox
Gate
SourceDrain
Polysilicon
Vgs Vgd
Vds = 0
+ +
+= 0
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 2626
Linear: Linear: IIdsds = 0 = 0
n+
p-type body (bulk)
n+
L
W
SiO2
Thickness = tox
Gate
SourceDrain
Polysilicon
Vgs Vgd
Vds = 0
+ +
+> Vth
= Vgs
- - - - - -
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 2727
Linear: Linear: IIdsds Increases with Increases with VVdsds
n+
p-type body (bulk)
n+
L
W
SiO2
Thickness = tox
Gate
SourceDrain
Polysilicon
Vgs Vgd
0 < Vds < Vgs-Vth
+ +
+> Vth
Vgs > Vgd > Vth
- - - - - -
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 2828
Saturation: Saturation: IIdsds Independent of Independent of VVdsds
n+
p-type body (bulk)
n+
L
W
SiO2
Thickness = tox
Gate
SourceDrain
Polysilicon
Vgs Vgd
0 < Vds > Vgs- Vth
+ +
+> Vth
Vgd < Vth
- - - - - -
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 2929
αα-Power Law Model-Power Law ModelVgs > Vth and Vds > Vdsat = Vgs – Vth (Saturation region):
βIds = Pc ─ (Vgs – Vth)α
2
where β = μCoxW/L, μ = mobility
For fully ON transistor, Vgs = Vds = VDD:
βIdsat = Pc ─ (VDD – Vth)α
2
T. Sakurai and A. R. Newton, “Alpha-Power Law MOSFET Model and Its Applications to CMOS Inverter Delay and Other Formulas,”IEEE J. Solid State Circuits, vol. 25, no. 2, pp. 584-594, 1990.
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 3030
αα-Power Law Model (Cont.)-Power Law Model (Cont.)
Vgs = 1.8V
Shockley
α-power law
Simulation
Vds
I ds
(μA
)
0 0.3 0.6 0.9 1.2 1.5 1.8
400
300
200
100
0
Idsat
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 3131
αα-Power Law Model (Cont.)-Power Law Model (Cont.)
0 Vgs < Vth cutoff
Ids = Idsat × Vds/Vdsat Vds < Vdsat linear
Idsat Vds > Vdsat saturation
Vdsat = Pv (Vgs – Vth)α/2
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 3232
αα-Power Law Model (Cont.)-Power Law Model (Cont.)
αα = 2, for long channel devices or low = 2, for long channel devices or low VVDDDD
αα ~ ~ 1, for short channel devices1, for short channel devices
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 3333
Power and DelayPower and Delay
Power = CVDD2
CVDD 1 1Inverter delay = ──── (─── + ─── )
4 Idsatn Idsatp
KVDD= ───────
(VDD – Vth)α
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 3434
Power-Delay ProductPower-Delay Product
VDD3
Power × Delay = constant × ─────── (VDD – Vth)α
0.6V 1.8V 3.0V VDD
Power
Delay
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 3535
Optimum Threshold VoltageOptimum Threshold Voltage
For minimum power-delay product:
3VthVDD = ───
3 – α
For long channel devices, α = 2, VDD = 3Vth
For very short channel devices, α = 1, VDD = 1.5Vth
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 3636
LeakageLeakage
IG
ID
Isub
IPT
IGIDL
n+ n+
GroundVDD
R
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 3737
Leakage Current ComponentsLeakage Current Components
Subthreshold conduction, Subthreshold conduction, IIsubsub
Reverse bias pn junction conduction, Reverse bias pn junction conduction, IIDD
Gate induced drain leakage, Gate induced drain leakage, IIGIDLGIDL due to due to
tunneling at the gate-drain overlaptunneling at the gate-drain overlap Drain source punchthrough, Drain source punchthrough, IIPTPT due to short due to short
channel and high drain-source voltagechannel and high drain-source voltage Gate tunneling, Gate tunneling, IIGG through thin oxidethrough thin oxide
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 3838
Subthreshold LeakageSubthreshold LeakageVgs – Vth
Isub = I0 exp( ───── ), where vT = kT/q = 26 mV n vT at 300K
0 0.3 0.6 0.9 1.2 1.5 1.8 V Vgs
Ids
1mA100μA10μA1μA
100nA10nA1nA
100pA10pA
Vth
Sub
thre
shol
dre
gion
Saturation region
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 3939
Normal CMOS InverterNormal CMOS Inverter
Polysilicon (input)SiO2
p+ n+ n+ p+ p+ n+
n-well p-substrate (bulk)
metal 1VDDGND output
input output
VDD
GND
o
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 4040
Leakage Reduction by Body BiasLeakage Reduction by Body Bias
Polysilicon (input)SiO2
p+ n+ n+ p+ p+ n+
n-well p-substrate (bulk)
metal 1VDDGND output
input output
VBBp
VDD
GNDVBBn
VBBn VBBp
o
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 4141
Body Bias, Body Bias, VVBBnBBn
+-0 < Vg < Vth
+ + + + + + + + + +
+ + + + + + + + + + + + +
+ + + + + + + + + + + + +
Depletion region
Polysilicon gateSiO2
p-type body
+-Vg < 0
- - - - - - - - - - - - - - - - - - + + + + + + + + + + + + ++ + + + + + + + + + + + ++ + + + + + + + + + + + ++ + + + + + + + + + + + +
Polysilicon gateSiO2
p-type body
Vt is a function of:Dopant concentration,Thickness of oxide
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 4242
Further on Body BiasFurther on Body Bias
Large body bias can increase gate Large body bias can increase gate leakage (leakage (IIGG) via tunneling through oxide.) via tunneling through oxide.
Body bias is kept less than 0.5V.Body bias is kept less than 0.5V.For For VVDDDD = 1.8V = 1.8V
VVBBnBBn = - 0.4V = - 0.4V
VVBBpBBp = 2.2V = 2.2V
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 5ELEC6270 Fall 07, Lecture 5 4343
SummarySummary Device scaling down reduces supply Device scaling down reduces supply
voltagevoltageReduced powerIncreases delay
Optimum power-delay product by scaling Optimum power-delay product by scaling down threshold voltagedown threshold voltage
Threshold voltage reduction increases subthreshold leakage power
Use body bias to reduce subthreshold leakage Body bias may increase gate leakage