elec-7250 vlsi testing
DESCRIPTION
ELEC-7250 VLSI Testing. Scan Design Implementation on ISCAS ’89 Benchmark Circuits – s1423 and s1512 Completed by: Jonathan Harris. PI’s. PO’s. Combinational Logic. Scan In. PO or Scan Out. O 1. dff 1. dff 2. dff n. D Q. D Q. D Q. O 1. O 1. O 1. Clock. Scan Mode. - PowerPoint PPT PresentationTRANSCRIPT
ELEC-7250 VLSI TestingELEC-7250 VLSI Testing
Scan Design Implementation on ISCAS ’89 Benchmark Circuits – s1423 and s1512
Completed by:
Jonathan Harris
What is Scan Design?What is Scan Design?
00110011
00101011 PO or Scan Out
Combinational Logic
PI’s PO’s
O
1
O
1
O
1
O
1
Scan In
Clock
D Q
dffn
D Q
dff2
D Q
dff1
Scan Mode
Scan Design – Pros & ConsScan Design – Pros & Cons
Disadvantages Gate and area
overhead Performance penalty –
2 gate delays Long test application
time
Advantages High Fault Coverage Minimal Test
Generation Time Easily Automated
s1423 and s1512s1423 and s1512s1423 s1512
# Primary Inputs 17 29
# Primary Outputs 5 21
# Gates 557 780
# Flip-Flops 74 57
% Scan Overhead 22.8% 16.9%
Scan Design ResultsScan Design ResultsTotal
Faults
Undet.
Faults
Fault
Coverage
# Gates
Test
Time
(min)
circuit
s1423
w/o scan 1663 946 47.78% 731 19
pseudo-scan 1663 27 98.38% 731 32
full scan 2131 27 98.73% 1027 726
circuit
s1512
w/o scan 1411 1364 22.86% 837 14
pseudo-scan 1411 68 95.18% 837 23
full scan 1761 68 95.14% 1025 487
Project Demo and QuestionsProject Demo and Questions