electronic devices in mtl annual report 2001

8/2/2019 Electronic Devices in MTL Annual Report 2001

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Electronic Devices


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Double-Gate MOS Transistor with Self-Registration

Optimal MOSFET Design for Low Temperature Operation

Experimental Investigation of Carrier Velocity and Mobility in Deeply Scaled NMOS

SiGe CMOS Design

SiGe Heterostructure Field Effect Transistors

CMOS Technology for 25 nm Channel Length

Understanding Mobility Behavior in Strained Si MOSFETs

Strained Si/SiGe-on-Insulator (SGOI) RF Power MOSFETs

Hydrogen Degradation of GaAs and InP High Electron Mobility Transistors

Automatic Small-Signal Model Extraction for RF-LDMOSFETs on SOI

RF Power SOI LDMOSFETs for System-On-Chip Applications

Magnetic Random Access Memories (MRAMs)

Magnetic Nanostructures Made by Block Copolymer Lithography

Vertical MOSFET fpr Field Emission Applications

Field Emitter Array Flat Panel Displays for Head-Mounted Applications

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Electronic Devices

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The double-gate MOSFET is considered the mostpromising candidate to circumvent the scaling lim-its of bulk CMOS devices. In order for the double-

gate MOSFET to exhibit its inherently ideal featuressuch as approximately twice current per unit width,enhanced transconductance, ideal subthreshold swing,and short-channel effect immunity, it should satisfyseveral criteria, namely : 1) perfect top-to-bottom gatealignment, 2) very thin uniform undoped Si chan-nel, 3) source/drain extension structure to enablehigh doping, as well as thick source/drain structureto reduce the series resistances, 4) control of spacerlength to reduce gate to source/drain overlap capaci-tance while maintaining proper current drive, 5) suit-able process integration for a higher dimensional ICimplementation. Such a device structure has not been

yet developed. In this work, we propose a double-gateMOS transistor with self-registration (DGSR). The keyfeatures of DGSR are i) a top-to-bottom gate self-regis-tration device structure , where the spacers in the top-to-bottom are self-aligned, and the alignment accuracyof the top-to-bottom gate is determined by the dif-ference in spacer thickness ; ii) a thick source/drainstructure using a reverse active patterning ; iii) aneasy doping control of source/drain extension regionsby ion implantation onto those regions just after gateformation as well as an easy control of spacer length.Also the device fabrication process has been designedto avoid novel processing techniques so that it can be

ready to be integrated into a standard CMOS process,and it has also been designed to be suitable for a high-er dimensional IC integration.

Shown below in Figure 1 is a schematic of key processsteps used to realize the DGSR MOSFET. Fabricationstarts with formation of the bottom-gate stack on anSOI wafer. Then the source/drain regions are ionimplanted. After LTO/poly spacer formation, the bur-ied oxide is etched to make a top-to-bottom gate self-

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Double-Gate MOS Transistor with Self-Registration

PersonnelD. Song (D. A. Antoniadis)

SponsorshipDARPA

Continued

Fig.1


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as a hard etch-mask. To realize a thick source/drainstructure, a reverse active patterning technique is usedfollowed by removal of the residual poly spacer, thin

nitride deposition, and LTO deposition and oxide CMPfor planarization. Poly deposition, poly CMP, poly etch-back, and ion implantation into source/drain regionsfollowed by wet etching of the oxide and nitride com-plete the thick source/drain structure. It is interesting tomention that at this process step, the formation of inter-connection levels to either a higher dimensional integra-tion or a single gate MOSFET for the characterizationof process quality as well as electrical device charac-teristic can be made. The SOI wafer with polished LTOis bonded to a handle wafer with thermal oxide, andthe SOI substrate and buried oxide are removed. Thinsacrificial oxide growth is followed by nitride spacer

formation, and the thin oxide is removed. By top gateoxide growth, top gate poly deposition, top gate polyCMP and etch-back, and ion implantation for top gateas well as source/drain regions, the device structure ofthe DGSR MOSFET is completed with the subsequentformation of interconnection levels.

Low temperature operation of MOSFETs improves theirperformance by increasing the mobility and by allowinglower threshold voltages. The goals of this project are

to understand how to achieve an optimal device designat low temperature and how much performance gainoccurs at low temperature. A set of devices from IBMwhich have two different threshold voltage designs (alow-Vth design and a high-Vth design) were usedto examine two design options. Since a devices switch-ing speed depends on both current and capacitance, thetwo designs were compared at the same channel length(approximately the same gate capacitance) allowingthe on-current of the devices to give a direct measureof device switching speed. Also, in order to make afair comparison, a forward substrate bias was used toadjust the off-current of all devices to the same value

(10-9 A/m). A large forward bias can be used, with noimpact on the off-current, because the source and drainp-n junction current is significantly reduced at low tem-perature.

Plotting each devices on-current versus channel length(Leff ) clearly shows that the low-Vth design consistentlyyields a higher on-current for a given Leff (Figure 2) andsame off-current (Figure 2).

Examining device characteristics (again, at the substratebias needed to set the off-current), the low-Vth deviceshave a steeper subthreshold slope than the high-Vth

devices (Figure 3 middle) which, given the fixed off-current, results in a lower Vth (Figure 3 top) and thus ahigher on-current. The low-Vth designs also have lessshort channel effects as evidenced by their lower draininduced barrier lowering (DIBL) at a given Leff (Figure3 bottom).

The differences in subthreshold slope and short chan-nel effects are directly related to the maximum deple-tion depth in the channel (xd,max). For instance, asmall xd,max gives a larger (shallower) subthresholdslope, but better short channel effects. In this

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Optimal MOSFET Design for LowTemperature Operation

PersonnelK. M. Jackson(R. Dennard IBM, D. A. Antoniadis,H. Smith)

SponsorshipIBM, Intel (Intel Fellowship)

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case, although the two device designs (at a given Leff) have the same off-current, the high-Vth design hasa smaller xd,max than the low-Vth design. This results

in the worse subthreshold slope which gives a higherVth and thus a lower on-current. What this suggests isthat designing for a low threshold voltage requires bothreaching the maximum off-current allowed, as well asminimizing the subthreshold slope by having as large axd,max as allowed by short channel effects limits.In summary, the optimal design of a MOSFET at lowtemperatures requires the use of a low threshold volt-age. A low Vth with the proper xd,max (balancing thesubthreshold slope and short channel effects) is bestachieved by using a lower channel doping, than a roomtemperature device, coupled with a forward substratebias. The experimental results above for 80 nm N-

MOSFETs at 200 K show the low-Vth design achieving a5% higher on-current (for the same off-current) than thehigh-Vth design. Continuing work is focusing on quanti

fying the origins of the performance gains across designand versus temperature.

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TotalDIB

L(mV)

SS(mV/dec)

Vtha

tVdd(V)

Continued

Fig. 3: Device parameters at the substrate bias that givesan Ioff=10

-9 A/m.Fig. 2: On-current vs. Leffat Ioff=10-9 A/mm

Leff (nm)

Low-Vth design

Low-Vthdesign

Low-Vthdesign

Low-Vthdesign

High-Vthdesign

High-Vthdesign

High-Vthdesign

High-Vth design

Leff (nm)

200 K, Ioff =10-9 A/m

200 K, Ioff =10-9 A/m

Ion(

mA/m)


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Fig. 4: Ballistic efficiency (veff/ vq, where vq is the thermal veloc-ity of carriers in the source accumulation layer) for industrybulk NMOS technologies A and B, as well as for Monte-Carloresults for 25 nm Leff NMOS. Derived from measured effectivevelocities, plus estimates for vinj. The decrease in veff from Bto A may be mainly due to a decrease in mobility; this maybe due to heavier channel doping necessary to suppress short-channel effects, as well as to increased scattering associated withultra-thin oxides.

Continued success in scaling bulk MOSFETs hasbrought increasing focus on fundamental performancelimits. Drain current is limited by carrier velocity (veff);

the theoretical limit to carrier velocity is the rate atwhich carriers can be thermally injected from the sourceinto the channel. This thermal limit is equivalent tofully ballistic transport. In this work we investigate thephysical meaning of different MOSFET carrier velocityextraction methods, in order to measure appropriatelyhow close to the thermal limit a modern MOSFET oper-

ates. Applying our findings to two advanced industryNMOS technologies, we experimentally set an upperbound on the thermal or ballistic efficiency . Figure 4

summarizes these results: we find that a deeply-scaled(Leff < 50 nm) 1V NMOS technology operates, at most,at 40% of the limiting thermal velocity. In addition, wesee no indication that bulk NMOS scaling will bring uscloser to this limit.

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Experimental Investigation of Carrier Velocity and Mobility in DeeplyScaled NMOS

PersonnelA. Lochtefeld (D. A. Antoniadis)

SponsorshipDARPA

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Improving the ballistic efficiency of deeply-scaledMOSFETs may require strategies for enhancing car-rier mobility, such as strained-Si channels, or undoped

thin-film SOI (Silicon-on-Insulator). However, therelationship between low-field effective mobility (eff)and high-field carrier velocity is not well understoodfor deep-sub-100 nm MOSFETs, where the lateral elec-tric field is far in excess of Esat (which corresponds tovelocity saturation in isotropic field regions). We haveinvestigated this experimentally by mechanically induc-ing uniaxial strain, via a four-point bending apparatus,on the above-mentioned 1V NMOS technology. AsFigure 5 shows, shifting eff in a long-channel deviceby 13% corresponds to a velocity shift in a short-chan-nel device of 4%. However, uniaxial strain appears toeffect short devices (which have higher average chan-

nel doping, due to non-uniform lateral doping profilesassociated with halos) differently then long devices.Preliminary results suggests that shifting eff in a short-channel device (Leff < 50 nm) by just 5% corresponds toa velocity shift (in the same device) of 3%.

This study investigates possible substrate options thatcan be used for SiGe CMOS design. CMOS devicesfabricated on SiGe substrates offer a practical means of

extending the scaling of Si devices since it is silicon pro-cess compatible and allows for strained layers resultingin enhancement of electron and hole transport. Onepossible substrate shown in Figure 6 has been studiedby Rim et. al at IEDM 1998.

Transport in this structure occurs in the strained siliconlayer at the top. The layer is under biaxial tensile strainsince the lattice constant of germanium is larger thansilicon. It was demonstrated that NMOS devices builton this substrate exhibit enhanced electron mobility fora wide range of vertical fields but that PMOS devicessuffered a degradation of enhancement for vertical elec-

tric field greater than 1.15 MV/cm resulting in furtherimbalance of PMOS and NMOS devices warrantinga study of alternative substrates. Possible substrateswhere analyzed by performing electrostatic simulationsusing MEDICI.

One possible substrate shown in Figure 7 below com-bines a biaxial compressive layer giving enhancedhole mobility with a biaxial tensile strained layer forenhanced electron mobility.

The hole concentration can be made to be confinedto the hole layer for a proper bias voltage due to the

valence band discontinuity between Si0.2Ge0.8 and thestrained-silicon. The electron population is concen-trated in the strained-silicon layer due to the proximityto the surface and the conduction band discontinuity ofstrained-silicon and Si0.2Ge0.8. The substrate has prom-ising potential for improving electron and hole trans-port, but the electrostatic integrity is poor as shownbelow in Figures 8 and 9 that show higher subthresholdslopes, SS.The SS increases due to a large hole concentration inthe buried compressive layer that results in a weaken-

75

SiGe CMOS Design

PersonnelH. Nayfeh (D. A. Antoniadis, J. L. Hoyt)

Fig. 5: Shift in long-channel mobility vs. shift in short-channel veloc-ity, induced via uniaxial strain applied to technology A (see table,Figure 4).

SponsorshipSRC, DARPA

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ing of the top-gate control of the electron charge. A larg-er Ge concentration is also simulated so as to increasethe hole charge. The result is that the SS is larger dem-

onstrating the effect of the hole well. Figure 10 belowshows the band structure and charge concentration atsubthreshold for the NMOS device.

The PMOS SS is degraded from 73 mV/dec to 100mV/dec. To understand this, the formula for the subthresh-old slope is n*60mV/dec where n is an ideality factorthat is 1+Cs/Cgc, where Cs is the semiconductor capac-itance at subthreshold and Cgc is the gate to channelcapacitance in inversion. The ratio of Cs to Cgc is largerfor the buried hole well structure than the surface chan-nel device due to hole charge modulation in the wellreducing the Cgc capacitance and as a result increasing

the ideality factor.It is apparent that to improve the NMOS subthresholdcharacteristics the hole well below the electron well

needs to be removed. A substrate that removes the holewell is shown below in Figure 9. The NMOS devicearea is achieved by selectively etching the top layers

so that the buried hole is removed resulting in deviceswith the same electrostatics as the bulk-Si counterpart.

However, the PMOS to no surprise has a degraded SSfor a Ge fraction of 60% in the buried layer. The PMOSelectrostatics will improve by reducing the hole popula-tion in the hole well by reducing the Ge concentrationsince the valence band discontinuity is reduced. Thisindicates that a compromise between electrostatics andcurrent drive improvement is needed since mobilityenhancement increases with strain. Analysis is current-ly underway to determine the optimum layer structure.

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Continued

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Fig. 6: Strained -Silicon CMOS substrate. Fig. 7: Compressive and tensile strained layer subtrate.


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Continued

Fig. 8: (Left) Degraded NMOS SS. (Right) Degraded PMOS SS

Fig. 9: Band structure and charge concentation at subthreshold forthe NMOS device.

Fig. 10: Substrate with hole well removed.

Bulk-Si 60% Ge 80% Ge 80% GeSSmV/dec Bulk-Si

Large HoleConcentration

Hole WellElectron Well


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We are exploring mobility enhancements in hetero-structure MOSFETs grown on relaxed SiGe virtualsubstrates. Such devices offer significant perfor-

mance improvement over bulk Si devices and can beintegrated into conventional Si MOSFET processingschemes. We have fabricated heterostructure MOSFETsvia a novel short-flow process with a deposited gateoxide and a single photolithography step. The effectsof strain and channel thickness on device mobilitieshave been investigated. In agreement with theoreticalpredictions, different mobility enhancement satura-tion behaviors are observed for strained Si n- and p-MOSFETs fabricated on relaxed SiGe virtual substrates.

By performing an intermediate CMP step on therelaxed SiGe layers, strained Si devices were fabricatedon virtual substrates of negligible surface roughness

for the first time. The mobility enhancements of thesedevices are virtually identical to those of devices onunplanarized SiGe substrates. The process stability ofstrained Si devices has also been studied. The effectsof Ge interdiffusion explain the mobility degradationof strained Si MOSFETs annealed at temperatures over1000oC. We are currently investigating MOSFETs fab-ricated on SiGe-on-insulator substrates, strained Gep-MOSFETs, and optimized heterostructures for SiGe-based CMOS.

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SiGe Heterostructure Field Effect Transistors

PersonnelM.T. Currie, C.W. Leitz, Z. Cheng, M.L. Lee (E.A. Fitzgerald and D.A. Antoniadis)

SponsorshipDARPA, Singapore-MIT Alliance, NSF/MRSEC

Fig. 11: Electron mobility enhancement of strained Si n-MOSFETs as a function of channel thickness. Poor confinement degrades the mobilityof the thinnest channels. The slightly relaxed thickest channels exhibit no mobility degradation

PoorConfinement


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The double-gate (DG) MOSFET (Figure 12) is consid-ered a promising device for CMOS scaling to deep sub-100 nm gate lengths. However, realization of the ideal

DG-MOS structure involves significant technologicalchallenges: formation and alignment of gates above andbelow a thin single-crystalline silicon layer, and achiev-ing low source/drain resistance for this thin layer. Weare addressing these issues though integration of threeprimary technologies: wafer bonding with pre-pat-terned features, interferometric alignment, and selectiveepitaxy.

Monte-Carlo modeling predicts that double-gateddevices that are scaled to Leff = 25 nm will have trans-conductances Gm in excess of 2000 mS/m, whilemaintaining almost perfect sub-threshold slope.

However, models also predict that the tolerance inaligning front and back gates has to be within Lg/4in order to avoid performance deterioration due tooverlap capacitance. The Lg/4 requirement translatesinto 6 nm alignment tolerance for a 25 nm channel. Inorder to meet this alignment challenge we will use theIBBI (Interferometric Broad-Band Imaging) alignmenttechnique which achieves sub-nanometer misalignmentdetectivity. The planar double-gate devices will befabricated starting with a SIMOX wafer. First the gatestack for the back-gate will be deposited and patternedby x-ray lithography. The structure will then be coveredby a layer of CVD oxide, planarized, and bonded to

a handle wafer. The bulk of the SIMOX wafer willthen be chemically etched using the back-oxide of theSIMOX wafer as the etch-stop. The fabrication will thenfollow a conventional SOI (Silicon on Insulator) pro-cess, with front gate precisely aligned to back-gate layerusing the IBBI alignment scheme. The final structure isdepicted in Figure 12.

We employ a direct alignment approach to form top-gates with correct relative placement to the bottom-gates. We have demonstrated the functionality of this

alignment system. Figure 13 shows a DG-MOS deviceafter top-gate x-ray lithography, with buried n+ polygate visible beneath a 25 nm silicon layer. Although

we have attained alignment detectivity of the order ofseveral nanometers, final alignment results are equallya function of precise pattern placement between theupper-and lower-gate x-ray masks. We have been devel-oping a process to obtain this precision through closeproximity x-ray mask replication. In this scheme, gatepatterns from the upper-gate mask are transferred to thelower-gate mask using x-ray lithography. This is donewhile the alignment marks of the two masks are aligned.Lithography of this sort is challenging primarily for tworeasons: 1) the pattern on the replicated mask must be ofthe same polarity as that on the source mask, 2) it is nec-essary to maintain sub-100 nm resolution. Maintaining

pattern polarity is a subtle yet crucial aspect of this pro-cess. Recently we have succeeded in developing a maskreplication process compatible with these constraints.The process that takes place on the duplicate maskinvolves the following four steps : X-ray patterning posi-tive resist, liftoff (yielding a pattern reversal), etch down(forming trenches) and finally, Au electroplating withinthose trenches. Once these steps are accomplished,mother and daughter masks have precisely matchingpatterns when the two masks are compared face-to-face. This is a key result for this project.

We are also investigating performance of deeply scaled

DG vs. bulk MOS. It has been projected that withaggressive channel dopant profile engineering, bulkmay scale down to ~25 nm Leff which may be near thepractical DG-MOS limit. However, to achieve this thebulk MOSFET must have very heavy (~1x1019 cm-3)peak body doping to suppress punch-through, whichresults in a very high transverse electric field (Eeff)at the inversion layer. According to the well-verifieduniversal mobility relationship, this can be expected toresult in severely degraded mobility in bulk MOSFETs.In SOI devices with undoped channels, short channel

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CMOS Technology for 25 nm Channel Length

PersonnelA. Lochtefeld, M. Meinhold, D. A. Antoniadis and H. I. Smith

SponsorshipDARPA and ONR

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effects are suppressed by limiting silicon and oxide filmthicknesses. Body charge can be essentially zero, result-ing in low Eeff and correspondingly superior mobility.

Using 2D numerical simulations (Avant! MediciTM) wehave determined the doping required for electrostatical-ly sound bulk uniform-doped n-MOSFETs (at the Leff =50 and 25 nm generations), as well as the resulting Eeffseen by electrons in the inversion layer. In Figure 14we show the corresponding range of mobility expected,based on the universal dependence of mobility on Eeff.Also shown are results for one additional bulk, and

three SOI, MOSFET architectures. Our results suggestthat single-gate SOI is an attractive alternative down to50 nm Leff. For deeper scaling, double-gate SOI should

have a 3-4X mobility advantage over aggressivelydesigned bulk NMOS.

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Fig. 13: DG-NMOS device after top-gate x-ray lithography.Alignment of gates is via IBBI.

Fig. 12: Double-gate (DG) NMOS transistor with 25 nm effectivechannel length. Gate-to-gate alignment is via IBBI.

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An attractive method to enhance MOSFET performanceis to alter the bandstructure of silicon to improve thecarrier transport properties. This can be achieved by

inducing biaxial tensile strain in the silicon channel.For example, epitaxial growth of 10 nm-thick layers ofsilicon on relaxed SiGe (20% Ge) will provide sufficientstrain in the silicon. Recent results on the applicationof these concepts to silicon MOSFETs indicate signifi-cant strain-induced performance enhancements at agiven channel length, in the deep sub-micron regime.Understanding the mobility enhancement mechanismis important for determining the ultimate performancelimits of these devices.

In this project, we begin by studying issues related tothe electron mobility in strained Si MOSFETs. One

method of understanding the mechanism of mobil-ity enhancement is to study the vertical effective fielddependence of the mobility as a function of tempera-ture. For high vertical fields (>1 MV/cm), it is antici-pated that surface roughness scattering will dominatetransport. The impact of strain on surface roughnessscattering is not understood at this time. Lowering themeasurement temperature reduces the phonon com-ponent of scattering, and thus enables us to observethe remaining mobility terms, which include Coulomband surface roughness scattering, in strained andunstrained Si devices.

Strained Si n-MOSFETs (20% Ge) and unstrained Sicontrol wafers with similar doping profiles were fabri-cated by K. Rim (Ph.D. thesis, Stanford). Our prelimi-nary measurements at room temperature are illustratedin Figures 15 and 16. Figure 15 shows split-CV datawhich is used to obtain the inversion charge, Qi, whichis required for the extraction of the effective mobilityueff = (L/W)gD/Qi. The lines in Fig.16 illustrate themobility we have measured for strained Si n-MOSFETs,and unstrained Si controls, at room temperature.

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Understanding Mobility Behavior inStrained Si MOSFETs

PersonnelG. Xia ( J. L. Hoyt )

SponsorshipSRC and IBM Corp.

Continued

Continued

Fig. 14: Universal effective MOSFET mobility curves from [2], withregions of operation delineated for five different bulk and SOI devicearchitectures. Figure 14a corresponds to the 50 nm Leff generation,and Figure 14b to the 25 nm generation. DG-Fmg refers to double-

gate SOI with midgap gate workfunctions. DG-n+p+ refers todouble-gate SOI with asymmetrical n+/p+ poly gates. For each devicearchitecture the range of Eeffis determined from 2D simulation,and corresponds to a range of inversion layer densities (Qinv) from

0.8x1013 to 1.2x1013 cm-3.


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The dashed line is the room temperature universalNMOS mobility (S. Takagi, et al., IEEE Trans. ElectronDevices,Vol. 41 p. 2357, 1994). The symbols show the

77K NMOS mobility for the strained Si devices, illus-

trating a significant enhancement compared to the uni-versal MOS mobility at that temperature.

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Fig. 16: Measured effective mobility versus vertical effectivefield for strained Si and unstrained Si control n-MOSFETs,at room temperature (lines). Symbols show the 77K data forstrained Si and the universal MOS mobility curve.

Fig. 15: Split-CV measurements of a strained Si n-MOSFETat room temperature.

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The rapid growth in wireless communication productsin recent years has driven the development of RF tech-nology. The implementation of the power amplifier

function of these systems in the intermediate frequencyrange of 5-20 GHz has predominately been fulfilledby GaAs technology. Advancements in SiGe HBT mayallow performance of up to 10 GHz depending on thepower level of the application, but as of yet there isno current prospect for Si-based technology to operatein the >10 GHz range. This project pursues emergingstrained Si/SiGe MOSFET technology to develop highperformance RF power devices that can operate in the10-20 GHz range at power levels of 100s of mWs. Sucha device will rival the performance of GaAs technologybut at a lower cost and with the potential for system-on-chip integration.

The basis for the superior performance of strainedSi/SiGe MOSFET technology is that it exhibits anenhancement in the fundamental transport properties

of Si resulting in improved device speed and powerdissipation. The stress induced by the lattice mismatchbetween a thin layer of epitaxially grown Si on arelaxed SiGe buffer layer induces a strain that results inimproved carrier transport through the thin Si film forboth holes and electrons. Recent experimental work hasshown increases of up to 80% in the low field mobilityof n-MOSFETs. The incorporation of an insulator layerunderneath the stack (as in SOI) offers the further ben-efits of lower capacitance and power dissipation.

A cross section of the proposed initial device struc-ture is shown in Figure 17. An LDMOSFET design is

used. The main features of the device are the lightlydoped drain which enables a high breakdown voltage

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Strained Si/SiGe-on-Insulator (SGOI) RF Power MOSFETs

PersonnelN. Waldron (J. del Alamo)

SponsorshipDARPA

Continued

Fig 17: Schematic cross section of proposed strained-Si RF-power LDMOSFET. Inset shows the epitaxial layer structure


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and the graded body doping profile which results in ahigh transconductance. These two key features impactthe trade off between the cut-off frequency fT and

breakdown voltage of the device. A P+

body contact isincluded to counteract floating body effects. The con-stituent layers of the epitaxial stack are also shown. Theepitaxial structure consists of a SiGe relaxed buffer layeron top of which the thin strained-Si layer is deposited.This thin Si layer forms the active region of the devicewhere the channel inversion layer is created. The gateoxide is grown on the strained-Si layer and the entirestack sits on a buried oxide forming what is termed anSGOI (Strained Si/Ge on Insulator) structure. The SGOIsubstrate is prepared by means of a Smart Cut processdeveloped at MIT.

A simulation platform which will allow for designoptimization is currently being developed using theMEDICI device design CAD tool. This modeling envi-ronment will be used to gain an understanding of theperformance benefits/tradeoffs of various epitaxiallayer structures. While strained Si/SiGe processing isentirely compatible with traditional CMOS fabricationtechniques, it does present some potential technologi-cal challenges particularly for RF power applications.Therefore identification and evaluation of the key criti-cal processing steps such as isolation, gate oxide forma-tion and body doping drive in is presently ongoing.

GaAs and InP High Electron Mobility Transistors

(HEMTs) hold promise for ultra-high-speed photonicsand millimeter wave power-applications. A major reli-ability concern in some of these devices is the shift of

the threshold voltage that is observed when the devicesare exposed to hydrogen. This can result into circuitmalfunction. The goal of this project is to understandthis reliability problem and find device level solutionsto mitigate it.

Recent research at MIT has shown that H exposureresults in the formation of TiHx in Ti/Pt/Au gates.This produces compressive stress in the gate, whichgenerates a tensile stress in the heterostructure under-neath. The resulting piezoelectric polarization chargein the semiconductor causes a threshold voltage shift.The reported experimental values of these shifts in InP

HEMTs and GaAs PHEMTs seem contradictory. ForGaAs PHEMTs, DVT is always positive and increasesas the gate length, Lg, is reduced. In contrast, for longgate length InP HEMTs, DVT is negative and increasingin magnitude with decreasing Lg. At a certain Lg, how-ever, there is a sign turn around and H-induced DVTbecomes positive.

In this project, we are developing a model for H-induced piezoelectric effect in InP and GaAs HEMTsthat explains this peculiar behavior of DVT and pro-vides design guidelines for minimizing H sensitivity.Our modeling approach involves: i) performing two-

dimensional mechanical stress simulations in typicalheterostructures, ii) computing the resulting piezo-electric charge, and iii) estimating its effect on VT. Thefigure shows the piezo-electric charge distribution thatis induced in an InP HEMT by an expansion of its 1mm gate. This calculation framework provides resultsthat are consistent with the experimental measurementsand illuminate the key dependencies of DVT on hetero-structure design. They also explain the fundamental dif-ference between GaAs and InP HEMTs.

84

Hydrogen Degradation of GaAs and InPHigh Electron Mobility Transistors

PersonnelS.D. Mertens (J.A. del Alamo)

SponsorshipNTT, HRL

Continued

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RF-power LDMOSFETs on SOI have great potential forsystem-on-chip integration. The use of SOI also resultsin lower parasitics and improved power efficiency.

For a device designer, it is important to understandhow each element of a device influences its perfor-mance. For RF power MOSFETs, for example, the gateresistance is a very important parasitic and needs tobe minimized. We have set up an infrastructure toautomatically extract a small-signal equivalent-circuitmodel of RF-power LDMOSFETs. This has allowed usto isolate the influence of each model element and toevaluate the impact of changes in device design on per-formance.

To build a small-signal equivalent-circuit model that

matches measured S-parameter data, it would be a poorstrategy to fix the equivalent-circuit topology and thensimply to try to optimize all parameter values. Thisis because of the large number of variables involved.Also, conventional equivalent-circuit model topolo-gies optimized for bulk devices might not be suitablefor SOI. Instead, our approach is to start with the mostintrinsic model of a MOSFET, which captures the coredevice behavior, and then, once optimized, add newelements one by one with a strict sense of priority. Itis very important, however, that every element that isadded is physically meaningful.

For our SOI LDMOSFETs, we started with the verybasic intrinsic model, indicated in Figure 19. The valueof all elements of this model was derived from experi-mental Y-parameters. After this, the program tried allpossible element additions and choose the one thatgave the best improvement in the data fit. Several ofthese cycles of adding one element and optimizing fol-lowed, until the degree of improvement fell below athreshold at which the program stops. Figure 20 showsthe result. As one can see, not only does the modelmatch the experimental Y-parameter data very well,

85

Automatic Small-Signal ModelExtraction for RF-LDMOSFETson SOI

PersonnelJ. Scholvin, J.G. Fiorenza (J.A. del Alamo)

SponsorshipSRC

Continued

Continued

This work will allow us to better understand theimpact of layer structure and gate design on the H-

induced VT shift in GaAs and InP HEMTs. Our ultimategoal is device design guidelines that minimize the Hsensitivity of these devices.

Fig. 18: Relative 2D piezoelectric charge distribution in a 1 mm InPHEMT stressed by an expanding gate. Only half of the device issimulated, as the other half shows a symmetric charge distribution.


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understanding the connections between device designand device operation.

86

Fig. 20: Measured (solid) and simulated (dashed) Y-parameters of a 1 mm wide RF-power SOI LDMOSFET.

Fig. 19: Automatically derived small-signal equiva-lent circuit model for RF-power SOI-LDMOSFET.Rg captures the gate resistance and the Cdsub-Rdsubnetwork represents substrate parasitics. The intrinsicmodel is marked by the box.

Continued

but the selected elements also capture all the importantparasitics associated with the substrate and gate.The approach demonstrated in this work will be instru-

mental in developing accurate device models and in


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Our research focuses on the development of a transis-tor technology for the RF power amplifiers of futuregenerations of highly integrated wireless communica-

tion systems. We have developed an SOI (Silicon-on-Insulator) LDMOSFET (Laterally Diffused MOSFET)which is optimized for RF power amplifier applicationsand which is fabricated with a technology that permitsits integration with CMOS into a single-chip wirelesssystem.

A cross-section of the RF SOI LDMOS device that wehave fabricated is shown in Figure 21. The device is aMOSFET that features several enhancements to give itsuperior RF power performance. To enhance its gainthe body doping of the device is laterally graded. Thelightly doped n-type drift region, combined with a

body contact under the source, increases the devicesbreakdown voltage and its power handling capability.The insulating buried oxide layer reduces the parasiticdrain capacitance and improves its high frequency

power gain as well as the isolation between differentdevices on the same substrate. The device fabricationprocess has been designed to avoid exotic processing

techniques so that it will ultimately be possible to inte-grate the power device process into a standard digitalSOI CMOS process.

We have demonstrated that the performance of SOILDMOSFETs can meet or exceed the performance ofbulk silicon LDMOSFETs, which are widely used todayin PA applications. Figure 22 shows the gain and effi-ciency of the devices as a function of the input power.Included in the figure are both SOI LDMOSFETs andbulk silicon LDMOSFETs that were fabricated in paral-lel using an identical process. The power efficiencyof the SOI device exceeds the performance of the bulk

device. Our research has shown that the origin of thisis reduced interconnect and contact pad loss on the SOIsubstrate.

In summary, the RF SOI LDMOSFET is a promising

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RF Power SOI LDMOSFETs for System-On-Chip Applications

PersonnelJ. G. Fiorenza (J. A. del Alamo)

SponsorshipSRC

Continued

Fig. 21: An RF Power LDMOSFET on SOI


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technology for RF power amplifiers in future genera-tions of highly integrated wireless systems.

MRAMs are solid-state non-volatile magnetic stor-age devices in which each bit of data is stored an asmall, elongated magnetoresistive sandwich ele-

ment. A typical magnetores istive (MR) sandwichconsists of two magnetic layers of different coercivity,one hard and one soft.

The direction of magnetization of the hard layer is usedto represent the data bit. To write data, a magnetic fieldis applied by passing a current through a conductorline (word line) adjacent to the element, such that thefield is large enough to change the magnetization of thehard layer. To read, a smaller current is passed, whichcan change the magnetization of the soft layer only. Theresistance of the element depends on whether the hardand soft layers are magnetized parallel or antiparal-

lel, hence changes in the resistance resulting from thereversal of the soft layer can be used to probe the mag-netic state of the hard layer. Elements are arranged in arectangular array and connected with conductor lines,allowing individual elements to be selected.

We have used interference lithography combined withreactive ion etching and ion-milling to produce arraysof Co/Cu/NiFe spin-valve elements and prototypeMRAM structures. The aim of this research is to investi-gate the behavior of sub-100 nm elements, much small-er than those used in present-day MRAM devices.

To tailor the properties of the pseudo spin valve (PSV)elements for MRAM devices, we analyzed the hystereticbehavior of large-area arrays of rectangular and ellipti-cal PSV dots. Rectangular dots of sub-100nm width withaspect ratios ranging from 1:1 to 1:10 were fabricated byexposing and etching a first grating into an SiO2-layer,and then spin-coating the sample with new resist andexposing a second grating of different period perpen-dicular to the first one. The hysteresis obtained from anarray of 80x140nm PSV dots exhibits two distinct steps,as shown in the Figure 23, corresponding to the separate

88

Magnetic Random Access Memories(MRAMs)

PersonnelC.A. Ross, H.I. Smith, B. Vogeli, F. Castano, M. Walsh,Y. Hao, S. Haratani, in collaboration with J.Q. Wang

SponsorshipTDK Corp., DARPA through U. of New Orleans

Continued

Continued

Fig. 22: RF Power Performance comparison between SOI and bulk-silicon LDMOSFETs fabricated at MTL.


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switching of the Co and NiFe layers. The switching ofthe two magnetic layers and their antiparallel alignmentat remanence leads to the conclusion that the layered

PSV-structure is preserved through the pattern transferprocess. Upon increasing the aspect ratio of the PSV-dots, the magnetic field at which the soft layer switchesto antiparallel alignment decreases and eventually thetwo magnetic layers align parallel at remanence, asrequired for MRAM devices.In Fig. 24, an MRAM structure is shown. The PSV ele-

ments are located where the horizontal word lines andthe nearly vertical sense lines intersect, sandwichedbetween the sense lines and a 30nm SiO2-insulation

layer. The buried PSV elements form a large-area arrayof 80x180nm PSV dots, as indicated by magnetic mea-surements. Their magnetic behavior is similar to that oflarge-area PSV-dot arrays of the same dimensions. Bothword and sense lines were found to be conductive.Block copolymers consist of polymer chains made from

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Continued

Fig. 23: Schematic of MRAM structure, which consists of an arrayof parallel sense lines and parallel word lines. The MR elements areconnected in series. Magnetic fields generated by currents passedsimultaneously through a sense line and a word line write the ele-ment at the intersection of the two lines. To read, resistance changesin the sense line caused by a smaller wordline current are measured.

Fig. 24: Hysteresis loop of an array of 80 nm x 140 nm elliptical par-ticles made of a Co/Cu/NiFe film. The steps in the loop correspond tothe separate switching of the NiFe and Co layers, which are coupled

antiparallel at remanence.

Fig. 25: Scanning electron micrograph of an arrayof PSV elements located at the intersection of thehorizontal word lines and vertical sense lines.


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a block-copolymer has been used as a lithographytemplate to ion-mill a thin magnetic film into a close-packed array of magnetic dots. Such materials are use-

ful for studying the thermal stability, switching behav-ior, and interactions between magnetic particles that aresmaller than can be obtained using conventional lithog-raphy techniques. They may also be useful in futuregenerations of storage materials such as flexible media.

90

two chemically distinct polymer materials. These canseparate to form small scale domains whose size andgeometry depend on the molecular weight of the two

types of polymer and their concentration. The domainshave a very uniform distribution of sizes and shapes.We have been using block copolymers as templatesfor the formation of magnetic particles, by selectivelyremoving one type of domain and using the resultingtemplate to form a nanostructured magnetic film. Thiscan lead to hexagonally close packed arrays of mag-netic dots or columns with diameters on the order of20 nm and periodicities of order 50 nm. As an example,

Magnetic Nanostructures made by Block Copolymer Lithography

PersonnelC.A. Ross, J. Cheng, H. I. Smith, collaboration with E.L. Thomas

SponsorshipNational Science Foundation through a Seed Grant from the MIT Center for Materials Science and Engineering

Fig. 25a: An array of Co dots, 8 nm thick and 20 nm in diameter, made by block-copolymer lithography. The array has acoercivity of about 100 Oe at room temperature.

200 nm


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As the pixel density of high-resolution electronic dis-play increases, there is a corresponding increase in theI/O data transfer rate necessary to address the display.

This ultimately reduces the row access time on the dis-play for a fixed scanning refresh rate. To alleviate thisproblem, active matrix addressing is used in currentdisplay technologies. However, the I/O data transferrate is still very high and leads to large power dissipa-tion in the addressing circuits and system drivers.

A proposed solution to this issue is the use of intelli-gent pixel arrays whereby an actively addressed pixelretains on/off information within the pixel betweenframe scans. This reduces the necessary refresh rateif the actively on or off pixel state does not need tobe modified on the subsequent picture frame. We are

proposing to construct a field emitter array with anintegrated transistor structure to form the basis of apixel latch sub-system. Using an additional transistorto isolate the pixel latch element from the display rowand column address lines, random addressing of eachpixel latch element is possible. An additional benefit ofan integrated transistor structure is stabilization of fieldemission current from the emitter arrays (FEA).

Using an integrated transistor structure, it is possible tomodulate the field emission current density by adjust-ing the vertical MOSFET (VMOS) gate voltage. Because

the VMOS is connected in series with the field emitterarray the gate voltage of the FEA is divided betweenthe drain to source voltage, VDS, and the gate to emit-ter voltage, VGE, of the FEA. This can be modeled as avoltage controlled current source with a floating drainvoltage for the VMOS device. The floating drain volt-age is then controlled such that the desired level ofemission current is produced.

Other approaches that have been proposed forMOSFET/FEA structures have used lateral MOSFETdesigns integrated with field emitter arrays. While thisis a very good device structure, higher packing density

and thereby greater display resolution can be achievedwith a vertically integrated MOSFET/FEA device. Thedevice can be constructed such that the same voltagecontrols the VMOS channel and field emitter gate.Initial investigations into VMOS simulation and fab-

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Vertical MOSFET for Field Emission Applications

PersonnelP. R. Herz (A. I. Akinwande)

SponsorshipDARPA

Continued

Fig. 26: VMOS doping profiles.

Drain

Gate

Source Source

DrainGate


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Continued

rication has been completed. The process design hasused vertically etched silicon pillars to create the VMOSstructure for testing and analysis. Figure 26 shows

VMOS source and drain doping profiles, indicatinggood agreement of simulation and experimental results.Top view SEM of the completed VMOS structure are

shown in Figure 27. There was some concern regard-ing feature topology and gate oxide integrity howeverdevice testing yielded encouraging results. VMOS cur-

rent-voltage characteristics were tested experimentallyand are shown in Figure 28, indicating clear transistorbehavior with a 2V threshold voltage and drive currentsof 5-10mA for a given VMOS array (100 transistors perarray).

Drain current vs. Drain voltage Drain current vs. Gate voltage

Fig. 28:VMOS experimental I-V characteristics.

Fig. 27: VMOS array. Fabricated device (top view).


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Advances in nanostructure technology have madefeasible small, high-resolution, high-brightness andhigh-luminous-efficiency field-emitter-array sources for

Head-Mounted Displays (HMDs). HMDs are expectedto have a variety of applications in military, medical,commercial and entertainment fields. The technologymost commonly used in deployed HMD systems is theCRT which is bulky, because of the use of a single elec-tron gun to generate images on a cathodoluminescentscreen, but has the most desirable attributes of highluminous efficiency, high brightness and easy imagerendition. However, the relay optics required for see-through HMDs become complicated because of thebulky nature of the CRT. For other applications, suchas entertainment virtual reality, the most commonlyused image source is the backlit Active-Matrix-Liquid-

Crystal Display (AMLCD), which is thin and has highresolution. Furthermore, the addressing electronics areintegrated on the same substrate as the image source.However, the backlit AMLCD image source does nothave sufficient brightness nor luminous efficiency tomake it suitable for application to see-through HMDs.

Our approach to demonstrating a small, high-resolu-tion, high-luminous-efficiency and high-brightness dis-play is the field-emitter-array Flat-Panel Display (FED)which incorporates a high-density, high-performancearray of low-voltage field emitters. CMOS-controlledelectron emission from the tips impinges on a cathodo-

luminescent screen. It is thus possible to integrate theaddressing and signal conditioning electronics on thesame substrate as the Field Emitter Arrays (FEAs). Themain advantage of this approach is the reduction ofthe number of wires and bond pads from about 2,000to about 50. For example, it will be difficult to attach >2,000 wires to bond pads in an area of 1.5" x 1.5" andobtain ultra-high vacuum in the display envelope.High resolution (>1000 dpi) FEDs are only possible ifthe addressing/driver and other signal conditioningelectronics are integrated on the same substrate as the

field emitter arrays.Our initial objective is to demonstrate the integrationof Si CMOS technology with low-voltage field-emit-

ter arrays fabricated using interferometric lithogra-phy. This project requires the fabrication of Si CMOSwafers with one or two levels of metal interconnect,followed by surface planarization using CMP technol-ogy. Interferometric lithography is then used to defineMo-cone field emitter arrays that are spaced 200 nmtip-to-tip and have


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Continued

A semi-automated Ultra High Vacuum (UHV) probechamber has been developed for the electrical char-

acterization of FEAs. This test bed allows the perfor-mance of the arrays to be evaluated without the lengthyoverhead of vacuum packaging devices. Device per-formance has been shown to be not only dependenton the device physical structure, but also on surfacecontamination that may have resulted during fabrica-tion and MEMS processing. The UHV probe chamberhas the capability to do device conditioning includingECR plasma cleans and wafer bake-out. The systemis designed to allow the future expansion to includesurface analysis chambers including a Kelvin Probe,Scanning Maxwell Microscope and Auger.

Electrical characterization of the 100 nm-apertureMolybdenum arrays (200 nm tip-to-tip spacing) hasshown that arrays can operate at voltages as low as16 volts and provide adequate current to support flatpanel display applications. We have demonstratedinitial testing of low-gate-voltage FEAs with discretesolid state devices. We replace the resistor that previ-ous approaches have used to limit and control emissioncurrent with a MOSFET. Current control is critical tothe uniformity of brightness across the display becauseFowler-Nordheim emission depends exponentially onthe ratio of the gate voltage to the tip radius-of-cur-vature (Vg/r). It is therefore very sensitive to small

changes in the radius-of-curvature. It was possible tocontrol the emitted current density using the gate volt-age of the transistor load. This may enable analog volt-age gray scale or temporal gray scale.

The above demonstration has gone a long way to showthe feasibility of high brightness, high-resolution FEAimage sources for head-mounted displays.


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Opposite Page:

Example of a ratchet potential. The particle sitting on the well requires less force to move through the first peak to the right than to move to theleft. Therefore, there is a preferred direction of motion.Courtesy: K. Segall, E. Tras, J. J. Mazo (T.P. Orlando).

electronic devices in mtl annual report 2001

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