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Electronics Made Easy Martin S Denny

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Page 1: Electronics Made Easy

Electronics

Made

Easy

Martin S Denny

Page 2: Electronics Made Easy

CONTENTS LIST page INTRODUCTION 7 PASSIVE COMPONENTS 8 RESISTORS 8 Resistors-Examples (cal sheet 1) 11 DC Theory-Examples (cal Sheet 2) 12 DC Theory-Examples (cal Sheet 3) 13 CAPACITORS 14 Series and Parallel Connection 16 Charge and Discharge Characteristics 16 Capacitors in Power Supplies 17 Capacitors-Examples (cal sheet 4) 19 Examples and Answers for Cal Sheets 1 to 4 20 INDUCTORS 22 SWITCHES 24 Fig 1 Latching Relay 26 Fig 2 DC Motor Reverse Control 26 BATTERIES 27 CRYSTALS 28 LOUDSPEAKERS AND MICROPHONES 28 TEMPERATURE MEASURING DEVICES 29 Thermocouples 29 Thermistors 30 OTHER DETECTORS 30 Light Dependant Resistor 30 Strain Gauges 30 AC THEORY 31 Fig 1 Voltage Waveform 31 Fig 2 Phase Relationship 31 Fig 3 Full Wave Rectification 32 Fig 4 Power Supply Smoothing 32 SEMICONDUCTORS 33 SEMICONDUCTOR MATERIALS 33 N Type Semiconductors 33 P Type Semiconductors 33 The P-N Junction 33 Fig 1 Reverse Bias 34 Fig 2 Forward Bias 34 DISCRETE COMPONENTS 34

Page 3: Electronics Made Easy

The Diode 34 The Zener Diode 35 Fig 3 Voltage Reference 35 The Transistor 36 Fig 4 Definition of Terms 36 Fig 5a Fixed Bias 37 Fig 5b Collector To Base Bias 37 Fig 5c Self Bias 37 The AC Circuit 37 Fig 6 Self Bias With AC Equivalent 39 Feedback in Transistor Circuits 39 Fig 7 Two Stage Amplifier With Negative Feedback 40 The Transistor as a Switch 42 Fig 8 Transistor Switch 42 Power Dissipation 42 The Field Effect Transistor 43 Fig 9a Structure of an n-Channel FET 44 Fig 9b Symbol for an n-Channel FET 44 INTEGRATED CIRCUITS 45 OPERATIONAL AMPLIFIERS 45 Fig 10a 8 Way DIL Package 45 Fig 10b OP-AMP 45 Fig 10c Inverting Amplifier 45 Fig 10d Non-Inverting Amplifier 46 Fig 10e Differential Amplifier 46 Fig 11 Differential Amplifier With Proportional Feedback 46 The Parameters of Operational Amplifiers 47 Fig 12 The OP-Amp as a Summer 48 The Operational Amplifier as a Comparator 48 Fig 13 The OP-Amp As A Comparator 49 LOGIC 49 ANALOGUE CIRCUIT APPLICATIONS 50 OSCILLATORS 50 Sinusoidal Oscillators 50 Fig 1 Crystal Oscillator 50 Fig 2 Feedback Oscillator 50 Square Wave Oscillators 50 Fig 3 Clipped Sine Wave 51 Fig 4 Square Wave 51 Fig 5 Equal Mark-Space Ratio 51 Fig 6 Uneven Mark-Space Ratio 51

Page 4: Electronics Made Easy

ACTIVE FILTERS 52 Fig 7 Low Pass Filter Circuit Diagram 52

Fig 8 Low Pass Filter Plot 52 Fig 9 High Pass Filter Circuit Diagram 53

Fig 10 High Pass Filter Plot 53 Fig 11 Two Stage Low Pass Filter Circuit Diagram 54

Fig 12 Two Stage Low Pass Filter Plot 55 Fig 13 Two Stage High Pass Filter Circuit Diagram 55 Fig 14 Two Stage High Pass Filter Plot 56

OPTICAL ELECTRONICS 57 Light Emitting Diodes 57 Fig 1 LED Connection Details 57 Displays 57 Fig 2 LED Display 58 Photoconductors 59 Fig 3 Optical Isolator 59 DIGITAL ELECTRONICS 60 LOGIC 60 Fig 1 Logic Packages 61 Boolean Algebra 61 Fig 2 Package Optimisation 62 Timing and Counting 63 Fig 3 Schmitt Trigger 63 Fig 4 Pulse Width Control Circuit 64 Fig 5 T Type Flip-Flop 64 Fig 6 J-K Flip-Flop 65 The Binary System 65 Fig 7 Counter Showing 4 Bit Binary Count 66 Fig 8 Binary Counter Feeding Display Via Display Driver 66 Timers 67 The 555 as a Timer 67 Fig 9 The 555 As A Timer 67 The 555 as a Monostable Multivibrator 67 Fig 10 The 555 As A Monostable 68 The 555 as an Astable or Free Running Multivibrator 68 Fig 11 The 555 As A Astable 68 USEFUL LOGIC CIRCUITS 69 The Latch 69 Fig 12 NAND and NOR Latches 69 Inhibit 69 Fig 13 NAND and NOR Inhibit 69

Page 5: Electronics Made Easy

Time Delay 69 Fig 14 Time Delay Circuit 70 Astable Multivibrator 70 Fig 15 Astable Multivibrator 70 DESIGN 71 The Initial Design Process 71 The Brainstorming Session 72 Design Evaluation 72 The Specification 72 The Quotation 73 Design Development 73 Post Production Evaluation 74 The Operating Manual 74 Glossary of Terms 75 Planning 76 Fig 1 Production Plan 77 WORKSHOP PRACTICE 78 1.0 Useful Equipment 78 2.0 Construction Methods 79 3.0 Soldering and Assembly Techniques 81 4.0 Testing 86 5.0 Finishing 87 SYMBOL LIBRARY 88 DESIGN EXAMPLES 89 1) Light Sensitive Switch 89 Fig 1 LSS Option 1 89 Fig 2 LSS Option 2 89 2) Temperature Controller 92 Fig 3 Temperature Controller 92 3) Loudspeaker Delay Switch 95 Fig 4 Supply Inhibit Timer 95 4) Transistor Tester 97 Fig 5 Transistor Tester 97 5) NiCad Battery Charger 99 Fig 6 Current Drive 99 6) Bench Power Supply 101 Fig 7 5V To 18V Power Supply 101 7) 110V/240V Auto Select Power Supply 104 Fig 8a 12V Power Supply With 240V/110V Auto Selection 106 Fig 8b 12V Power Supply With 240V/110V Auto Selection 112 8) Isolated Pulse Conditioning Circuit 113 Fig 9 Pulse Converter 117

Page 6: Electronics Made Easy

9) Optically Coupled Frequency to Voltage Converter 118 Fig 10 Opto-Isolated Frequency to Voltage Converter 122

10) Precision Square Wave Oscillator 123 Fig 11 Precision Square Wave Test Oscillator Part 1 126 Fig 12 Precision Square Wave Test Oscillator Part 2 128 11) General Purpose Oscillator 133 Fig 13 Sine-Square Wave Oscillator Circuit Diagram 133 12) Pulse Counter 137 Fig 14 Pulse Counter Part 1 143 Fig 15 Pulse Counter Part 2 144 Fig 16 Pulse Counter Part 3 145 Fig 17 Pulse Counter Timing Diagram 146 13) Notch Filter 148 Fig 18 Notch Filter Circuit Diagram 151 Fig 19 Plot of LPF Element of Notch Filter 152 Fig 20 Plot of HPF Element of Notch Filter 152 Fig 21 Notch Filter Output Plot Amplifying Notch 153 Fig 22 Notch Filter Gain Plot Attenuating Notch 153 Fig 23 Notch Filter Phase Plot Attenuating Notch 154 14) Non Linear Amplifier or Characteriser 155 Fig 24 Square Law Characteristic 156 Fig 25 Log Characteristic 157 Fig 26 S Curve Characteristic 158 Fig 27 Non Linear Amplifier Circuit Diagram Part 1 165 Fig 28 Non Linear Amplifier Circuit Diagram Part 2 166 Fig 29 Non Linear Amplifier Circuit Diagram Part 3 167 Fig 30 Non Linear Amplifier Additional Connection Details 168 15) Scanner 171 Fig 31 Scanner Circuit Diagram Part 1 Multiplex Stage 175 Fig 32 Scanner Circuit Diagram Part 2 Display Stage 176 16) Dice 177 Fig 33 Dice Circuit Diagram 179 17) Pulse Multiplier 181 Fig 34 Pulse Multiplier 184

Page 7: Electronics Made Easy

Introduction Electronics Made Easy started as a series of lessons produced for my son in 1998 to bring him up to GCSE standard. In general I have tried to keep mathematics to a minimum as in the real world it is rarely necessary to go above GCSE level. At this stage I must admit a certain bias in dealing with the subject, as somebody involved with electronic design in industry for most of my working life there is a tendency to over emphasise design techniques, the good bit. Certain aspects of the 1998 GCSE Electronics Products syllabus were current technology when I started my Degree in 1968. Although I have described the operation of obsolete devices, more modern equivalents are used in the examples. Some useful designs examples are provided at the end of the book. Some people may find electronic theory difficult to grasp, after all you cannot see current flowing through a device. The concept of current flow from positive to negative appears to be reasonable, but in reality electrons flow from negative to positive so we describe current in semiconductors as the flow of positive holes, and forget all about electrons for the rest of the time. When dealing with any complicated subject it pays to develop a mental model, for example let voltage be pressure, and current be water flow. Using this analogy resistance becomes a restriction or kink in a pipe, capacitance a tank and a diode becomes a non return valve. Transistors become diaphragm valves and zener diodes a tank with an overflow. Using this mental technique should enable you to grasp the basic concepts it worked for me anyway.

Page 8: Electronics Made Easy

PASSIVE COMPONENTS.

RESISTORS Resistors as the name suggests resist the flow of electricity. When a current is passed through a resistor a voltage is developed across it. The resistance to the flow is measured in Ohms. Resistors are produced in all sizes and can either be of a solid material or wire wound. The material chosen depends on many factors: 1) The stability with time and temperature. 2) The required power dissipation. 3) The accuracy required (the tolerance to which it can be produced). Common materials: 1) Copper, Low resistance meter shunts 2) Metal Alloys for high resistance wire. 3) Carbon 4) Metallic Oxides. 5) Iron (used in large high power resistors)

Fixed Resistors With Power Ratings 0.25 Watts To 25 Watts.

Page 9: Electronics Made Easy

Various Potentiometers Note High Powered Potentiometer On The Left Shows Method Of Construction.

Single Turn Open Frame, And Multiturn Trimmers.

Page 10: Electronics Made Easy

Symbols Resistor Variable Resistor or Potentiometer Many resistors are identified using a colour code shown below: 1 2 3 4 Band 1 First Digit 2 Second Digit 3 Multiplier 4 Tolerance % Band 1 First Digit 1 2 3 4 5 2 Second Digit 3 Third Digit 4 Multiplier 5 Tolerance % Colour Code 0 Black (Blk) 4 Yellow (Yel) 8 Grey (Gry) 1 Brown (Brn) 5 Green (Grn) 9 White (Wh) 2 Red (Red) 6 Blue (Blu) 3 Orange (Or) 7 Violet (Vio) Gold and silver bands are sometimes used to indicate the tolerance of High Stability resistors and generally indicate 1% and 2% respectively.

Page 11: Electronics Made Easy

RESISTORS (Examples)

All resistance values in Ω (Ohms). K is 1000 M is 1000,000 Resistors Connected in Series R1 R2 RT RT= R1+R2 Q1 Calculate RT

a) R1 10KΩ R2 10KΩ b) R1 4K7Ω R2 5K6Ω c) R1 100KΩ R2 1MΩ d) R1 10KΩ R2 2M2Ω e) R1 47KΩ R2 150KΩ Resistors Connected in Parallel R1 R2 1 1 1 - = - + - RT R1 R2 RT Q2 Calculate RT

a) R1 10KΩ R2 10KΩ b) R1 4K7Ω R2 5K6Ω c) R1 100KΩ R2 1MΩ d) R1 10KΩ R2 2M2Ω e) R1 47KΩ R2 150KΩ Resistor Networks Q3 Calculate RT

R1 a) R1 10KΩ R2 7K5Ω R3 15KΩ b) R1 12KΩ R2 5K6Ω R3 47KΩ c) R1 20KΩ R2 15KΩ R3 120Ω d) R1 470KΩ R2 1MΩ R3 10KΩ R2 R3 RT Cal Sheet 1

Page 12: Electronics Made Easy

DC Theory Examples Ohms Law V=I*R Power Calculation P=V*I Where: P is power in watts ( W ) V is volts ( V ) I or i is current in Amperes ( A ) The following Symbols are used as multipliers:

K 1000 times For example mA, µA, mV, KV, etc M 1000,000 times m 1/1000

µ 1/1000000 All resistance values preferred see component lists i R V Q1 Calculate Power Dissipation in each case and the missing value: R i V

a) 10KΩ 1.5mA ---

b) 100KΩ --- 12V c) --- 6mA 12V

d) 1MΩ 20µA --- The following circuit shows a voltage divider network i R1 Vin Vout R2 Q2 Calculate the power dissipation in each resistor and the missing values: Vin Vout R1 R2 i

a) 15V 3.46V 1KΩ --- ---

b) 12V --- 4K7Ω 3K3Ω --- c) --- --- 10KΩ 20KΩ 1mA d) --- 5.0V 5K6Ω 6K8Ω --- e) 6V 1.0V 10KΩ --- --- f) 15V --- --- 1K2Ω 5mA Cal Sheet 2

Page 13: Electronics Made Easy

DC Theory Examples The following circuit shows a voltage divider network which feeds a circuit with a resistance load of 1M ohm as shown below: i R1 Note: i=i1+i2 i1 i2 1/Ro = 1/R2 + 1/1M Vin Vout 1/R2 = 1/Ro - 1/1M R2 Q1 Calculate the missing values: (all resistance values in ohms) Vin Vout R1 R2 i i1

a) 15V 3.45V 10KΩ --- --- ---

b) 12V --- 4K7Ω 3K3Ω --- ---

c) --- --- 10KΩ 20KΩ 1mA ---

d) --- 5.0V 5K6Ω 6K8Ω --- ---

e) 18V 3.24V 10KΩ --- --- ---

f) 15V --- --- 1K2Ω 5mA --- Q2 In the previous questions the power dissipation of the resistors is calculated. Discuss why this is necessary. Q3 Resistors are produced from several materials. What factors influence the choice of material. Q4 Identify the value and tolerance of the resistors shown below: 1 2 3 4 Band 1 2 3 4 a) Red Red Or Brn b) Brn Blk Yel Red c) Or Wh Blk Gold d) Grn Blu Brn Red e) Brn Blk Grn Red 1 2 3 4 5 Band 1 2 3 4 5 f) Red Red Blk Or Brn g) Brn Blk Blk Yel Red h) Or Wh Blk Blk Brn i) Grn Blu Blk Brn Red j) Brn Blk Blk Or Red Q5 Construct a resistance network using a variable resistor and fixed resistors to produce an output from 1.0V to 2.0V from an input voltage of 15V. The input current must be greater than 5mA and less than 12mA. Cal Sheet 3

Page 14: Electronics Made Easy

CAPACITORS

Electrolytic Capacitors.

Polyester, Polycarbonate, Ceramic And Tantalum Bead Capacitors. In simple terms a capacitor conducts alternating current but not direct current its ac resistance or reactance is inversely proportional to frequency.

Reactance xc = 1/2πfC

Page 15: Electronics Made Easy

Capacitors are made up of two conducting plates separated by a dielectric, as the symbol suggests, the larger the area the greater the capacitance. In some cases a thin dielectric film is coated with a layer of metal then rolled up not unlike a Swiss roll.

Electrolytic capacitors are used mainly in smoothing applications where a large capacitance is required in a small space. This is achieved due to the extreme thinness of the dielectric which is an insulating film built up by an electrolytic process on one of the electrodes. The film deposited on the electrode acts as a dielectric with a high resistance in one direction but when the polarity is reversed it presents a low resistance. Thus a voltage reversal must be avoided. The capacitor working voltage limitation refers to the maximum peak voltage the capacitor will withstand before the dielectric breaks down. Capacitor Types: Electrolytic:- Polar capacitor, ie polarity sensitive. Used in applications

where high values are required, at high working voltage. Tantalum Bead:- Miniature capacitor used as a direct replacement for

electrolytic capacitors in lower voltage applications (up to 35V dc).Tantalum capacitors are not available at values above

100µF. Polyester:- These capacitors use polyester as a dielectric, they are more

stable than the above capacitors but are not available above

10µF. They are not polarity sensitive and are generally used for coupling, de-coupling and less sensitive timing circuits.

Ceramic:- Ceramic capacitors have similar uses to polyester capacitors

but are available at higher working voltage. Maximum value

typically 0.1µF. Polystyrene:- These capacitors use polystyrene as a dielectric, as they

combine high temperature stability and high accuracy. They are used for filter and accurate timing applications but are not available above 10nF and are not used in high voltage applications.

Silvered Mica:- These capacitors have a similar specification to polystyrene

but work at a higher dc voltage (500v). They are available up to 47nF. These capacitors are constructed by depositing a thin layer of silver on a thin mica slice as a dielectric.

Variable Capacitors:- These capacitors consist of two banks of blades with a

sufficient gap to allow the second bank mounted on a shaft to pass through it and provide a dielectric. In some cases a dielectric sheet of polystyrene or mica is interposed. This enables the clearances to be reduced. Variable capacitors are used in tuned circuits ie transistor radio's, television etc.

Page 16: Electronics Made Easy

Variable Capacitors Series and Parallel Connection C1 C2 In Series 1/CT = 1/C1 + 1/C2 CT OR CT = C1 * C2/(C1 + C2) -------- Units of capacitance Farad F

µ = 1/1000,000 n = 1/1000,000,000 p = 1/1000,000,000,000 C1 In Parallel: C2 CT = C1 + C2 CT Charge and Discharge Characteristics When the switch S is closed current i charges capacitor C via R1. The voltage across the capacitor rises until it reaches Vout (see Fig 1 ). Vout is calculated from the equation: Vo = Vin * R2/(R1 + R2) (see section on voltage dividers)

Page 17: Electronics Made Easy

The time taken to achieve full output voltage (Vout) is calculated as follows: T (sec) = C * R1 When the switch S is opened capacitance C discharges through resistor R2, (see fig 2). The time taken to fully discharge T is calculated as follows: T = C * R2 S i R1 C R2 Vin Vout

This circuit is especially useful in generating voltage ramps and timing functions, ie delay circuits when used in conjunction with an amplifier. This enables only the near linear portion of the curve to be used. The equation assumes that the ramp is linear and in practice when this circuit is used with a CMOS buffer which will switch before the circuit has timed out, a correction factor of 0.7 is used, ie T = 0.7CR. Capacitors in Power Supplies. Electrolytic Capacitors are used in power supplies to smooth the output DC voltage. The drawing below shows the output from a diode bridge rectifier feeding a smoothing capacitor C. The effectiveness of the smoothing capacitor depends on the amount of current fed into the circuit load R, the larger the current requirements the greater the capacitance value must be to maintain an acceptable voltage ripple on the output voltage.

To calculate the value of the capacitance:

Page 18: Electronics Made Easy

CV = IT Where C = Capacitor value V = Voltage ripple (rms) C = IT/V T = 1/2f (for diode bridge) I = Load current ie If Vin = 12V (rms) 50 Hz Vout = 1.414 * 12 - 1.2 = 15.8V Where 1.414 gives the peak value of the waveform, and 1.2v is the voltage drop across the diode bridge. If R = 20 ohms then I = 15.8/20 = 790mA If maximum acceptable ripple 1V then C = 0.79/ 2 * 50 * 1 C = 0.0079F = 7900æF

Nearest preferred value 10,000µF Note:- This would be perfectly acceptable when feeding a voltage regulator but in many applications this amount of ripple would be unacceptable.

Page 19: Electronics Made Easy

CAPACITORS ( Examples ) C1 C2 In Series, 1/CT = 1/C1 + 1/C2 CT CT = (C1 * C2)/(C1 + C2) Q1 For C1 and C2 connected in series calculate the value of CT when:

a) C1 = 1µF, C2 = 2µF b) C1 = 10µF, C2 = 100µF c) C1 = 2.2µF, C2 = 4.7µF d) C1 = 1000pF, C2 = 4700pF C1 In Parallel: C2 CT = C1 + C2 CT Q2 For C1 and C2 connected in parallel calculate the value of CT

a) C1 = 1µF, C2 = 2µF b) C1 = 10µF, C2 = 100µF c) C1 = 2.2µF, C2 = 4.7µF d) C1 = 1000pF, C2 = 4700pF

Q3 Calculate the value of reactance of a 1µF capacitor at the following frequencies:

Reactance xc = 1/2πfC a) 50 Hz Note: π = 3.142 b) 100 Hz c) 400 Hz d) 20 KHz Q4 calculate the time delays at switch "on" and switch "off" for the following values of R1 and R2, shown in fig 1:

a) R1 = 100KΩ, R2 = 1MΩ. Note: For switch "on" T1 = R1*C b) R1 = 470KΩ, R2 = 2MΩ. For Switch "off" T2 = R2*C c) R1 = 7K5Ω, R2 = 750KΩ Q4 Select a suitable capacitor which will reduce the ripple voltage to less than 1V rms for the circuit shown below.

Cal Sheet 4

Page 20: Electronics Made Easy

Examples and Answers for Cal Sheets 1 to 4

Cal Sheet 1 Q1a 20KΩ b 10K3Ω Q1a RT = R1 + R2 c 1M1Ω d 2M21Ω RT = 10K + 10K e 197KΩ

RT = 20KΩ

Q2a 1/RT = 1/R1 + 1/R2 Q2a 5KΩ b 2K56Ω 1/RT =( R2 + R1 )/R1*R2 c 90K9Ω d 9K95Ω RT = R1*R2/( R1 + R2 ) e 35K8Ω

RT = 100M/20K = 5KΩ

Q3a RT = R3 + R1*R2/( R1 + R2 ) Q3a 19K3Ω b 50K8Ω RT = 15K + 75M / 17K5 c 8K69Ω d 329K8Ω RT = 15K + 4K29 = 19K3Ω Cal Sheet 2 Q1a V = I * R Q1a V = 15V, P = 22.5mW b I = 120uA, P =14.4mW

V = 10000 * .0015 = 15V c R = 2KΩ, P = 72mW d V = 20V, P = 0.4mW P = V * I P = 15 * 1.5 mW = 22.5 mW

Q2a i = (Vin - Vout)/R1 Q2a i = 11.54mA, R2 = 300Ω P(R1) = 133.2mW i = 11.54/1 mA = 11.54mA P(R2) = 39.9mW Vout = i * R2 b i= 1.5mA, Vout = 4.95V P(R1) = 10.58mW R2 = Vout/i = 3.46/11.54 K P(R2) = 7.43mW R2 = 299.8 c Vin = 30V, Vout = 20V P(R1) = 10mW

R2 = 300Ω P(R2) = 20mW P(R1) = (Vin - Vout) * I d i=0.735mA, Vin=9.1v P(R1) = 3.02mW P(R1) = 11.54*11.54 = 133.2mW P(R2) = 3.68mW

P(R2) = vout * i e i = 0.5mA, R2 = 2KΩ P(R1) = 2.5mW P(R2) = 3.46*11.54 mW = 39.9mW P(R2) = 0.5mW

f Vout = 6V, R1 = 1K8Ω P(R1)=45mW,P(R2)=30mW

Page 21: Electronics Made Easy

Cal Sheet 3 Q1a i1 = 1.150mA

Q1a i = ( Vin - Vout )/R1 i = 1.155mA, R2 = 3KΩ i = 11.55/10 mA = 1.155mA b i1 = 1.497mA i = 1.502mA, If Ro is combined output R Vout = 4.94V 1/Ro - 1/1M = 1/R2 c Vin = 29.61V, Vout = 19.61V R2 = 1M * Ro/(1M - Ro) i1 = 0.980mA Ro = Vout/i d Vin = 9.15V i = 0.740mA Ro = 3.45/1.155 K = 2K987ê i1 = 0.735mA R2 = 1M * 2K987/(1M - 2K987) e i = 1.476mA

R2 = 2K2Ω R2 = 1M * 2K987/997K013 Ω i1 = 1.473mA

R2 = 2K9959 = 3KΩ f Vout = 5.99V R1 = 1K8Ω i1 = Vout/R2 = 3.45/3 mA i1 = 4.99mA i1 = 1.150mA

Q4a 22KΩ, 1% b 100KΩ, 2% c 39Ω high stab 1% d 560Ω, 2% e 1MΩ, 2% f 220KΩ, 1% g 1MΩ, 2% h 390Ω, 1% i 5K6Ω, 2% j 100KΩ, 2% Cal Sheet 4

Q1a CT = C1*C2/C1 + C2 Q1a CT = 0.67 µF CT = 1 * 2/1 + 2 æF b CT = 9.09 µF CT = 2/3 æF c CT = 1.50 µF CT = 0.67 æF d CT = 824 pF

Q2a CT = C1 + C2 Q2a CT = 3 µF CT = 1 æF + 2 æF b CT = 110 µF CT = 3 æF c CT = 6.9 µF d CT = 5700 pF

Q3a xc = 1/2ãfC Q3a xc = 3K18Ω xc = 106/2ã * 50 * 1 b xc = 1K59Ω xc = 3K18ê c xc = 398Ω d xc = 7.96Ω Q4a At Switch "on" Q4a T1 = 10 s T1 = R1 * C T2 = 100 s

T1 = 100K * 100 µs b T1 = 47 s T2 = 200 s T1 = 10 s c T1 = 750 ms T2 = 75 s At Switch "off"

T2 = R2 * C = 1M * 100 µs T2 = 100 s Q5 Vout = 27V, R = 100ê, V ripple = 1V i = Vout/R = 27/100 = 0.27A CV = iT, T = 1/2f (for diode bridge) C = i/2fV = 0.27/2*50*1 F

C = 2.7 * 10-3 F = 2700 µF Preferred Value for C = 3300 µF

Page 22: Electronics Made Easy

INDUCTORS

Various Chokes.

Transformer (PCB Mounting). Inductors are employed in many high frequency circuits, ie radio, television, video recorders, etc. Included in this section are transformers and chokes which can be considered to be inductors, and are used in almost every ac appliance.

Inductors are available in all types ranging from small air cored coils

used in radio frequency tuned circuits, having an inductance of a fraction of a

micro-henry (µH) to the iron cored coils used in passive filters, where the inductance may be as large as 100 Henrys.

Page 23: Electronics Made Easy

At high power and low frequency iron laminates are used, ie chokes and

transformers (this is necessary to reduce heat build up in the core which would result in high temperature and poor efficiency). At high frequency magnetic powder cores are used (ie Ferrite). Ferrite consists of ferromagnetic particles coated with insulating material, compacted to form a solid mass (used in RF chokes, IF transformers and ferrite rod aerials).

Coils or inductors are generally made from copper wire either solid or in

the form of twisted and insulated filaments. As the frequency increases a higher proportion of the current is carried on the outside of the conductor, this is called the "skin effect" which is even noticeable at 50 Hz. By increasing the outside area of the conductor economies can be made in size and weight. At ultra high frequencies (GHz range) wave guides are used which resemble square section pipes the size dependant upon the frequency.

Direct current relays use a solid core where the requirement is to produce

a magnetic field capable of operating relay contacts. Inductance in this case is an unwanted by-product and can cause problems due to inverse voltage spikes. This problem is alleviated by the use of a diode connected across the relay coil, which conducts in the reverse direction of the power supply.

The impedance (Z) of a inductor is the vector sum of its dc resistance and its ac reactance.

Z = R + xl Ω

where xl = 2πFL Ω

Page 24: Electronics Made Easy

SWITCHES (including relay contacts)

Switches are manufactured in all shapes and sizes. Limiting factors in size are contact area and contact separation, ie current and voltage rating. Switch contacts are made from a variety of conductors dependant on the estimated life of the component, and the contact resistance. In some cases mercury is used either to wet the contacts (anti-bounce), or in liquid form to provide low resistance high current switching (arc suppression), for example tilt switches. Restrictions in some European countries prevent the use of mercury for Health and Safety reasons.

The most common forms of switch use, toggle (up/down), push button

(in/out) or rotary action. Micro switches can be best defined as a push button switch operated by a lever arm. These switches are used mainly as limits to mechanical operations ie voltage "cut outs" on equipment doors movement restriction on machinery even as a reversing switch on some windscreen wiper motors.

Reed/relay switches are also quite common and can be operated either by a

relay coil, or a fixed magnet. They are available as single, double, and change-over options. Construction of the relay is simplified as contacts are deflected by the magnetic field rather than an arm operated by the electro-magnet as in

Page 25: Electronics Made Easy

more conventional relays. The contacts are sealed usually in a glass envelope, which allows mercury wetted contacts to be used. The construction of reed relay switches enables them to be used in hazardous environments, and at high frequency. They are also useful in applications where high packing density is required due to their relatively small size. Disadvantages are relatively low current switching and due to their size low voltage rating. Common Terms: SPST: Single Pole Single Throw. Switch contacts are either closed or open

(in off position). DPST: Double Pole Single Throw. Two sets of switch contacts are either

closed or open. SPDT: Single pole double throw. A single set of switch contacts, where c connection is made to a contact in either switch position. DPDT: Double pole double throw. Two sets of switch contacts where,

connection is made to both sets of contacts in either switch position.

Bias: Toggle switches can be biased up, down, or in the middle position.

This enables the switch to be used either as “off” in the middle position and “on” in the outer positions, or to return to a preset position either “on” or “off”.

CO: Change-over, equivalent to double throw in switch terminology, ie

changing a connection from one terminal to another. NO or NC: Normally Open/Closed, This term relates to the contact position when

a relay is de-energised.

Decade Switch And Switch Wafer

Page 26: Electronics Made Easy

Figure number 1 shows an example of a latching relay circuit. When RL1 is energised via PB1 the energised contacts are made. RL1b contact supplies the load whilst RL1a provides an alternative supply to the relay coil. To reset the relay PB2 is depressed removing the relay coil supply. Diode D1 provides protection against back EMF generated by the inductance of the coil.

Page 27: Electronics Made Easy

Figure number 2 shows an example of a DC motor reverse control circuit. With the relay de-energised the positive connection is made at the top motor terminal and negative to the bottom terminal. When SW1 is closed RL1 is energised thus reversing the power connections. Diode D1 provides protection against back EMF generated by the inductance of the coil. BATTERIES Three components are required to produce a voltage cell, two metallic electrodes of dissimilar material, and a suitable electrolyte. Batteries can be separated into two types, non-rechargeable and rechargeable. Non-Rechargeable Batteries: Zinc-Carbon: A standard dry cell, an electrolyte paste is used the main

advantage is that the cell is inexpensive. Zinc-Chloride: A dry cell with a higher energy content (long life etc). They

are more expensive than the standard dry cell and should be used for equipment with higher loads or where regular charging of batteries is inconvenient, ie smoke alarms, electric bells etc.

Alkaline: A Mercury free dry cell with a higher energy content than

Zinc-Chloride batteries. These batteries are twice the price of Zinc-Chloride batteries.

Silver Oxide: Usually Button cells suitable for watches, calculators etc.

Cell voltage 1.55v. Mercury Oxide: Button cells as above but cell voltage 1.35v. Lithium: Coin cell designed for low current drain applications memory

back up etc. The main advantage is that the cell is less expensive than rechargeable equivalent. Nominal voltage 3v.

Zinc-Air: These batteries operate using a reaction between the zinc

anode and free oxygen, which enters through small holes in the body, and the outer can. When not in use these holes can be sealed giving the battery a long shelf life. This allows operational life to be confidently calculated. The use is mainly restricted to medical and other portable equipment where reliability is paramount, as these batteries are expensive.

Rechargeable Batteries: Lead-Acid: These batteries use either a liquid electrolyte or a viscous

gel the unwanted by-product being Hydrogen so in some cases they are sealed. All these batteries should be charged in a well ventilated area whatever manufacturers instructions. Advantages are high charge and discharge rates. Disadvantages weight and size. Typical uses vehicle and static plant electrical supply, supply back-up and UPS applications. These batteries are the most cost effective of the rechargeable batteries.

Nickel-Cadmium: These cells are the most commonly used rechargeable batteries

apart from Lead-Acid. They do not suffer from the charging problems associated with lead-acid batteries and are more

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compact, typical voltage 1.2v/cell. Disadvantages are the low charging rate and expense. They are commonly used in portable equipment, memory back-up, radio controlled cars and low power UPS applications (not greater than 500w).

Lithium: These coin cells have the advantages of the non rechargeable

lithium cells that their output voltage per cell is 3v. Used generally in memory back-up circuits where non rechargeable cells would have insufficient life. Main disadvantage is low power output.

CRYSTALS (XTAL) Quartz Crystal Vibrator Certain natural crystalline materials exhibit what is known as the piezo-electric effect. If a slice is cut in a particular direction and a metallic film applied to two opposite faces so that the arrangement can function as a capacitor the application of a potential difference (v) to the electrodes produces a mechanical strain in the crystal if the potential is reversed so is the strain.

The strain will tend to set up vibrations in the structure of the crystal which will then vibrate at its natural frequency (resonance). The natural frequency is dictated by the thickness of the slice of crystal.

Quartz crystal has good temperature stability and can be cut with great accuracy. The resonant frequency of the crystal can be determined to 10 ppm (parts per million). Temperature stability of 50 ppm/deg C is typical for crystals above 1 MHz.

Due to their accuracy and stability Quartz crystals are used in the communications field where high frequency stability is required, the generation of clock signals in computers, and the reference signals in most clocks and watches. LOUDSPEAKERS AND MICROPHONES If a cone is pointed at a sound source it will tend to vibrate at the frequency of the sound. These vibrations are used to generate movement of a coil mounted at the centre of the cone. The coil moves within a magnet so a small voltage proportional to the sound is generated and it becomes a microphone. If voltage is fed to the coil then it will be translated into a movement of the coil and therefore the cone, thus producing sound. It then becomes a loudspeaker.

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Loudspeaker Microphone Microphones can also be constructed using capacitance effect. In some

cases in line amplifiers or even small transmitters are incorporated into the microphone body. TEMPERATURE MEASURING DEVICES Thermocouples:

The previous diagram shows a simple thermocouple circuit with junctions at T1 and T2. The thermocouple will generate an output voltage proportional to T2 -

T1, (For NiCr/NiAl approx 4mV per 100°C). The main disadvantage with this system is the need to reference the junction at T1. This is sometimes achieved by inserting a second thermocouple in series and placing the end in melting ice

(0°C), or using a thermistor to generate a voltage equivalent to the ambient temperature (T1). Where many thermocouples are terminated one reference may serve all thermocouples if they are mounted in a sealed junction box, the box is then considered to be isothermal.

Thermocouples are used at all temperatures from ambient to above 600°C although platinum resistance thermometers give better results under 100°C.

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Thermistors: R Vs Rt Vout

These devices vary their resistance with temperature (+ve or -ve response) and are generally used in control applications. It is necessary to calibrate systems using thermistors as they are non-linear. A simple circuit is shown above. A supply voltage Vs feeds the voltage divider formed by resistor R and the thermistor Rt. The voltage across the thermistor will then vary with temperature. OTHER DETECTORS Light Dependant Resistor (LDR): These devices are housed in a moulding or case with a clear end window to allow light to fall on the cadmium sulphide resistor. These devices have negative response to light, ie resistance reduces as the light falling on the device increases. LDR`s are generally used as sensors for remote outside lighting. Strain Gauges: Direction of Strain <---> Strain gauges are a thin element of a conductor constructed as shown above mounted on a thin flexible film, which can be bonded to a sample. They are only effective in one plane so they are generally mounted in groups. As the sample moves the strain gauge is stretched which reduces the cross sectional area of the conductor, increasing the resistance.

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AC THEORY

The UK mains supply is specified as 240V rms at 50Hz. The waveform generated by a rotating magnetic field can be considered to be sinusoidal.

The drawing below, (see fig 1), shows a sinusoidal voltage waveform. The

average value of the waveform = Vpk/√2 (pk = peak and pp or pkpk the peak to peak value) and for current waveform Ipk/√2.

These values are known as the rms values, which equate to the dc equivalent, ie Power = V * I.

The voltage and current waveforms shown below in fig 2 are displaced by

the phase angle 90° (pure resistive load). The phase shift of the voltage and current waveforms is dependant on frequency as is the impedance Z. The impedance of a circuit is its AC resistance in ohms.

An inductive load will produce a lagging current waveform whilst a capacitive load will produce a leading current waveform. The reactance X of the

load can be represented as a vector drawn at 90° to the resistance vector (pure capacitance or inductance only). The value of the reactance X is frequency dependant as shown below:

Xc = 1/2πfC Xl = 2πfL A circuit will exhibit its minimum ac resistance (impedance Z) when Xl = Xc, and the power in the circuit W = VA (the product of V*I). The power factor of a circuit is the relationship between power W and VA. Power Factor = W/VA The impedance of a circuit (Z) can be calculated by using Pythagoras Theory:

Z = √(R2 + X2) When a sinusoidal waveform is passed through a bridge rectifier the resultant waveform is the positive half of the sine wave with the mirror image of the

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negative half added (full wave rectification). The resultant waveform will have a Time T = 1/2f and a voltage of 1.414Vrms - 1.2V (voltage drop across the diode bridge) as shown below in fig 3.

If a smoothing capacitor is connected across the positive and negative terminals of the bridge in parallel with the resistive load the resulting voltage ripple can be calculated as follows:

As P = VI = I2R and Energy E = QV and Pt = VIt then: QV = VIt therefore Charge Q = It

as charge Q can be expressed as CV then CV = It and V = It/C

The result of smoothing on a full wave rectified voltage is shown below in

figure 4. The resultant ripple is shown superimposed on the bridge output without smoothing.

The power supply is shown with a resistor R (the load). The maximum output

with no load Vo max = 1.414V - 1.2V, where V is the transformer output in volts rms. The transformer will have a known droop factor at full load, given in percentage of rated output. The power supply dc output will be further reduced by the level of voltage ripple.

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SEMICONDUCTORS SEMICONDUCTOR MATERIALS

Semiconductors are termed active components as the name suggests they exhibit a high or low impedance dependant upon current flow.

The most common forms of semiconductor are silicon and germanium, in their pure form they behave as an insulator and are said to be an intrinsic semiconductor. The relatively low conductivity of an intrinsic semiconductor can be increased considerably by the introduction of impurities. These impurities have the property that their atoms nearly fit into the crystal structure of the semiconductor. N-type Semiconductors

If a pentavalent impurity element such as arsenic or antimony is introduced into say a germanium crystal only 4 out of 5 valence electrons in each atom are used in forming covalent bonds with the surrounding germanium atoms. The 5th electron even at relatively low temperatures will acquire enough energy to break away and increase the conductivity of the material (electron rich). In N-type materials the impurity atoms become positive ions, which are fixed and an equal number of electrons are able to move about in the crystal. P-type Semiconductors

Intrinsic semiconductor atoms may be displaced by atoms of trivalent elements such as indium, gallium or boron. In this case there is an incomplete valence band leaving a hole which may be neutralised by an electron moving into it from a nearby bond (electron poor). The hole can move at random and therefore acts as a positive charge carrier. The holes are the majority carriers in this material. The P-N Junction n type p type Barrier Region The p-n junction refers to the boundary between two types of semiconductor where the material is in effect a single crystal. The formation of the junction causes some holes from the p material and some electrons from the n material to diffuse towards each other and combine. The positive charge on the n side and the negative charge on the p side form a potential a potential barrier. The potential difference across the barrier is sufficient to prevent the movement of both holes and electrons.

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Fig 1 Reverse Bias - + N type p type + -

If a p-n junction is reverse biased the depletion layer is increased. The electrons are attracted towards the positive terminal whilst the holes are attracted towards the negative terminal. When the barrier potential is increased in this way the junction is said to have reverse bias applied, (see Fig 1). Fig 2 Forward Bias - + n type p type - +

If a p-n junction is forward biased the electrons in the n type material are then attracted across the junction towards the positive terminal of the battery, while the holes move towards the negative terminal. The internal potential barrier is reduced until its effect is nullified,(see Fig 2).

One by-product of the p-n junction is that as the depletion layer increases in width so does the capacitance therefore the p-n junction becomes a voltage dependant capacitor. DISCRETE COMPONENTS The Diode

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i

The characteristic of the p-n junction allows current to pass in one

direction (forward bias) while it becomes a high impedance in the other direction (reverse bias). The forward bias necessary to overcome the barrier potential is approximately 0.2V for germanium and 0.6V for silicon, most modern semiconductor devices use silicon.

Diode Bridges For Use In Power Supplies. The Zener Diode

The Zener Diode is defined by Vb breakdown voltage and Pt maximum power. To determine the diode load select Iz

≤ Pt/Vb. Maximum Iz will occur when Il is at minimum. R = (Vs-Vb)/I where I=Iz+Il

To Calculate Resistor Power: Pr = I(Vs-Vb) Fig 3 Voltage Reference Diodes, which are designed with adequate power dissipation to operate in the breakdown region, are known as avalanche breakdown or zener diodes. The diode is capable of regulating the output voltage from a relatively low current (Iz) to the point at which Iz = Pt/Vb (see Fig 3 above).

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The Transistor

The transistor can be considered as two p-n junctions arranged p-n-p or n-p-n. A p-n junction with a forward bias has a low resistance and conversely a high resistance with reverse bias. If a small control current is introduced at the mid point of the two junctions and sufficient current fed in to forward bias one junction and reverse bias the other, then a current should pass through the device. The collector current (Ic) is much greater than the control current (Ib) this factor is known as Gain (hfe), (See Fig 4).

Before a transistor can act as an amplifier the DC bias conditions and gain must be set so that the resulting waveform is of the correct amplitude. Another consideration is the input and output impedance of the stage. The previous stage must be able to drive the input at the transistor base via a decoupling capacitor, and the transistor drive its output load.

The same calculations are true for NPN, PNP, and even Darlington

configured transistors. The Darlington configuration is used when high gain is combined with high power. Power transistors generally have a low gain. If a medium power transistor is combined in the same package high gain and high power output can be achieved. The only significant difference to be taken into account is that the Vbe voltage of the first stage must be added to that of the second.

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Fig 5a shows the simplest biasing arrangement; the voltage at the

collector is controlled by the value of R2 and the current passing through it (Ic). For maximum output without saturation Vc = 0.5Vs, the maximum value of Ic should not be exceeded when the transistor is fully switched on (ie Vc equal to approximately 0V). The supply voltage must also be taken into account so the maximum Vce voltage is not exceeded.

Calculating the DC Bias of the amplifier. (R1 and R2):

R2 = (Vs - Vc )/ Ic Where: Vs is the supply voltage.

Vc is the collector voltage, (0.5 * Vs). Current Gain hfe = Ic/Ib Ic is the desired collector current. Ib is the base current. Ib = Ic/hfe (see transistor data sheet) R1 = (Vs - Vbe)/Ib

Note, this configuration limits Vin to less than 1.2V pkpk The AC Circuit (Voltage Gain):

The ac equivalent circuit of the amplifier can be described as the dc circuit where the 0v and +Vs rails are considered to be at the same potential, and the transistor can be considered as a device with input impedance hie and gain hfeIb, (note, hfe*Ib = Ic). Figure 6 shows a simplified circuit. In this case the values of Re and Cz are zero. Selection of coupling capacitor and bandwidth: An approximation of the input impedance can be made by assuming that the effect of hie (data not generally available) is small and the major effect will be that of the collector voltage and current and any load resistors present. For the purposes of selecting a coupling capacitor:

Rin ≡ Vc/Ib*hfe ≡ Vc/Ic

C1 must be chosen to have a value of xc considerably less than the input impedance of the amplifier over the desired frequency range of the amplifier. In this case the lower frequency must be considered.

xc = 1/2πfC.

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The bandwidth of this amplifier is specified at the frequencies where the output voltage drops to 50% of the mid range design value (3db point), ie when xc = Rin, and at the stated top end frequency of the transistor. The voltage gain will always be less than the current gain of the transistor due to the resistor loading. If the load on the output is equal to R2 then the gain will be reduced by 50% (see fig 6). The gain of an amplifier, or conversely the attenuation of a circuit is sometimes quoted in terms of decibels.

For voltage gain: Gain db = 10LogG* For power gain 20logG is used. For Example: A 50% drop in output voltage is equivalent to a gain of 0.5*. Gain db = 10Log0.5 = 10 * -0.30103 = -3db A stage gain of 1* = 10 * 0 = 0db

A stage gain of 10* = 10 * 1 = 10db

A stage gain of 100* = 10 * 2 = 20db A stage gain of 1000* = 10 * 3 = 30db Figure 5b shows an example of collector to base bias. The advantage of this configuration is that it offers better gain stability than the fixed biased example. In this case Ic and Ib pass through R4 so:

R4 = (Vs - Vc)/(Ic + Ib) R3 = (Vc - Vbe)/Ib Current Gain hfe = Ic/Ib

To select C2

Rin ≡ IcVc and Xc = 1/2πfC (Xc should be at least 0.1*Rin). Figure 5c shows an example of self bias. This configuration has several advantages over the previous examples, higher input levels can be accommodated as the emitter resistor allows the bias voltage level of the emitter and hence the base to be raised significantly above 0V.

With the capacitor C4 removed the output Vout can be connected across R8 (emitter follower), thus giving a low impedance output, (at the cost of gain usually reduced to approximately unity) and the Vce voltage can be reduced if this is critical.

R6 = (Vs - Vc)/Ic Note with C4 in circuit ( with xc considerably greater than R8 ) the bias set voltage at the collector (Vc) can be set to the same value as in previous circuits.

R8 = Ve/(Ic + Ib) hfe = Ic/Ib

R7 = (Ve + Vbe)/I, Where i is chosen ≥ Ib

R5 = (Vs - Vbe - Ve)/(i + Ib)

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To select C3

Rin ≡ IcVc, and xc = 1/2πfC (at least 0.1*Rin) To select C4

xc = 1/2πfC (at least 0.1*R8 at the lowest frequency) With capacitor C4 removed Vout will be elevated with respect to (wrt) 0V. The value of Vc can be adjusted to take this into account. The voltage gain will be reduced significantly.

Feedback in Transistor Circuits

When the input level of a single stage transistor amplifier rises, the increase in input current causes a proportional increase in collector current which reduces the output therefore the amplifier is a inverting amplifier. If two stages are used the output becomes non-inverting. It follows that odd stages are inverting and even stages non-inverting.

Feedback can either be positive (regenerative) or negative (degenerative).

Positive feedback can be demonstrated by placing a microphone connected to an audio amplifier close to the amplifier loudspeaker. Initially the loudspeaker is silent but the smallest sound is sufficient to start the process for every increase in sound is accompanied by a further increase from the speaker. Positive feedback is used in oscillator circuits. Negative feedback is used in amplifier design to provide gain control and stability.

Figure 7 demonstrates the use of voltage series feedback in an amplifier design. The design is of a two stage non inverting amplifier where negative feedback is fed from the output of stage 2 to the emitter of stage 1. This requires two stages as this circuit would provide positive feedback in a single stage.

Overall Gain = G1 * G2 * β,where β = Re/(Re + Rf)

Re is the emitter resistor Rf is the feedback resistor

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To design a non-inverting amplifier with gain variation 250 to 500, and a low frequency response down to 10Hz. Transistors BC108, hfe 110 to 800, Vce 5v, Ic max 100mA, Pt 300mW

Assume hfe 150.

Vs = 13.6V, hfe = 150, hfe = Ic/Ib Stage 1 (also basis for stage 2)

Let Ic = 2mA, then for 6v across R3, R3 = 3KΩ, and 2v across R4, R4 = 1KΩ.

For Ic = 2mA, Ib = 13.3µA

Voltage across R2 = 2v + 0.6v = 2.6v and i ≥ 0.01mA

Let R2 = 30KΩ then i = 86.7µA

Current through R1 = 86.7µA + 13.3µA = 100µA. Voltage across R1 = (13.6 - 2.6)V

Then R1 = 11/0.1 KΩ = 110KΩ.

Vc = 7.6v to estimate Rin, Rin ≡ Vc/Ic = 7.6/2 KΩ = 3K8Ω Selecting C1 and C3:

Try 1µF, then xc = 1/2πfc = 1/2π10*1 MΩ

xc = 15K9, If C = 10µF then xc = 1K59Ω.

Select C1 and C3 10µF, as R4 = 1KΩ Let C2 = 22µF (xc = 723Ω)

Current Gain 150, With output loading Rin (stage 2) ≡ 3K8Ω For voltage gain G1 (no load):

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Vout1 = hfeIb * R3 (see fig 6). When loaded:

Vout2 = hfeIb * R3Rin/(R3+Rin).

With no load G1 ≡ hfe therefore G1 = hfe Vout2/Vout1

G1 = hfeR3Rin/R3(Rin+R3) = hfeRin/(R3 + Rin)

G1 = 150 * 3k8/6K8 = 84 approx If the same design is used for stage 2: G2 = 150 unloaded

Total Gain = G1*G2 = 150*84 = 12600 and Overall Gain = G1*G2/β

β =R5/(R10 + R5) to (Vr1 + R5)/(R10 + R5 + Vr1)

For gain 250, β = 250/12600 = 1/50.4, For gain 500, β = 1/25.2

Let Vr1 = 200Ω then R5 = 200Ω and gain 10K nom Correcting G2: G2 = hfe(R10+R5)/(R8 + R10 + R5) =150*10K2/13K2

G2 = 116 approx

G1*G2 = 9736, β = 1/39 and 1/19.5

β = 200/(R10 + 200)

R10 + 200 = 200*39 therefore R10 = 7K6Ω

R10 = 7K5Ω preferred value. Component List

R1 110KΩ 0.25W MF R2 30KΩ 0.25W MF R3 3KΩ 0.25W MF R4 1KΩ 0.25W MF R5 200Ω 0.25W MF R6 110KΩ 0.25W MF R7 30KΩ 0.25W MF R8 3KΩ 0.25W MF R9 1KΩ 0.25W MF R10 7K5Ω 0.25W MF

Vr1 200Ω 20t cermet trimpot Tr1 BC108 Tr2 BC108

C2 22µF 6v wkg tantalum, Remainder 10µF poly

As a practical amplifier this design has many drawbacks:

1) Without testing each transistor before use an accurate estimate of gain and input impedance is impossible. 2) The value of Vr1 and R5 must be kept low in comparison R8 and R9.

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3) As the transistor has a relatively low input impedance multi-stage design becomes difficult as illustrated in the previous example.

Transistors have a relatively high frequency response and are frequently used in oscillator and in high frequency amplifier design. Other uses include the output stage in power amplifiers where the collector drives the load (loudspeaker) directly or via a capacitor. The Transistor as a Switch. For a transistor to operate as a switch the collector voltage should swing between 0 and the supply voltage (Vs), see figure 8. When Vc is 0v, Tr1 is switched on, Ic = Vs/R2

Ib ≥ Ic/hfe min and R1 = (Vin-Vbe)/Ib

In the switch mode the transistor is ideal, the base resistor can be

selected to saturate the transistor at the minimum value of hfe and presents a high input impedance.

The transistor in switch mode is used extensively for power regulation (voltage and current), switching relays, and sometimes as a buffer between dissimilar logic circuits. Power Dissipation. In the previous examples power dissipation has been low in comparison with the component ratings. When a transistor is operated near its maximum power rating it may become necessary to provide a heat sink. Heat sinks are designed to present the maximum surface area to the surrounding air and are constructed using a good heat conductor, (usually aluminium which is light and easy to mould into intricate shapes). If the transistor is housed in a metal box it is sometimes convenient to secure the transistor directly to the case, if this is done care must be taken to isolate the transistor electrically as the transistor body is generally connected to the collector.

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The Field Effect Transistor.

The FET is a semiconductor where the control of current is by an electric field. There are two types of field effect transistors the junction field effect transistor (JFET or FET) and he insulated gate field effect transistor (MOSFET). The FET has many advantages over conventional transistors: 1) The FET is a unipolar device; it depends on the flow of majority carriers only. 2) It is relatively immune to radiation. 3) It has a high input impedance typically megohms. 4) It is less noisy than a transistor. 5) It exhibits no offset voltage at zero drain current. 6) It has good thermal stability.

The main disadvantage is its small gain bandwidth in comparison with conventional transistors in high frequency applications. The following notation is standard: Source: The source S is the terminal through which the majority carriers

enter the bar. Conventional current entering the bar is designated by Is.

Drain: The drain D is the terminal through which the majority carriers

leave the bar. Conventional current entering the bar at D is designated by Id. The drain to source voltage Vds is positive if D is more positive than S.

Gate: On both sides of the n-type bar of (fig 9a) heavily doped (p+)

regions of acceptor impurities have been formed by alloying or diffusion (creating p-n junction). These impurity regions are called the gate G. Between the gate and source a voltage Vgs is applied in the direction to reverse bias the p-n junction. Conventional current entering the bar at G is designated Ig.

Channel: The region in fig 9a of n-type material between the two gate regions

is the channel through which the majority carriers move from source to drain.

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When the gate is biased negatively it repels some of the electrons flowing in the material and forces them into a narrower path thereby increasing the resistance of the current channel. In effect an increase in the reverse bias broadens the depletion layer where there are no free carriers and by constricting the conduction channel reduces the longitudinal current. Simply a FET controls drain-source current by the bias voltage on the gate, whereas the transistor controls the collector current by an increase in base current.

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INTEGRATED CIRCUITS

An integrated circuit consists of a single-crystal chip of silicon containing both active and passive elements and their interconnections. These circuits are produced by the same processes used to fabricate individual transistors and diodes.

Integrated circuits are cheap to mass produce and an operational amplifier for example can be purchased for the price of two general purpose transistors. OPERATIONAL AMPLIFIERS

These devices are generally housed in duel in line packages (DIL) although some military specification devices are housed in a metal can rather like a transistor but with more leads. Figure 10a shows a typical op-amp package. Packages are available in 8 way, 14 way, 16 way, up to 40 way, where several devices may be housed in the same package.

The operational amplifier,(op-amp) symbol shown in fig 10b shows an amplifier with a negative inverting input and positive non inverting input with respect to the output. The power supply connections are shown above and below the body of the amplifier. The amplifier is generally supplied with a duel power supply to enable it to operate either side of 0 volts, but in many cases it is cost effective to design a circuit where the amplifier output does not fall below zero volts thus making a size and cost saving in the design. Note not all operational amplifiers will operate with a single supply.

The operational amplifier configurations shown in figures 10c,10d and 10e

enable the amplifier to operate as an inverting, non-inverting or differential amplifier. Without external components the amplifier would have a gain in the order of 10,000 times therefore negative feedback is introduced into the design.

The inverting amplifier shown in figure 10c is driven from a source with an output impedance of Rs. Resistors Ri and Rf are used to provide negative feedback. The values are calculated as follows:

Gain G = Rf/Rin, where Rin = Rs + Ri

1/R = 1/Rin + 1/Rf, therefore R= RinRf/(Rin + Rf) R is selected to provide the same impedance to the positive input as the negative.

In the case of a variable Rs, ie feed from a potentiometer, the value of Ri should be selected to be many times greater than Rs, so Rs has an insignificant effect on gain.

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The non-inverting amplifier shown in Figure 10d is driven from a source with an output impedance of Rs. Resistors R and Rf are used to provide negative feedback. The values are calculated as follows:

Gain G = (Rf + R)/R, and R = Rin = Ri + Rs

The differential amplifier shown in Figure 10e has inputs at both inverting and non - inverting ports. This is useful in cases where a signal 0v cannot be directly connected to the amplifier zero volt line, ie buffer amplifiers, or the difference between two separate points which must be amplified. The amplifier produces a positive output when the signal on the positive port is greater than the signal on the negative port. The values are calculated as follows:

Gain G = (Rf + Rin)/Rin, where Rin = Ri + Rs and R = Rf

In cases where a considerable variation in gain is required from a single stage amplifier problems can arise from the impedance imbalance caused by a potentiometer either in the feedback loop or at the input. This can result in excessive drift or instability of the output signal. These problems can be largely avoided if a proportional feedback circuit is used, see fig 11.

To calculate the maximum and minimum values of gain:

At Gain min: G = [(Rf + Rin)/Rin]*(R1 + Vr1 + R2)/(R2 + Vr1)

G = (Rf + Rin)(R1 + Vr1 + R2)/Rin(R2 + Vr1)

At Gain max: G = [(Rf + Rin)/Rin]*(R1 + Vr1 + R2)/R2

G = (Rf + Rin)(R1 + Vr1 + R2)/RinR2 Where R = Rf and Rin = Rs + Ri

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The Parameters of Operational Amplifiers Supply Voltage Range:

This is specified as ±V or +V1 to +V2 note there is always a minimum supply voltage. Input Current:

This is the load current of the inverting and non-inverting inputs measured in nA (this is usually small and can be neglected in most designs). Input Offset Voltage: This is the standing voltage on the input which will be reflected as an offset voltage on the output, this is gain dependant. Input Offset Current: The input offset current will also be reflected on the voltage output it is input resistor and gain dependant. Drift: Input offset current and voltage dependant these figures are not always quoted for general purpose operational amplifiers. Common Mode Rejection: This is the noise rejection of the inputs where both inputs are subjected to the same noise. To minimise common mode noise rejection the input impedances of a differential amplifier should be balanced. Series Mode Rejection: This is the rejection of input noise in terms of current, to minimise the effects of series mode noise the input resistor impedances must be as small as possible. Differential Input Voltage (max): This is the maximum voltage swing the inputs can accept and is also limited by the supply voltage. Power Dissipation (max): The power dissipation of the operational amplifier is mainly affected by the output voltage swing and the output load (as the output impedance is small). The supply volts if significantly higher than the voltage swing will also be detrimental to the power dissipation. Open Loop Voltage Gain: This is the gain of the amplifier before external feedback components are added. It is usually quoted in db. Note: Gain in db = 20logG* where Log10 = 1, Log100 = 2, Log1000 = 3,Log10000 =

4, etc where log = logarithm to base 10. Therefore a gain of 60db ≡ 1000*.

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Slew Rate: This is the response of the output signal to a step change in the input signal

measured in V/µs. Output Voltage Swing (max): This is quoted at a typical supply voltage for the device, and usually is approximately 2V below rail voltages. Gain Bandwidth Product: The frequency at which the output voltage is attenuated by 3db, with the input level constant. The Operational Amplifier as a Summer:

If several signals are to be combined, ie summed these signals can be fed via their own input resistors to an operational amplifier, Fig 12 shows a non inverting amplifier with summing junction.

The gain is set by (Rf + R)/R, and 1/R = 1/(Rs1 + Ri1) + 1/(Rs2 +Ri2).to +1/(Rsn + Rin) where n is the nth input.

The obvious disadvantage with this system is that to balance the input impedances increasingly high input resistors must be used limiting the available gain. The Operational Amplifier as a Comparator When the amplifier is used as a comparator the gain becomes the open loop gain of the device, as no feedback resistor is used. In this mode if the input voltage on the non-inverting + input is higher than the input on the inverting - input then the output voltage will rise to saturation, approximately 2 volts below the supply rail voltage. Conversely when the positive input is less than the negative input to amplifier out will drive negative. It is normal to run the comparator from a single supply so the output switches between 0v and Vs-2V. An example of a comparator is shown in figure 13 where the switching point is set by voltage divider R1,R2. When the input voltage at the + input rises above the voltage set by the divider the output rises from 0V to Vs - 2V. By reversing the inputs the output would switch between Vs -2V and 0V.

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LOGIC

There are two systems in use TTL, transistor logic and CMOS, FET based logic. TTL is generally used in high frequency applications ie computing, and CMOS at lower speeds. The devices are not directly compatible although several hybrid devices are available. If it is necessary to join the two systems the best solution would be to use a transistor in switch mode as a buffer. Advantages and disadvantages of CMOS verses TTL:

TTL 74 Series CMOS 4000 series

Supply: 5V ±10% 3V to 18V Input level: 0 below 0.8V 0 below 0.3Vs

1 above 2V 1 above 0.7Vs Output: will drive 10 gates will drive 10 gates Advantages:

1) Will operate at high frequency 1) Supply variation 3V to 18V 2) Less susceptible to noise 2) Low supply current

Disadvantages:

1) High power consumption 1) Will not operate above 1MHz 2) Rigid supply limits 2) Low output drive current

This subject is discussed in the digital electronics section.

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ANALOGUE CIRCUIT APPLICATIONS OSCILLATORS

An oscillator is basically an amplifier with positive feedback. If the oscillator is driven into saturation a square wave output can be produced whilst sinusoidal oscillators operate within the range of the amplifier. Sinusoidal Oscillators

The crystal oscillator design in fig 1 will operate from 100KHz to the upper frequency limit of the transistor. The advantage of this design is the excellent frequency accuracy and stability afforded by the crystal. The amplifier is collector to base biased and operating as an emitter follower (note

amplifier gain ≥ 1).

At frequencies below 100KHz where it is either impractical to use a

crystal due to size and expense or where a variable frequency output is required a feedback oscillator is a better option, see figure 2.

For a variable frequency oscillator the value of R can be varied between

30KΩ and 1M03Ω, so use a 1MΩ double ganged potentiometer. Further variation can be achieved by range switching the capacitance value.

To produce a sinusoidal waveform the amplifier gain must be adjusted to

exactly 3. At less than 3 there will be insufficient gain to produce oscillation. With the gain above 3 the peak of the waveform will start to clip. Square Wave Oscillators

To generate a square waveform it is necessary to drive the active device ie operational amplifier or transistor into saturation. For the crystal oscillator in fig 1 best results can be achieved by adding another transistor in switch mode.

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To derive a square wave output from the feedback oscillator in fig 6 the

amplifier gain must be increased, ie the value of the feedback resistance increased. Fig 3 shows the output with the gain set to 6 times. The clipped sinusoidal output approximates to a square wave.

By increasing the gain further the clipped sine wave will become a square wave, see fig 4.

In many cases waveforms are not symmetrical or consist of a series of narrow pulses. Figure 5 shows a square wave where the time duration of the pulse, T1 is equal to the time of the space between the pulses T2. The Mark-Space Ratio is said to be equal, ie 1:1 or T1:T2. The repetition frequency f = 1/(T1+T2).

Figure 6 shows a square waveform with uneven Mark-Space Ratio. The mark-space ratio = T1:T2 and the pulse repetition frequency f = 1/(T1+T2).

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ACTIVE FILTERS

Filters are defined as either high pass (HPF, passing high frequency signals), low pass (LPF, blocking high frequency signals), or notch which contains elements of both high and low pass, and can either pass or exclude signals within a narrow band of frequencies.

Figure 7 shows a conventional low pass filter network, combined with a non-inverting amplifier with a gain of 4.3* or 12.db see below: G = (R4 + R3)/R3 = (33K + 10K)/10K = 4.3 To convert Gain to decibels: G = 20 Log 4.3 = 12.6db An Approximation of Fc is calculated as follows:

Fc = 1/(2πRC) = 106/2*3.142*33*103*0.01 = 482Hz Where: R = R1 = R2 and C = C1 = C2. and Fc is the cut off frequency and is defined as the frequency when the gain falls by 3db (-3db point).

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The gain /frequency plot of the low pass filter in figure 1 is shown in figure 8. The slope of the gain or attenuation curve is defined as attenuation per decade of frequency.

A phase shift is associated with the gain frequency plot and is typically

90 degrees at the Fc point. If the positions of C and R (ie C1, C2, R1 and R2) are interposed then the

low pass filter becomes the high pass filter shown in figure 3. Gain and Fc calculations are the same as in figure 7.

Figure 10 shows the Gain/Frequency plot for the high pass filter shown in figure 9. As before the attenuation of the filter is 42db/decade. The Fc value of 380Hz is approximately 20% less than the calculated value whereas Fc was 20% higher for the previous low pass filter.

Inspection of the plots in figures 8 and 10 show the obvious weakness in the conventional design. The amplitude instability as the filter approaches its design frequency would preclude its use in many applications although it may provide a cheaper alternative to more complicated filters.

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To solve the problem of amplitude stability exhibited in the previous filters a design of the type shown in figures 11 to 14 may be adopted. The two stage low pass filter gives an attenuation of 80db per decade with no gain overshoot. Stage gain is carefully selected using precision resistors. The design frequency of the filter is calculated in the same way as the previous design.

Fc = 1/(2πRC) Where: R = R1 = R2 = R5 = R6 and C = C1 = C2 = C3 =C4

For C=0.01µF and R = 1MΩ Fc = 106/2*3.142*1*106*0.01 = 1/0.06284 = 15.9Hz For stage 1: K = 1.152

R3 = (K-1)R4 if R4 = 11K8Ω then R3 = 0.152*11K8 = 1K793Ω

The nearest preferred value to 1K79Ω is 1K78Ω, in practice several values of R4 must be tried to get the best resistor combination for the closest value of K. For stage 2: K = 2.235

R7 = (K-1)R8 if R8 =9K31Ω then R7 =1.235*9K31Ω = 11K498Ω

The nearest preferred value to 11K498Ω is 11K5Ω. Note in selecting values for R3, R4, R7 and R8 the operational amplifier should not be significantly loaded, and the precision resistors should not dissipate more than 1/8 W. Component List

R1 1MΩ 0.25W MF R2 1MΩ 0.25W MF R3 1K78Ω precision MF R4 11K8Ω precision MF R5 1MΩ 0.25W MF R6 1MΩ 0.25MF R7 11K5Ω precision MF R8 9K31Ω precision MF

C1 to C4 0.01µF polystyrene or Silvered Mica

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IC1 and IC2 CA3140 Note for low drift designs it may be necessary to select a low drift operational amplifier.

Figure 12 shows the gain frequency characteristic of the low pass filter example in figure 11. The circuit exhibits excellent gain stability and has an attenuation of 80db/decade at the design frequency. The circuit has a phase

shift of 180° at Fc. The two stage high pass filter design shown in figures 13 and 14 shares the same components as the two stage low pass filter. The calculations are therefore exactly the same.

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Component List

R1 1MΩ 0.25W MF R2 1MΩ 0.25W MF R3 1K78Ω precision MF R4 11K8Ω precision MF R5 1MΩ 0.25W MF R6 1MΩ 0.25MF R7 11K5Ω precision MF R8 9K31Ω precision MF

C1 to C4 0.01µF polystyrene or Silvered Mica IC1 and IC2 CA3140

A single stage inverting or non-inverting filter can also be constructed using a constant factor K of 1.58. For a non-inverting filter interpose + and – pins of the operational amplifier. All filters of this type exhibit a slight gain in the stable region due to the K factor of the filter.

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OPTICAL ELECTRONICS Light Emitting Diodes Gallium phosphide and gallium arsenide phosphide light emitting diodes provide a visible light source when a current is passed through them. Typically for a red LED a value of If, 5mA to 25mA will provide a sufficient light output, with the light output doubling over this range. The forward bias voltage Vf, will be of the order of 1.9V to 3V.

Generally for LED's of different colours and tri-state the current If must be increased. Figure 1 shows LED connection details.

If both the red and green LED's of the tri-state LED are illuminated the resultant colour yellow can be generated. Displays

Rectangular shaped LED's can be formed into a figure eight configuration where seven LED's are connected in either common cathode or common anode mode, see figure 2.

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To produce numbers, segments are powered in the following sequence:

Numbers 1 2 3 4 5 6 7 8 9 0 Segment a 0 1 1 0 1 0 1 1 1 1 b 1 1 1 1 0 0 1 1 1 1 c 1 0 1 1 1 1 1 1 1 1 d 0 1 1 0 1 1 0 1 1 1 e 0 1 0 0 0 1 0 1 0 1 f 0 0 0 1 1 1 1 1 1 1 g 0 1 1 1 1 1 0 1 1 0

where 0 ≡ 0v and 1 ≡ +Vs

Liquid crystal displays are also available. These displays do not emit light but generate black lettering on a silvered background which reflects incident light some displays have backlighting as the example below. The main advantage is extremely low power consumption.

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Photoconductors

If radiation falls upon a semiconductor its conductivity increases. The conductivity of a semiconductor is proportional to the concentration of charge carriers present, radiant energy supplied causes covalent bonds to be broken and additional hole-electron pairs are created. The increased current carriers reduce the resistance of the material, such devices are called photoresistors or photoconductors.

Phototransistor Opto Isolator Phototransistors are commonly used with LED's in fibre optic circuits or

opto isolators, where a pulsed signal is fed to the LED and converted into a light pulse. This is directed to a photo-transistor within the same package or via a fibre optic cable. Figure 3 shows an optical isolator.

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DIGITAL ELECTRONICS LOGIC

Logic circuits are used extensively in modern electronics and replace complicated relay logic previously used. Gate packages are cheap and require few external components. As previously discussed in the integrated circuits section, there are two systems in general use, TTL and CMOS. The two systems operate at different voltage and frequency ranges but the functions are comparable. Definition of Logic Functions: AND: When inputs A and B are high, ie logic 1, output Z is high. This can be

described as the exclusive state as other combinations produce a low output, ie 0v logic 0.

OR: When inputs A and/or B are high then output Z is high. The exclusive state

only occurs when A and B are low ie logic 0, and Z is low. XOR: Defined as exclusive OR, inputs A and B are either both high or both low

output Z is low. When either A or B is high, Z is high. NAND: (Not AND) The output is inverted, ie to produce a low output when A and B

are high. This also enables the gate to be used as an inverting buffer ie A and B connected together.

NOR: (Not OR) The output is inverted so when A and B are both low the output Z

is high. Again connecting A and B will produce an inverting buffer. The symbols of the logic gates together with their truth tables are shown below:-

AND OR XOR NAND NOR A B Z A B Z A B Z A B Z A B Z 1 1 1 1 1 1 1 1 0 1 1 0 1 1 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 0 1 0 0 1 1 1 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1

Most logic designs will require inverting buffers at one stage of the design as the gates must be manipulated to operate at their exclusive state. A good design will minimise gate packages therefore a combination of packages may be used in a design. The example above shows gates with two inputs. Packages are available with up to eight inputs but the operation remains the same ie the exclusive state remains the same. Inverting buffers and non inverting buffers are also available in packages of 6. Figure 1 shows a typical CMOS and TTL package.

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Boolean Algebra Terms A, B, and Z can be expressed in the form of Boolean Algebra as follows:

When A = logic 1, Boolean Expression is A _

When A = logic 0, A

When B = logic 1, Boolean Expression is B _

When B = logic 0, B

where - denotes “not 1”

The gate functions shown on the previous page can be expressed as follows:

AND Z = A.B _ _

OR Z = A.B + A.B + A.B _ _

XOR Z = A.B + A.B _ _ _ _

NAND Z = A.B + A.B + A.B _ _

NOR Z = A.B

Only the values of Z = logic 1 are shown in the equation therefore all other combinations of A and B are equal to logic 0. A truth table can therefore be easily constructed from a Boolean Expression.

The gate combinations shown below can be expressed in the form of a truth

table. All the combinations of A, B, C and D are shown on the left hand side of the truth table, the various output values are shown on the right hand side. For four inputs the number of combinations possible is 16, the binary code formed is expressed by numbers 0 to 15 in the left hand column.

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Truth Table

No A B C D Z1 Z2 Z3 Z4

0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 2 0 0 1 0 0 1 0 0 3 0 0 1 1 0 1 1 0 4 0 1 0 0 0 1 0 0 5 0 1 0 1 0 1 0 1 6 0 1 1 0 0 1 0 1 7 0 1 1 1 0 1 1 1 8 1 0 0 0 0 1 0 0 9 1 0 0 1 0 1 0 1

10 1 0 1 0 0 1 0 1 11 1 0 1 1 0 1 1 1 12 1 1 0 0 0 1 1 0 13 1 1 0 1 0 1 1 1 14 1 1 1 0 0 1 1 1 15 1 1 1 1 1 1 1 1

Z1 = A.B.C.D _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Z2 = A.B.C.D + A.B.C.D + A.B.C.D + A.B.C.D + A.B.C.D + A.B.C.D _ _ _ _ _ _ _ _ _ _ _ + A.B.C.D + A.B.C.D + A.B.C.D + A.B.C.D + A.B.C.D + A.B.C.D _ _ + A.B.C.D + A.B.C.D + A.B.C.D

_ _ _ _ _ _ _ _ Z3 = A.B.C.D + A.B.C.D + A.B.C.D + A.B.C.D + A.B.C.D + A.B.C.D

+ A.B.C.D

_ _ _ _ _ _ _ _ _ _ Z4 = A.B.C.D + A.B.C.D + A.B.C.D + A.B.C.D + A.B.C.D + A.B.C.D _ _ + A.B.C.D + A.B.C.D + A.B.C.D

To optimise the number of packages it is sometimes more practical to use

NAND and NOR logic. Figure 2 shows a circuit using AND gates and inverting buffers, and the equivalent circuit using NAND gates.

When A and B are both 1 and/or C and D are both 1 then Z = 0

If either A and/or B is 0 and C and/or D is 0, then Z = 1

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No A B C D Z 0 0 0 0 0 1 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 0 4 0 1 0 0 1 5 0 1 0 1 1 6 0 1 1 0 1 7 0 1 1 1 0 8 1 0 0 0 1 9 1 0 0 1 1 10 1 0 1 0 1 11 1 0 1 1 0 12 1 1 0 0 0 13 1 1 0 1 0 14 1 1 1 0 0 15 1 1 1 1 0

Timing and Counting

When a pulsed signal is fed into a circuit it is sometimes necessary to condition the signal to prevent double pulsing or to provide a suitable leading edge to trigger the circuit. A Schmitt trigger is sometimes used to condition the input signal where the input voltage "switch on" and "switch off" points are controlled, see figure 3.

Apart from variation in trigger level the Schmitt trigger will produce a

variation in mark to space ratio.

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When an input is fed from a switch or relay it is possible to get a double pulse due to contact bounce, this can be overcome by triggering on the first leading edge and generating a pulse of a suitable width, see figure 4.

At input A = 1, Z1 = 0 and Z2 = 1. The output Z2 is fed back to input B via capacitor C, which holds Z1 at logic 0 until the voltage at B is discharged via resistor R to logic 0. Z1 will then be logic 1 if input A is logic 0, therefore output Z2 is logic 1.

For CMOS logic For TTL logic

Logic 0 below 0.3Vs below 0.8v

Logic 1 above 0.7Vs above 2.0v

The output pulse width T will be equal to 0.7CR for CMOS and (5-0.8)/5 *CR for TTL.

When a Bistable Multivibrator is fed with a trigger pulse it serves to toggle the output between 0 and 1, thus two pulses generate one pulse in phase with the input. A T type flip-flop is a bistable multivibrator with an input T and outputs Q and not Q (ie inverted Q), see figure 5.

If several flip-flops are cascaded it is possible to form a counter as

each stage gives a divide by 2 function. The J K flip-flop shown below is essentially a T type with two additional inputs J, set and K, reset. The J, K inputs only effect the output when a clock pulse is present at input T, see figure 6.

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Note: n represents the number of operations or clock pulses. The Binary System As only 0 and 1 are available it is necessary to count in increments of 2 or in binary, see below. Binary 27 26 25 24 23 22 21 20

Decade 128 64 32 16 8 4 2 1 1 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 1 0 3 0 0 0 0 0 0 1 1 4 0 0 0 0 0 1 0 0 5 0 0 0 0 0 1 0 1 6 0 0 0 0 0 1 1 0 7 0 0 0 0 0 1 1 1 8 0 0 0 0 1 0 0 0 9 0 0 0 0 1 0 0 1 10 0 0 0 0 1 0 1 0

The previous table shows the decimal equivalent of an eight bit binary number. It is possible to generate a maximum count of 11111111 which is equivalent to 255, (1+2+4+8+16+32+64+128).

In order to convert a train of pulses into a binary number it is necessary to pass the input pulses through several stages of a divide by 2 circuit ie flip-flop, which resets after the desired number of pulses. In practice counter logic IC's are available to provide a binary count from a train of pulses, see figure 7.

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Figure 7 shows a 12 bit binary counter with outputs Q0 to Q11, of which only Q0 to Q4 are used to produce a 4 bit binary count.

Q0 to Q3 feed transistor switches which drive LED's to provide an optical indication. Note the output equivalent to 20 is Q0 and 23 is Q3. When the count goes above 1111 or 15, Q4 goes high and resets the counter to 0000. If an 8 bit counter were required then outputs Q0 to Q7 would be connected to the drivers and Q8 would be connected to reset.

The binary number generated by a counter can be converted to drive a digital display using a BCD 7 segment decoder, see figure 8.

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The Binary counter output Q0 to Q3 is fed to the display driver (4511B) and the reset logic. At the count of 10, or 1010 the AND output goes to logic 1 and resets the counter to 0000. The output of the display driver feeds the display via current limiting resistors. If a count greater than 9 is required the reset pulse from the counter can be fed into a duplicate circuit as the trigger pulse. The second display would indicate tens not units as in the first display. The reset pulse from the second circuit could be used to generate 100's if necessary (ie cascaded). Timers

There are several specialised timers available, both CMOS and TTL. The 555 timer illustrated is both CMOS and TTL compatible although many of the functions could be better performed either with a specialised timer or using logic gates.

The timer can be used in three modes timing, as an astable multivibrator, or a monostable multivibrator. The 555 as a Timer

The input circuit of the timer shown in figure 9 produces a negative going pulse into pin 2 of the 555 timer. The timer reset pin 4, is connected to logic 1 to enable the timer. When a input pulse is present the output at pin 3 goes high and the transistor switch at pin 7 is disabled allowing the capacitor C to charge via resistor R. When the voltage reaches the threshold voltage (pin 6), the transistor switch is enabled discharging the capacitor to zero producing a logic 0 at output pin 3.

The time delay can be calculated by assuming that T = 1.5CR approximately. The 555 as an Monostable Multivibrator.

A monostable multivibrator requires a trigger pulse to generate an output pulse. The output waveform will have an equal mark to space ratio.

As before the input network ensures that the trigger pulse is a negative going pulse into pin 2. Reset pin 4 is connected to logic 1 to enable the 555. The output waveform is generated by connecting pin 6 to the input at pin 2 with a suitable capacitor, see figure 10.

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The 555 as an Astable or Free Running Multivibrator.

The 555 operating in this mode acts as a free running square wave

oscillator where T is approximately 0.25CR for values of R between 1K5Ω and 6K8Ω, see figure 11.

This circuit does not always produce an even mark to space ratio, the M-S ratio changes with the values of C and R.

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USEFUL LOGIC CIRCUITS The Latch

The latch retains a logic state until reset. Two examples are shown in figure 12.

For a NAND latch, if A goes from 1 to 0, then Z1 = 1 and Z2 = 0. Z2 holds Z1 at 1 until the latch is reset ie R goes to 0.

For a NOR latch, if A goes to 1, then Z1 = 0, and Z2 = 1. Z2 holds Z1 at 0 until reset R goes to 1. Inhibit

The operation of a gate can be disabled or blocked by controlling one of the inputs, see figure 13.

Figure 13 shows two examples, although this technique can be used for all logic gates. For NAND the output of gate 1 will only change state with input A when the inhibit input I is at logic 1. Gate 2 is connected as an invertor. A = Z when I = logic 1.

For NOR the output of gate 1 with input A when the inhibit input I is at logic 0. Gate 2 is connected as an invertor. A = Z when I = logic 0. Time Delay

A time delay can be incorporated in a logic design by the addition of a resistor and capacitor in a logic circuit as shown in figure 14. Similarly a solid logic 1 can be converted into a pulse by feeding the signal into a series capacitor and discharging through a resistor.

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When the output of invertor 1 goes high capacitor C is charged via

resistor R. The voltage across C rises until it reaches logic 1, and the output of invertor 2 goes to 0. The minimum value of logic 1 for CMOS is 0.7Vs, for TTL 2v at a nominal supply voltage of 5v.

To calculate time delay:

T = 0.7CR for CMOS T = 0.4CR for TTL

The pulse width control circuit shown in figure 4 could equally be described as a timer. If a continuous logic 1 is used as a trigger, ie reset after timing period then input should be fed via a capacitor and discharge resistor, the value of T being much less than that of the timer. Astable Multivibrator. The Astable Multivibrator design shown in figure 15 uses 2 inverting buffers to generate a square wave output. The third invertor provides a buffered output which may not be necessary if the multivibrator is lightly loaded, ie feeding another gate.

Again the pulse width equals 0.7CR so the time between pulses equals 1.4CR, and the frequency F = 1/1.4CR.

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DESIGN

The design of any device requires careful attention to detail. It is not simply enough to design an electronic device to perform a specific function but its packaging and ease of operation must have an equal importance.

In determining the viability of a design the first question a customer will ask will be can it be done, if so when and how much will it cost. In practice the first question is irrelevant as virtually any task imaginable can be achieved with unlimited time and money. The second two questions are interrelated as for a design project to be successful in general there must be a financial advantage in its continued use (or its production). In either case the production cost and unit cost must be balanced with the potential financial gain.

If a new product is to be launched a careful appraisal of the market must be undertaken to determine the financial viability of the project. The measure of a good designer must be that in the words of the old adage that he can produce for £1 what anybody else can produce for £2. The Initial Design Process

In most cases a customer or your superior in the company will propose the initial design project. It is most important that as much information as possible is collated at this time. The following questions should be answered at the first meeting: a) What does the customer intend to achieve with this device. b) Where is the device to be used and by whom, is it to be portable or fixed, ie must it be robust and light, and what are the environmental conditions. What is the level of competence of the operator. c) What is the probable financial return in the use of this device. This can be in terms of time and or money. d) What expenditure will the customer accept, and how quickly must the project be completed. These questions are the most difficult to answer as understandably the customer will be reluctant to give this information especially if more than one company is quoting for the project. The customer may specify an unrealistic time scale, so do not commit yourself at this stage.

Apart from the discipline required formulating a quotation it is desirable at this stage to produce a full specification for the proposed device. This will require a certain amount of development work as the specification produced must be binding on both sides.

The specification should be included in the quotation, but in the event of an internal design it should be approved in writing before work is carried out. This is of great importance as the customer is certain as day follows night to attempt to change the specification as the project progresses. Any additional work resulting from a change in specification should be quoted for separately.

Before any quotation can be produced the design concept must be finalised. In the case of an inexperienced designer it may be helpful to hold a meeting to discuss ways of proceeding with the design. This is often called a Brainstorming session.

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The Brainstorming Session.

In this meeting the designer should present the information obtained in the initial meeting with the customer including if possible an outline specification of the device, ie input, output, operating conditions, size and weight if applicable.

The other persons present at the meeting should be then requested to suggest design solutions, which the designer should note and evaluate after the meeting.

It should be noted that the brainstorming session will be only as good as the people attending the meeting so care should be taken to invite the appropriate experts. Design Evaluation.

An outline design and costing should be produced for each solution so the cheapest solution can be adopted. At this stage the designer must determine whether the design is feasible within the time scale:- a) Are you confident that the design construction and testing of the device can be completed within the time scale. b) Are all the components available, if not what is the delivery time and can the production of the device be planned to take any delays into account. c) Are the skills available to produce the device or will it be necessary to sub-contract parts of the development or manufacture. d) If a Declaration of Conformity is required determine the additional testing requirements for the design. This can add a significant cost to the design project. e) At this stage based on your initial evaluation is it desirable to proceed with the project. You must be convinced that the project can be produced on time and at a profit. To default on the project at a later stage would prove costly and damaging to your reputation.

Once a design has been selected a full specification should be produced. The Specification. The specification should contain the following:- a) Signal input limits where applicable. b) Power Supply requirements including maximum and minimum working voltages, frequency and power factor when applicable. This should also include current loading. c) Environmental Conditions, ie maximum and minimum working temperatures and storage temperatures where applicable. d) Output Information ie accuracy, linearity, hysteresis, temperature drift, noise, maximum and minimum output levels etc. e) User Controls, ie Gain ( or Span ), Zero, etc. These can be expressed as the voltage variation at the output or as a percentage of output.

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f) Packaging Details ie box or housing, size, weight etc.

It is usual to provide an operating manual with any design, which would include this specification. The manual should also provide a description of the design philosophy, operating instructions and limitations of operation together with full circuit, layout diagrams and component lists. The Quotation. This stage is possibly one of the most important parts of the design function, as it must be adhered to. All costs ie design, development, construction etc, must be calculated including the time span of the project ie delivery date. A suitable profit margin must also be allowed for. A quotation should include the following: a) Description of Device b) Specification c) Warrantee ie how long do you take responsibility for its operation. d) Additions ie operating manual, test certificate, declaration of conformity etc. e) Cost and delivery, remember to include costs incurred in the development of the quotation, and allow a margin of error in the delivery time ie determine a reasonable time and double it.

In some cases part of the development and testing costs may be waived if it is considered that further units may be constructed in the future at a similar cost, or it is desirable to gain the contract from this company in order to encourage further work.

Assuming the contract is awarded to you or your company work can begin once you have received the order to start work at the agreed price. At this stage the design must be fully developed before production can begin. Design Development.

Any doubts in the design concept should be addressed at this stage, by experiment and or by consulting manufacturers data. A design analysis programme may also be of use. The initial design process should have enabled the designer to check the viability of his design but at the pre production stage many other considerations must be included in the design: a) How many new and relatively untried components will be used in the design and what is the probable reliability of these components. The incidence of failure of older components is known therefore the larger the content of older technology in the design the more predictable the failure rate of the design, and ultimately the more reliable the design. b) What is the effect of individual component failure within the device. Does the device fail safe. Is it necessary to alarm individual failures or provide a back-up system. c) Is the case or housing the correct size and shape for the device. Could the appearance of the device be improved, and what colour scheme will be used for case and panels. Is it only necessary to change the colour of panels, reducing painting costs. How will panels be labelled, silk screen printing for example is only cost effective for large batch production ( 50+ ).

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d) Having identified all proposed controls will they fit on the panels in a logical fashion (Ergonomics). e) What production methods will be employed in the manufacture of the device. Will printed circuit boards be used or prototype boards. Prototype boards avoid the cost of producing and processing printed circuit board (pcb) artwork but inevitably will result in a loss of reliability and increased production time. For a rule of thumb guide it is generally cost effective to produce printed circuit boards for batches of 3 or more but individual requirements might dictate the use of a pcb for one unit ( ie reliability and strength ). f) The panel labelling artwork must be produced please remember that the appearance of the finished device is almost as important as its function, so great care should be taken to create a superficially pleasing design. g) A production plan or instruction must be produced if the device is produced outside your immediate control. Remember to include a complete component list, circuit and layout diagrams and provide the components or specify the suppliers. Note that delivery times can be a significant factor. Post Production Evaluation.

The device must be thoroughly tested to confirm that it complies with the original specification. An inspection or test report must be prepared on the device showing the measured parameters, and then signed and dated.

In many cases a Declaration of Conformity will be required which will state the relevant British or European standards the device conforms to. It may be necessary to confirm this by testing (in a standards laboratory) and can prove very expensive for small quantities. Another requirement is that the designer or manufacturer retains a conformity file on the device. This document must contain the specifications of all components used in the device with a listing of the appropriate standards. The Operating Manual.

The report or operating manual will be required in almost all cases. The manual has two functions, to allow the safe operation of the equipment and to impart enough information to facilitate repair.

The manual should have a logical format starting with a contents list and ending with any additional information enclosed in an appendix. If the manual is produced for a specific device the appendix could contain the Test Report and Declaration of Conformity. A typical manual format is shown below: CONTENTS: This section should list subject headings in page number

order (include drawings and figure numbers). 1 OPERATION: This section gives a brief introduction to the device ie

use, define inputs/outputs, additional functions etc. 2 SPECIFICATION: Operating limits as previously specified. 3 CIRCUIT DESCRIPTION: Describe operation of circuit. Circuit Diagrams: Layout Drawings: Wiring Schedule:

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Component Lists: Exterior Detail Drawings: 4 CALIBRATION AND OPERATION: How to calibrate and use the device. 5 APPENDIX: Test Data: Test Report: Declaration of Conformity: Contact Address and Telephone number:

The manual format is similar to a report format except the summary and authorisation sheet is not added to the front of the manual, and conclusions and recommendations are omitted. Glossary of Terms Accuracy: This can be defined as the total error over the working

temperature range as a percentage of output. British Standards: The standards published by the British Standards

Institute specify materials and testing procedures. Copies can be obtained from the reference section of major public libraries. I.E.E Regulations must also be complied with (Re Electrical Installation).

Drift: Most electronic devices are affected by drift. Drift is

defined generally by its effect on the output. Two types of drift are prevalent in electronic circuits, long term and temperature. Drift can affect the output voltage offset or the gain of the device if the drift effects the voltage offset it

can be represented by mV/°C or mV/month. If drift effects the gain of the device it can be represented as a percentage error

ie %/°C or %/month. Ergonomics: This is the study of design for human use. If you develop a

good design its operation should be obvious, ie up or clockwise for increase, down or anti-clockwise for decrease, up for off down for on (note in some countries to opposite is true). Controls for a particular channel or operation should be grouped together and labelled clearly. A poor design can result in improper operation or can make the device extremely difficult to operate.

Hysteresis: Some devices exhibit hysteresis where the output from a rising

input has a different characteristic to a falling input. If a graph is plotted of the input/output characteristics the resultant curves would form a leaf shaped envelope.

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Linearity: A device is said to be non-linear if the input\output graph deviates from a straight line. Many analogue electronic devices exhibit some non-linearity. Linearity is expressed as the deviation from the best straight line, as a percentage of output range. Many devices have an error which is minimum at 0%, 50%, and 100% of output range so careful testing is required to identify errors.

Span: This term is generally used where a device is used to drive a

recorder type instrument, where an increase in gain results in an increase in span of the recording device, ie gain equals span.

Zero Offset: This term can be used to define the voltage offset of an

output or an output offset control, units, ñ mV or ñ V. Planning.

It is useful once the final design solution has been selected to produce a plan of the process showing activity against time (see figure 1). The critical path should be marked on the diagram, ie those processes which must be completed before the next stage can begin. It may be useful to flowchart the process as an aid to determining the critical path.

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WORKSHOP PRACTICE I started building electronic equipment as a hobby at the age of 12. As the circuits became more complicated the time spent de-bugging equipment exceeded the build time, if they worked at all. The easy explanation might be faulty components or a poor initial design or possibly even a mistake in reading the circuit design, but in practice the fault usually lay with the idiot using the soldering iron. When soldering components to a printed circuit board or each other a good electrical and mechanical connection must be achieved. It does not follow that more solder or more heat is better in fact the reverse is true. A good soldering technique relies on preparation. 1.0 Useful Equipment Before starting any build a selection of tools must be obtained, and an area prepared to carry out the work. 1.1 The Workbench Any table or existing workbench can be used as long as you feel comfortable sitting at it. It should be faced with hardboard, glossy side up, coated with several applications of varnish. The workbench should be close to a 13A socket outlet preferably at worktop height or power can be fed via an extension lead. The work area should be well lit possibly with an additional desk lamp. 1.2 Hand Tools When making or adapting a case or enclosure the usual mechanical tools are requires ie drills reamers files etc. It is generally better to carry out this work away from the electronic workbench as it should be kept as a clean area. The list below represents the bare minimum tools required to start: 1) Long nosed pliers large. 2) Long nosed pliers small. 3) Side cutters small 4) Cable Stripper 5) Craft knife or scalpel 6) Small crocodile clips 7) Flexible test lead probe with crossover claws 8) Set of screwdrivers, terminal posidrive and flathead 9) Set of needle files 10) Soldering Iron 15 to 25w or temperature controlled soldering station. 11) Solder sucker

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Probably the two most important tools in the list are the soldering iron and side cutters the other tools can be acquired cheaply. The soldering iron should be as small as possible with a range of replaceable tips a 15 watts rated iron is usually adequate. A simple stand can be fabricated using a block of wood and a piece of metal coathanger.

Soldering stations which use a low voltage temperature controlled heating element are available but in my opinion are overly cumbersome and expensive. Soldering Iron And Stand Most standard side cutters are generally too large and not able to cut close to a joint. For electronics work the cutters must be small and made of high quality steel with preferably a spring release. These are best purchased from an electronics supplier. 1.3 Disposables 1) Multicore Solder (electronics grade 18 SWG) 2) Fine Wet or Dry abrasive paper or fine glass paper 3) Flux cleaning solvent 4) Spare soldering iron bits 5) Printed circuit board lacquer 2.0 Construction Methods Small prototype circuits not using integrated circuits can sometimes be constructed using tagstrip, but this construction method is severely limited. For larger designs a printed circuit board or prototype board is necessary. 2.1 Printed Circuit Boards Tagstrip Printed circuit boards (PCB’s) comprise of an insulating board usually fibreglass with a copper film bonded on one or both sides. The part of the copper film required to make connections ie tracks and pads will be coated with an etch resistant coat, then the PCB will be placed in an acid bath to remove unwanted copper. The resulting board can then be drilled to facilitate the assembly of components. In recent years PCB’s have been designed to incorporate surface mounted components which are mounted on top of the tracks without drilling, this facilitates the automatic production process.

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Most PCB’s will be cleaned then passed across a solder bath to coat or tin the copper film. This makes soldering components to the PCB far easier and the joints more reliable. Whether the board is single sided ie copper film on one face only, or double sided, the faces are defined as copper side and component side. Although both sides may contain copper track it follows that to prevent construction errors the component mounting side must be defined.

PCB Copper Side PCB Component Side When designing a PCB layout most designers will treat the design as a single sided board until the number of links required on the component side reaches 5 or 6, above this point it is more economical to produce a double sided board, where small numbers of PCB’s are required. Gone are the days when PCB layouts were produced using different sized sticky tape and pads stuck to clear plastic or tracing paper. Computer programs have been available for the past 15 years which will produce accurate PCB layouts which can be passed to the PCB manufacturer in digital form. Before attempting a layout please check with the local PCB manufacturer to find out which programs are compatible with his system. There are PCB prototyping systems available which enable small quantities of PCB’s to be produced. The process is still relatively expensive and the resulting boards generally of poor quality, these systems are best avoided. Due to the set up process the cost for a PCB manufacturer to produce a small number of PCB’s is very high. The break even point between using a prototype board and designing your own PCB is of the order of five to ten units ie find five to ten people who also wish to build the circuit.

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2.2 Prototype Boards Prototype boards are effectively general purpose PCB’s and are available from most electronic suppliers. The boards are constructed of an insulating material with a 1oz or 2oz copper film bonded to one or both sides of the PCB. The boards are drilled to take components on a 0.1 inch grid and are available in two distinct types, veroboard or stripboard which has copper strips running the length of one side of the board and development boards which are designed to accommodate DIL integrated circuits. Development or Prototype Board Veroboard is generally the cheaper of the two options but is more difficult to use as the parallel tracks must be cut using a track cutter or 3mm drill to form the circuit and the close proximity of adjacent tracks requires great care when soldering components on the board. Additional connections can be made using solid insulated wire. Connections to and from the board should be made with multi stranded insulated wire (7/0.2 or 16/0.2). Veroboard or Stripboard Prototype (matrix) boards are also available with no copper tracks. Components can be assembled using a combination of soldering and wire wrap techniques. Wire wrapping involves tightly wrapping wire around a square section conductor relying wholly on mechanical grip for the electrical connection. This technique allows the faster assembly of the prototype but is expensive and unreliable.

Wire Wrapping. 3.0 Soldering and Assembly Techniques 3.1 Preparation There is a natural tendency once you have assembled all the components to rush into building the circuit, but to be successful care should be taken in your preparations. The first stage should be to measure all the components and their lead spacing (see the next section). It might seem overly pedantic but work in imperial units most components and all of the prototype boards are designed that way and multiples of 0.1 inches are easier to read than 2.54mm. Using different colour pens draw the circuit layout including component dimensions. It may help to use squared paper or graph paper.

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Example of a Simple Layout on a 0.1 inch Grid When drawing a layout especially for high frequency circuits keep the connections as short as possible. Remember long parallel leads can provide an unwanted path to an adjacent circuit due to capacitance. Oscillators especially can provide high frequency noise to the rest of the circuit. A small polyester or ceramic capacitor (say 0.1uF to 1uF) connected across the power feed ie V to 0v, as close as possible to the source of the noise should considerably reduce the problem, so make allowances in the layout drawing. When the drawing is complete check it carefully against the circuit diagram as from now on mistakes can be expensive both in time and money. Please always retain you layout drawings as if anything goes wrong they will be needed. 3.2 Assembly Most components can be horizontally or vertically mounted on the board but unless space is at a premium it is generally better to mount horizontally. When preparing passive components and diodes for mounting grip the component lead close to the body using small long nosed pliers and bend the remaining part of the lead as required.

Horizontal Mounting Vertical Mounting It is better to assemble a reasonable number of components before soldering therefore when the component is in position bend the leads on the underside of the board slightly to retain the component.

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When positioning integrated circuit bases it is better to position the base then solder two pins to the board while holding the base. Later when soldering the whole base solder the two original pins properly. Remember pin 1 is marked or a semicircle is cut in the moulding at the top of the base. I prefer to position all the bases first without other components to get in the way. Don’t try to save money by soldering integrated circuits directly to the board they can be easily damaged and you may need to remove them when testing the board on completion of the project. Turned pin DIL sockets are generally the most reliable.

Turned Pin Duel In Line Sockets Most discrete semiconductors ie diodes and particularly transistors are vulnerable to heat therefore additional care must be taken when soldering. Whenever possible solder these components last and allow the component to cool after each joint. If the semiconductor is to be soldered to a large area of track or tag, soldering time will be increased, and it may be necessary to sink some of the heat by clipping a crocodile clip or probe on the lead close to the component. Connections to and from the board should be made in multistrand cable. Again keep these connections reasonably short for high frequency applications. For audio circuits low level signals should be connected with screened cable.

Keep lead angle from the vertical As small as possible.

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3.3 Soldering Before starting work give the soldering iron enough time to heat up properly, test the temperature by applying multicore solder to the bit. The solder should flow easily when the iron is up to temperature. Before soldering anything ensure that the components to be soldered are clean and free of oxide. Printed circuit boards, not already tinned can be cleaned with paper, stubborn areas can be polished with a fine abrasive paper but be careful the copper layer is very thin. Connectors on switches, potentiometers etc can also be cleaned with a fine abrasive paper if absolutely necessary. Component leads generally will not require cleaning especially if the component is new. Multicore solder contains flux within the solder wire, when heated the flux will flow fractionally before the solder. The flux has two functions to coat the area to be soldered to prevent oxide build up and to facilitate the flow of the solder. A common fault when soldering is to apply solder to the bit and then attempt to stick two components together. This can sometimes be done to temporarily hold a component in position ie DIL sockets on a PCB but will inevitably result in a poor joint sometimes called a dry joint.

Dirty Bit Clean Bit When soldering first clean the soldering iron bit by applying a small amount of multicore solder to the bit and wiping the bit on a damp sponge. The bit should then appear shiny with no pitting. If the surface is damaged temporary repairs can be made with abrasive paper then repeating the process but it is better to accept the inevitable and change the soldering iron bit immediately. Allow the soldering iron to cool down then fit a new bit and re-heat and tin the new bit. In many cases a new soldering iron bit will not immediately tin properly if this is the case hold a piece of paper flat on the workbench and polish the bit adding solder occasionally until the tip of the bit is properly tined and has a shiny finish, do not use abrasives as this will permanently damage the bit.

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Hold the soldering iron as you would a pen or pencil only providing enough force to maintain contact with the work piece.

Soldering techniques vary slightly between connecting two components together and a component to a PCB. When connecting two components tin the contact area of each of the components after first cleaning the bit on the damp sponge. Apply multicore solder to the component and the bit with the bit in contact with the area to be tinned. The tinned area of the component should appear shiny and have a consistent coating. Repeat the process with the second component then with the components in position apply sufficient heat to join them, applying additional solder as necessary. At first sight it may appear that you need three hands but remember you can usually use the soldering iron in its stand, or use a small vice to hold the component. A probe or crocodile clip can also be useful. When soldering components to a PCB locate the components on the component side then push the leads through the holes. To retain the components bend the leads slightly on the copper side, this should prevent movement when you turn the board over to solder it. To solder the component to the board, clean the bit then position the bit on the track and the component lead then apply the solder to the joint. Never use more solder than absolutely necessary as it can result in bridging of tracks on the board. It is usually possible to do two or three joints in this manor before cleaning the bit but do not allow surplus solder to remain on the bit.

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Dry Joint, Solder Surface Appears Good Joint Solder Surface Appears Rounded or Convex. Concave The resultant joints should appear shiny not matt and have a concave appearance. If they appear convex or rounded solder them again using a solder sucker if necessary as dry joints are mechanically weak and can sometimes have a high electrical resistance. Dry joints are usually the cause of intermittent faults. On completion always switch off the soldering iron and put iron and stand in a safe place to cool down. Using side cutters trim off all unwanted component leads from the copper side of the board. 4.0 Testing Having spent hours making your project the natural tendency is to apply power and switch it on. DON’T DO IT. The first step should always be to remove all debris from the workbench or testing area to limit the chances of short circuits, then follow the procedure listed below: 1) Using layout and circuit diagrams check for accuracy. 2) Inspect all joints and ensure that there are no dry joints or inadvertent short circuits. 3) Switch on power supply set and check voltage levels. 4) If you are using integrated circuits check that they have not yet been inserted into the DIL sockets. 5) Connect your project to the power supply double check your connections before you switch on.

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6) Using a voltmeter check voltage levels at power rails and at each DIL socket. If the supply voltage differential is less than 50v, run the tip of your finger over all the components to check for overheating. 7) Plug in the Integrated circuits stage by stage testing each stage before plugging in the next. Note it is advisable to disconnect the power supply before plugging in each integrated circuit. 5.0 Finishing If your project is to be used in damp conditions it is advisable to coat vulnerable parts with printed circuit board lacquer. Before starting clean and de-flux the PCB, mask any clear plastic wafer switches and integrated circuits. The easiest way to mask integrated circuits is to fit masking tape to the top of the plastic covers that are supplied with the IC’s. It is advisable to spray lacquer in a well ventilated area if this is not possible lay newspaper across the top of your cooker and use the extractor fan to remove fumes. When spraying apply several light coats to both sides of the board allowing drying time between coats.

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DESIGN EXAMPLES

1) Light Sensitive Switch

Using a light dependant resistor design a light sensitive switch to operate a security light, internal or external, during hours of darkness. The light switch should be capable of switching 500w at 240V ac, and utilise an existing 12v dc supply.

Component Data:

SPNO Relay Tr1 BC109 D1 IN4001

Contact Rating 6A/250v ac Ic = 100mA I = 1A

Coil Resistance 720Ω Vcbo = 30v Vb = 100v Operating Volts 8.4v to 27.6v Vceo = 20v

hfe = 200 to 800

D2 LDR1 NORP12 NSL19

Red 10 Lux 9KΩ 20KΩ to 100KΩ Vf = 1.9v 100 Lux ---- 5KΩ If = 10mA typ 1000 Lux 400Ω ----

If = 30mA Max Dark 1MΩ 20MΩ

Calculating Ic (Tr1 collector current) Vsupply = 12v, For D2 Vf = 1.9v, Therefore Voltage RL1 coil = 10.1v Ic = Vc/Rc = 10.1/720 = 14mA (for diode D2 If 10mA to 30mA)

Tr1 base current Ib = Ic/hfe = 14/200 mA to 14/800 mA. = 70µA to 17.5µA Option 1 use voltage generated by resistor divider R1, VR1/LDR1 to switch transistor Tr1 (see fig 1).

For Tr1 to conduct: Vb ≥ 0.6v and Ib ≥ (17.5µA to 70µA) Selecting LDR1 as NORP12

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Nominal Switching point LDR1 = 9KΩ (Vb = 0.6v) so Ildr = 66µA

and I(R) = 66µA + 17.5µA = 83.5µA to 66µA + 70µA = 136µA Where R is the combined resistance of R1 and VR1. Therefore R = (Vsupply - Vb) / I at nominal switching point.

R = 11.4/0.0835 KΩ or 11.4/0.136 KΩ = 137KΩ to 84KΩ

Adjustment for switching point LDR1, say 4K5Ω to 100KΩ

At LDR1 = 4K5Ω, Ildr = 0.6/4K5 =133µA

At LDR1 = 100KΩ, Ildr = 0.6/100K = 6µA

At LDR1 = 4K5Ω, R = 11.4V/(133+17.5) µA = 76KΩ to 11.4V/(133+70) µA = 56KΩ

At LDR1 = 100KΩ, R = 11.4/(6+17.5) µA = 485KΩ to 11.4/(6+70) µA = 150KΩ

For full adjustment R must vary between 56KΩ and 485KΩ therefore select VR1 500KΩ and R1 47KΩ. NOTE: Although it is possible to achieve adequate adjustment it would be difficult to set up for precise light levels as a high proportion of the adjustment is allowing for gain variations in the selection of the transistor. It is not practical to use the cheaper NSL19 LDR in this circuit. Option 2 (see Fig 2) Use an Operational Amplifier as a comparator. IC1 output (for on state) is 10v (supply voltage less 2V)

therefore R4 ≤ 10/0.07 KΩ = 143KΩ

Let R4 = 20KΩ

If LDR1 Resistance Variation is 4K5Ω to 100KΩ make 100KΩ equiv to 6v into pin 3 of IC1, therefore R1 = 100KΩ at 4K5Ω and Vp3 = 12 * 4K5/104K5 = 517mV. IC1 is configured as a differential amplifier with a gain equal to the open loop gain of the amplifier (a comparator). When the voltage on pin 2 is less than the voltage at pin 3 the output will rise to the saturation voltage of the device typically 2v below supply voltage.

To allow the specified adjustment, select VR1 = 10KΩ, R2 9K1Ω, R3 750Ω As fig 2 is more flexible than fig 1 NSL19 can also be used.

LDR1 variation becomes 10KΩ to 1MΩ therefore Let R1 = 270KΩ. Then maximum volts at IC1 pin3 = 9.5v. Minimum voltage at pin 3, IC1 = 12 * 4K5/274K5 = 0.197v

Select VR1 10KΩ: then voltage across VR1 = 9.5V-0.2V therefore

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R3= 0.197 * 10/9.3 KΩ = 212Ω, preferred value 200Ω R2 = 2.5*10.2/9.5 KΩ = 2K68Ω preferred value 2K7Ω The power rating of the resistors needs to be determined. The easiest way is to calculate the value of resistance for standard power ratings at the supply voltage.

For Power 1W, P = V2/R therefore R min = 12*12/1= 144Ω For Power 1/2W, P = V2/R therefore R min = 2*12*12/1 = 288Ω For Power 1/4W, P = V2/R therefore R min = 4*12*12/1 = 576Ω

By inspection only R3 is below 576Ω and R3 is part of a voltage divider which is well within tolerance.

Component List: Fig 1 Fig 2

R1, 47KΩ 0.25w MF R1, 270KΩ 0.25w MF VR1, 500KΩ 20t cermet trimpot R2, 2K7Ω 0.25w MF LDR1, NORP12 R3, 200Ω 0.25w MF Tr1, BC109 R4, 20KΩ 0.25w MF D1, IN4001 VR1, 10KΩ 20t cermet trimpot D2, Red LED Vf 1.9v, If 10-30mA LDR1, NORP12 or NSL19 RL1, SPNO 6A/250v Tr1, BC109

IC1, CA3140 D1, IN4001 D2, Red LED Vf 1.9v,If 10-30mA RL1, SPNO 6A/250V

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2) Temperature Controller

Using a NiCr/NiAl K type thermocouple design a temperature controller for

a small industrial oven to be controlled between 100°C and 400°C. To prevent constant switching a controllable dead band should be incorporated in the design. The oven is rated 5A\240v. Note a thermocouple cold junction reference should be included in the design.

Component Data:

SPNO Relay Tr1/2 BC109 D1 IN4001

Contact Rating 6A/250v ac Ic = 100mA max I = 1A

Coil Resistance 720Ω Vcbo = 30v Vb = 100v Coil Volts 8.4v to 27.6v Vceo = 20v

hfe = 200 to 800

D2 K type T/C 3140 BiMOS opamp LM35DZ

Red LED 4mV per 100°C Vs = +4 to +36v Temp sensor

Vf = 1.9v Max temp = 400°C OL Gain = 100 db 0 to 100°C If = 10mA Vs = +4v to +30v

If 30mA Max Vo 10mV/°C Calculating Ic (Tr1 collector current) supply = 12v, For D2 Vf = 1.9v, Therefore RL1 coil voltage = 10.1v Ic = Vc/Rc = 10.1/720 = 14mA (for diode D2, If = 10mA to 30mA)

Tr1 base current Ib = Ic/hfe = 14/200 to 14/800 mA. = 70µA to 17.5µA Maximum output Volts for IC3 and IC5 is 2v below supply voltage (12 - 2) = 10v.

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Maximum value of transistor drive resistor = 10/70 MΩ =142KΩ. Minimum value based on maximum load of IC3 and IC5 1KΩ.

So select R15 and R16 10KΩ and R14 20KΩ.

As thermocouple output is 4mV per 100°C, the output of IC1 (10mV/°C) must be attenuated by a factor of 250:1. Let R2 = 100Ω, then R1 = 24KΩ

The input at R3 varies between ambient 25°C, (1mV) and 400°C, (16mV). Let gain of IC2 = 250* then maximum output 4v nom. This is necessary to improve the signal to noise ratio before the signal is fed into the comparator. A low signal level would also be detrimental to the switching speed and accuracy. Gain = (R4 + R5)/R4 and R source + R3 = R4

Note max value R5 1MΩ therefore max value R4 3K9Ω.

Select R4 = 3KΩ then R5 = 747KΩ, preferred value 750KΩ. Gain = 251*

R source can be considered as R2 + Rtc = 200Ω, R3 = 3KΩ - 200Ω = 2K8Ω preferred value 2K7Ω

At 100°C the output of IC2 becomes 1.004v and 4.016V at 400°C.( ie 10mv/°C) IC3 is an amplifier with no feedback resistor to limit gain thus gain is equal to the open loop gain of the amplifier (100db, 100000000000* approx). When the positive input is higher than the negative input the output will rise to its saturation voltage of 2v below supply rail. The amplifier may be considered to be operating as a comparator. The voltage across VR1 (temperature control setting) must be equal or greater than (4.016-1.004). The voltage across R7 must be less or equal to 1.004v, to achieve control range.

Let VR1 = 1KΩ then i ≥ 3.012/1 mA, and R7 ≤ 1.004/3.012 ≤ 333Ω.

To allow adequate control let R7 = 300Ω (a 330Ω resistor could be greater than 333Ω due to the resistor tolerance). To calculate R6 the maximum voltage at the positive terminal of IC3 must be equal or greater than 4.016v and voltage across R6 must be less or equal to 12v - 4.016v = 7.84v. i = 4.016/(1K + 300) = 3.09mA

R6 ≤ 7.84/3.09 KΩ ≤ 2K54Ω preferred value 2K4Ω. Therefore I = 12/(2.4+1+0.3) mA = 3.243mA Control variation = I*R7 to I*R7 + I*VR1 = O.973V to 4.216V.

Temperature Control 97°C to 422°C. To apply a dead band the output from IC3 must be inhibited. This is achieved by Tr2 pulling down the output of IC3 via R15. When the temperature signal is close to the control signal. The error signal differential amplifier IC4, is saturated (output 10v) until the error signal is reduced to the range of the amplifier in this case, approximately twice the required dead band. The Dead Band is selected

at 1 to 10°C.

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The switching level can then be set via resistance chain R12,VR2 and R13, which sets the switching level of IC5.

To determine error amplifier gain (IC4), Calculate Vin for 2 * 10°C, as the output of IC2 is equivalent to 10 mV/°C,Vin = 200mV at 10v output. Therefore gain of IC4 = 10/0.2 = 50* G = (Rin + Rf)/Rin Where Rin = Rs + R8 = Rs + R9 as the source impedances are different it is necessary to make the values of R8 and R9 as large as

possible for Rf not greater than 1MΩ.

As the Gain is 50 * nom, Rin max = 20KΩ. Gain = (1M + 20K)/20K = 51*

Selecting Resistors: R8 = 20KΩ, R9 = 20KΩ, R10 = 1MΩ, R11 = 1MΩ.

The Error Amplifier Output becomes 5.1v at 10°C, and 0.51v at 1°C.

Let VR2 = 1KΩ then I = (5.1v - 0.51)/1 mA = 4.6mA

R13 = 0.51/4.6 KΩ = 110Ω, R12 = (12 - 5.1)/4.6 KΩ = 1K5Ω

Note C1 and C2 are selected at 0.1µF to limit high frequency noise in the circuit. D1 prevents back EMF generated by the inductance of the relay coil. The power rating of the resistors needs to be determined. The easiest way is to calculate the value of resistance for standard power ratings at the supply voltage.

For Power 1W, P = V2/R therefore R min = 12*12/1 = 144Ω For Power 1/2W, P = V2/R therefore R min = 2*12*12/1 = 288Ω For Power 1/4W, P = V2/R therefore R min = 4*12*12/1 = 576Ω

By inspection only R2, R7 and R13 are below 576Ω and all these are part of a voltage divider, which is well within tolerance. Component List (Temperature Controller):

C1 and C2, 0.1µF ceramic or polyester

R1, 24KΩ 0.25w MF R2, 100Ω 0.25w MF R3, 2K7Ω 0.25w MF R4, 3KΩ 0.25w MF R5, 750KΩ 0.25w MF R6, 2K4Ω 0.25w MF R7, 300Ω 0.25w MF R8, 20KΩ 0.25w MF R9, 20KΩ 0.25w MF R10, 1MΩ 0.25w MF R11, 1MΩ 0.25w MF R12, 1K5Ω 0.25w MF R13, 110Ω 0.25w MF R14, 20KΩ 0.25w MF R15, 10KΩ 0.25w MF R16, 10KΩ 0.25w MF Tr1,Tr2 BC109 D1, IN4001 D2, Red LED, Vf=1.9v If= 10-30mA

VR1, 1KΩ linear potentiometer VR2, 1KΩ linear potentiometer IC1, LM35DZ IC2 to IC5, CA3140 RL1, SPNO, Contact Rating 6A\240V, Coil 8.4v to 27.6v T/C, K type.thermocouple

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3) Loudspeaker Delay Switch

Using a double pole change- over relay with contacts rated at 5A/30v dc, design a timer to inhibit loudspeaker connection during "switch-on" of a stereo amplifier. Time delay should be greater than one second. Where possible the stereo amplifier power supply should be utilised.

Component Details: Relay 5A DPCO, coil 8.8v to 18v

220Ω Tr2 2N3053, Ic = 700mA, Pt = 5W

hfe = 50-250 Vce =10v Tr1 BC109, Ic = 100mA, Pt = 300mW

hfe = 200-800, Vce=5v

RL1 Volts = 12v, Assume that supply volts Vs = 15v, Then voltage across R2 = 3v I(Relay) = 12/220 = 54.55mA nom

R2 = 3/(54.55) KΩ = 55Ω preferred value 56Ω

The choice of the relay with a coil resistance of 220Ω requires a medium power transistor to drive it. This transistor has a hfe of 50 which requires a base current of 1.1mA to drive it into saturation. To achieve this with one stage a very large and expensive capacitor would be required.

Assume Ib2 = 1mA then Ie1 = 1mA and with hfe 200, Ib1 = 5µA Ie1 = Ib1 + Ic1 therefore Ic1 = 1 - .005 mA = 0.995mA Relay current I(Relay) = Ic1 + Ic2 and I(R2) = Ic2 + Ib2 as Ib2 = Ic1 + Ib1

Then I(R2) = I(Relay) + 5µA, as 5µA is small it can be ignored.

If I(Relay) ≡ I(R2) then I(R2) = 15/(220 + 56) A = 54.35mA The Voltage across R2 = 56 * 54.35 mV = 3.04v at Power P = 165mW The Voltage across C1 = 3.04 + 0.6 + 0.6 = 4.24v T = C1*R1 where T is the time in seconds to reach Vs. To drive Tr1 “ON”: V(R1) = (15-4.24)v = 10.76v at Ts = 4.24C1*R1/15 where Ts is the time to “switch on” Tr1.

Therefore Ts = 0.28C1*R1 as I(R1) ≥ 5µA, R1 ó 10.76/5 MΩ = 2M15Ω

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for R1 = 2MΩ and C1 = 10µF, Ts = 0.28*2*10 = 5.6s for R1 = 1MΩ and C1 = 4.7µF Ts = 1.3s Let R1 = 1MΩ 0.25w MF, R2 = 56Ω 0.5W MF, C1 = 4.7µF, 16v wkg Components List:

R1, 1MΩ 0.25w MF, R2, 56Ω 0.5W MF

C1, 4.7µF, Tantalum 16V dc wkg

RL1, 5A/220Ω D1, IN4001 Tr1, BC109 Tr2 2N3053,

Page 97: Electronics Made Easy

4) Transistor Tester

Design a transistor tester to determine transistor current gain (hfe) and lead connection. The tester should be capable of testing both PNP and NPN transistors. The transistor tester should be powered from a bench power supply providing 12v to 15v dc, but it would be desirable to design a battery option for this unit ie 9v PP3.

Fig 5 Transistor Tester Component Data:

D1, Zener BZX79 Tr1, BC478 PNP D2, LED Amber Vz = 7.5v hfe = 110-450 If = 20mA (10mA Typ) Pt = 500mW Vce = -5v Vr = 3v

Temp Coeff 4mV/°C Ic = -150mA For NPN Transistors Rc = R4 + R3 and Rb = R7 + Vr1 and SPDT switch selects “NPN” + 7.5v. When Vr3 = 0.6v Tr1 is switched on and D2 illuminated via R5. With the switch selected to “PNP” 0V, Rc = R6 and Re = R3, Rb = R7 + Vr1. When the voltage across R3 = 0.6v the LED is switched "on". Note: Rb is base resistor, Rc is collector resistor and Re is emitter resistor. With the transistor connected correctly Vr1 can be adjusted for LED "on". In any other position the LED is either permanently on or off. When the LED is switched fully on the pot position indicates gain. For Zener Voltage 7.5v: R4 and R6 = (7.5 - 0.6)/Ic

Page 98: Electronics Made Easy

If R4 = 1KΩ then Ic = 6.9mA. R3 = 0.6/(6.9 + Ib1) KΩ. As Ib1 is small R3 = 87Ω with the test transistor saturated. For the transistor to operate out of

saturation, let R3 = 120Ω.

Ic1 = 10mA then R5 = (7.5 - 3)/10 KΩ = 450Ω preferred value 470Ω. Total circuit load = 17mA. For a 15V supply the maximum Zener diode current Id1 max = 66mA at 500mW.

R2 = (15 - 7.5)/(17 + 66) KΩ = 90Ω min

For a 12V supply R2 = (12 - 7.5)/27 = 167Ω max

Let R2 = 120Ω, at 0.5W.

For a 9v, PP3 battery, V = 8.2v to 9.5v, R1 = 0.7/27 KΩ = 26Ω max R1 = 2/83 KΩ = 24Ω min. Let R1 = 24Ω 0.5W preferred value.

To reduce high frequency noise C1 = 0.1µF. To determine Gain: Voltage across Rb or (R7 + Vr1) = 6.9v. Ic = 0.6/R3 = 0.6/120 A = 5mA (at LED on)

Rb = 6.9/(Ic/hfe) = 6.9hfe/5 KΩ = 1.38hfe KΩ

Resistance Ω Rb Vr1

hfe

1K38 0 1 2K76 1K56 2

6K9 5K7 5

13K8 12K6 10 27K6 26K4 20

69K 67K8 50 138K 136K8 100

276K 274K8 200 690K 689K 500

1M104 1M103 800

1M38 1M379 1000 Component List

R1, 24Ω 0.5W MF R2, 120Ω 0.5W MF R3, 120Ω 0.25W MF R4, 1KΩ 0.25W MF R5, 470Ω 0.25W MF R6, 1KΩ 0.25W MF R7, 1K2Ω 0.25W MF Vr1, 1MΩ Log potentiometer

SW, SPDT Turned Pin 14w DIL Skt (cut down to 10 way)

C1, 0.1µF polyester or ceramic

D1, BZX79 7V5 D2, Yellow LED Tr1, BC478

Page 99: Electronics Made Easy

5) NiCad Battery Charger

Design a current driver capable of charging all common nicad batteries to be powered from a 1A bench power supply 5v to 18v dc (nominal setting 12V). Typical charging rates are shown below:

PP3 9mA, PP9 100mA, AA 45mA, C 150mA, D 350mA, RR 140mA.

Component Data:

Tr2, BU406 Tr1, BC109 IC1, CA3140 D1, ZN458B Hfe = 20 min hfe = 200-800 OL Gain = 100db I = 2-120mA Vce = 10v Vce = 5v Vs = +4 to +36v Vref = 2.45v

Iop = 12mA Drift = 29ppm/°C Noise = 10µV rms

The transistor Tr2 is switched on when the voltage across R3 is less than the reference voltage to the + input of IC1. The input power supply voltage (5v to 18v), should not exceed 10v above cell voltage ie the battery to be charged, or transistor Vce will be exceeded. If the supply voltage is less than 4v above cell voltage there may be insufficient current drive. Select Maximum Current, say 400mA. Then select a low value resistor for R3 (improves range reduces power dissipation).

Let R3 = 1.5Ω. At maximum output, 400mA, Vr3 = 0.4*1.5v = 0.6v, P = 0.6*0.4 = 0.24W

Let R3 = 1.5Ω 0.5W MF. D1 produces a reference voltage of 2.45v. Voltage across R3 = 0 to 0.6v for drive current of 0 to 400mA. For control range Vr1 must produce 0 to 0.6v.

If Vr1 = 100K then current through Vr1 = 0.6/100 mA = 6µA.

Select C1 = 0.1µF to reduce high frequency noise.

R4 = (2.45 - 0.6)/0.006 KΩ = 308KΩ preferred value 330KΩ

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D1 ref Current Ir = 2.45/(100+330) mA = 5.7µA and Vr1 range 0 to 0.57v. Therefore Maximum Current Drive = 0.57/1.5 A = 380mA.

If the value of R4 300KΩ Then:

D1 ref Current Ir = 2.45/(100+300) mA = 6.125µA and Vr1 range 0 to 0.6125v. And maximum current drive = 0.6125/1.5 A = 408mA

From Data D1 current is 2mA to 120mA. At supply 5v and Id1 2mA, R1 = 5/2 KΩ = 2K5Ω max. At supply 18v and Id1 120mA, R1 = 18/120 K = 150Ω min

Let R1 = 1KΩ. As IC1 cannot provide enough current for Ib2 it must feed the base of Tr1. Tr1 and Tr2 are connected in darlington mode with current limiting resistor R2. If Tr2 has hfe 20 then for current drive of 380mA Ib2, and Ie1 = 380/20 mA = 19mA.

If Tr1 has a gain of 200 then Ib1 =95µA. The Vce of Tr1 (BC109) = 5v therefore at Tr2 with a Vce 10v, R2*Ib2 + 5v = 9.4v,

R2*Ib2 = 4.4v as Ib2 = 19mA, min value of R2 = 231Ω, Preferred value 240Ω. Note: To reduce power dissipation in the transistors it is better to select the minimum power supply voltage to drive the charging current ie 3 or 4 volts above cell voltage (maximum 10v).

Tr2 should be provided with a heat sink of approximately 10°C/W. Component List

R1, 1KΩ 0.25W MF R2, 240Ω 0.25W MF R3, 1.5Ω 0.5W MF R4, 330KΩ 0.25W MF

Vr1, 100KΩ 10t linear potentiometer

C1, 0.1µF poly or cer D1, ZN458B Tr1, BC109 Tr2, BU406 IC1, CA3140

Heat sink, 10°C/W

Page 101: Electronics Made Easy

6) Design a Bench Power Supply with a variable regulated voltage output from 5V dc to 18V dc, at current 1A. The supply output should be displayed on the front panel.

Component Data:

D1 BZX79 Zener D2 Red LED D3 BZX79 Zener IC1 CA3140 Vz = 5.1V Vf = 3V Vz = 10V Vs +4V to +36V

-0.8mV/°C If = 10mA 6.4mV/°C OL Gain 100db Pt = 0.5W Ifmax = 30mA Pt = 0.5W

REG1 LM317T REC1 Diode Bridge T1 Transformer Sw1 DPDT Vin Max = 40V 1.6A, 100V Prim 240v/110v 240V/2A Vdiff = 2.3V Sec 2* 20v,0.5A Min Load = 3.5mA Droop at FL 7% Ripple Rej = 80db Therm Res 4øC/W T max 125øC

Transformer Rating 20VA at sec assume 22VA at primary. Therefore Iin = 100mA So select fuse 250mA. Calculating the value for C1: CV = IT where V = Vripple and T = 1/2F Vac at T1 sec = 20V rms Bridge output = 20 * 1.414 -Vbridge = 28.28V - 1.2V = 27.08V dc Transformer droop at full load 7% so min DC voltage = 0.93*28.28 – 1.2 = 25.1V. Min Vin for 18V output = 2.3V + 18V = 20.3V. Acceptable ripple Vr pkpk = 25.1-20.3V = 4.8V pkpk = 1.7V rms.

C1 = 1 * 10 * 10-3/1.7 F = 5882µF, preferred value 6800µF 35V DC wkg. Assume Vref to REG1 = 1.5V below Vout. therefore Vref = 3.5V to 16.5V. As the zener voltage Vz of D1 = 5.1V, gain of IC1, G1 = 16.5/5.1 G1 = 3.235 = (R4 + R5)/R4 where R4 = R3 + Rin

If R4 = 10KΩ then R3 = 10KΩ as Rin small in comparison with 10KΩ

3.235*10K = 10K + R5, therefore R5 = 22.35KΩ preferred value 24KΩ and G1 = 3.4

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Voltage across R2 = 3.5/3.4 V = 1.03V To calculate the values of R1, R2 and Vr1:

Let Vr1 = 1KΩ, Voltage Swing = (5.1 - 1.03)V = 4.07V Ivr1 = 4.07mV.

R2 = 1.03/4.07 KΩ = 253Ω preferred value 240Ω then Ivr1 = 5.1/(1K + 240) Ivr1 = Ir2 = 4.11mA. D1 Pt = 0.5W therefore Iz max = 0.5/5.1 = 98mA D2 If max = 30mA, If typ = 10mA. let If = 14 mA,

then R1 = (Vin - Vz - Vr)/If = (27.08 - 5.1 - 3 )/14 KΩ = 1.36KΩ

R1 = 1K2Ω preferred value. If = 15.8mA at no load. Pt = 300mW use 0.5W At 1A output Vin will drop to 27.08 - 0.07*28.28 = 25.1V therefore If = 17/1.2 mA = 14.1mA at 1A output. The max power dissipation of REG1 will occur at 5V 1A where the voltage across the regulator = 20.1V, Pt = 20.1*1 = 20W.

The Thermal Resistance of LM317T is 4°C/W and maximum operating temperature

125°C. It is desirable to reduce this value considerably by using a heat sink or case mounting the regulator. R9 is required to satisfy the minimum load requirements of the regulator.

At 5V out Imin = 3.5mA therefore R9 = 5/3.5 KΩ = 1.43KΩ pref 1K5Ω Pmax = 18 * 18/1.5 mW = 216mW say 0.5W. Note: this is acceptable as resistor chain R7/R8 is also in circuit.

The Digital Panel Meter ( DPM ) requires a supply current of 150µA at Vs 7V to 14V. Select D3 say 10V. (Pt = 500mW Iz = 50mA max) Let Iz = 10mA then Ir6 = 10.15mA. Vr6 = (27.08 - 10)V

therefore R6 = 17.08/10.15 KΩ = 1.68KΩ preferred value 1K5Ω, P = 17.08*17.08/1.5 mW = 194mW use 0.5W

C2 and C3 zener HF noise reduction capacitors 0.1µF. Resistor chain R7,Vr2,R8 must attenuate [5V to 18V] down to [50mV to 180mV] An attenuation of 100:1.

Let R7 = 20KΩ then R8 200Ω for Vout 18v, Ir7 = 18/20.2mA = 0.891mA,

Vr8 = 0.20 * 0.89 V = 178mA, adding Vr2 (10Ω) to the chain, Ir7 = 0.8906mA. DPM Input Adjustment at Vout 18V = 178.1mV to 187.0mV. Component List

R1, 1K2Ω 0.5W MF R2, 240Ω 0.25W MF R3, 10KΩ 0.25W MF R4, 10KΩ 0.25W MF R5, 24KΩ 0.25W MF R6, 1K5Ω 0.5W MF R7, 20KΩ 0.25W MF R8, 200Ω 0.25W MF R9, 1K5Ω 0.5W MF

Page 103: Electronics Made Easy

Vr1, 1KΩ 10 turn potentiometer Vr2, 10Ω 20t cermet trimpot

DPM, Vs = 17V to 14V, Is = 150µA, Full scale 200mV D1, BZX79, 5V1 D2, Red LED D3, BZX79, 10V IC1, CA3140 REC1, 1.6A, 100V REG1, LM317T

C1, 6800µF Electrolytic 35V DC wkg

C2 and C3, 0.1µF polyester or ceramic T1, Transformer, 20VA, 240V primary, 2* 20V secondaries

f1, 250mA/250V Slow Blow + Skt

Sk2 and Sk3, 4mm terminal posts Sk1, IEC chassis plug 8 way DIL Turned Pin Socket

Page 104: Electronics Made Easy

7) 110V/240V Auto Select Power Supply

Design a 12V DC power supply with a current output of 0.5A, for use in 240V and 110V supply environments. Supply selection should be automatic to prevent inadvertent connection. The circuit diagram is shown in figure 8.

Component Data: BZX85 15V Zener Red LED Green LED DPCO Relay Vz = 15V Vf = 3V Vf = 3V 3A, 240V contacts

0.09mV/°C If = 10mA If = 20mA 290Ω coil Pt =1.3W Ifmax = 25mA If max = 25mA Coil Volts 9.9-19.8V DPCO Relay BC182L (NPN) BC478 (PNP) BZX85 11V Zener 1A, 30V contacts Ic max = 100mA Ic max = 150mA Vz = 11V

Operation 5mS hfe 120 to 500 hfe 110 to 450 0.08mV/°C 720Ω coil Pt = 350mW Pt = 360mW Pt 1.3W Coil Volts 8.4-17.2V MC7812 Diode Bridge 20VA Transformer 20VA Transformer Vin 14.5 to 35V 1.6A, 100V Prim 240v/110v Primary 240V/110V Vdiff = 2.5V Sec 2* 12v,0.8A Sec 2* 15V, 0.6A Output 12V, 1A Droop at FL 7% Droop at FL 7%

Temp 0 to 150°C At full load (0.5A) at 240V supply a single 12V secondary winding will

have the following maximum dc voltage:

Assuming a 5% load factor the 12V winding will produce 12*0.95 =11.4V ac. The theoretical maximum dc voltage = 11.4 * 1.414 –1.2 = 14.9V Two secondary windings in series will produce 22.8V ac at 0.5A load which will provide a maximum dc voltage of 31.0V under no load conditions this would rise to 32.7V. It follows that when the supply voltage drops to 120V ac the maximum dc voltage will be 14.9V.

It follows that neither condition is satisfactory using a single winding at 240V supply a maximum of 14.9V is achievable which is only 0.4V above the minimum drive voltage for the MC7812 regulator. Using two windings the dc voltage of 31V is unacceptably high, a problem which is exacerbated under no load conditions.

Using a 20VA transformer with two secondary windings of 15V at 0.6A, the maximum voltage per winding becomes 20.0V at no load and 18.5V at full load. The dc voltage for secondary windings in series is 41.2V at no load and 38.3V at full load. To allow automatic supply selection it is necessary to either switch the primary or the secondary windings. If the primary windings are switched the transformer size can be reduced but the transformer must be capable of withstanding at least half a cycle at 100% over voltage. Greater flexibility and reliability can be achieved by switching the secondary winding, with the disadvantage that only one secondary winding is available. For duel supplies either a voltage converter must be used or switching the primary windings should be considered. For correct regulator operation: Minimum DC level = 14.5V + ripple say 16V

Page 105: Electronics Made Easy

Maximum DC Level = 35V – ripple – safety factor (10%) say 30V If a MC7812L 1A regulator is selected, the maximum input voltage = 35V dc. The regulator will dissipate approximately (18.5 – 12 – V[R3])*0.523 W

For this design example the obvious choice would be to switch the secondary winding, the increase in transformer size is more than compensated for by the simplicity and reliability of the design, see figure 8a. Figure 8b shows a design solution for switching the primary windings. The other secondary winding is then available for a negative supply or the windings can be connected in series to enable a smaller transformer to be used, for example 12VA with 9v secondaries. Design Option 1 Secondary Winding Switching: Select Sk1 as IEC chassis plug with integral fuse holder (for connection to supply via 110V or 240V leads). Let f1 be 250mA anti surge 20mm and T1 20VA, with 15V secondary windings. With secondary windings in series maximum dc voltage = 30 * 1.414 – 1.2 = 41.2V Allowing for a suitable safety margin let RL1 be energised when dc voltage is equal to 30V (max regulator input volts 35V).

Select RL1 as 12V DPCO relay with operating volts 8.4 to 17.2, impedance 720Ω and contact rating 1A at 30V dc or 0.5A at 120V ac (operating time typically 5mS). If D3 is a 15V zener then: Voltage across R5 + RL1 = 15V when RL1 energised and reaches 26.2V max.

RL1 = 720Ω at 8.4V when voltage across R5 and RL1 15V

R5 = (15 – 8.4)*720/8.4 Ω = 565.7Ω preferred value 560Ω. At max voltage current through D3, R5 and RL1 = 26.2/(720 + 560) = 20.5mA. Maximum Voltage Across RL1 = 720 * 0.0205 = 14.76V (max rated volts 17.2). Power Dissipation of D3 = 15 * 0.0205 W = 0.308W (BZX85 Pt = 1.3W) Power Dissipation of R5 = 0.02052 * 560 = 0.235W preferred value 0.5W. When Voltage across C4 = 30V load current = 15/(720 + 560) = 11.71mA,

with an effective load resistance of 1.28KΩ. For a drop of 1V in 5mS:

C4 = 30T/R = 5*30/1.28 µF = 117.2µF preferred value 220µF at 63V.

Let REC2 = 1A or 1.6A, 100V bridge rectifier, and D4 = IN4001.

Let REC1 = 1A or 1.6A, 100V bridge rectifier. If 0.5A load is permanently connected R4 can be removed from the design

its purpose is to ensure a minimum load on the regulator of 2.5mA or 4K7Ω. The maximum regulator output current = 0.5A + 20mA + 2.5mA = 0.523A.

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To calculate the value of C1:

CV = IT where T = 10mS, I = 0.523A + 0.003A = 0.526A and let voltage ripple = 2V.

C1 = 10 * 526/2 µF = 2630µF preferred value 4700µF 63V. R3 must be selected to provide a suitable time delay on “switch on” to prevent over voltage of the regulator input and provide enough delay to facilitate relay operation.

Delay Time T = R3*C1. If R3 = 1R5Ω then T = 1.5 * 4700 µS = 7.05mS

If R3 = 1Ω then T = 1 * 4700 µS = 4.7mS

If R3 = 1Ω then Power Rating ≥ 0.5262 * 1 = 0.277W, therefore power rating of R3 must be greater than 0.277W. As 0.5W and 1W resistors are not generally

available at 1Ω, say 1Ω, 2.5W silicon coated wire wound. A 4W resistor may prove less expensive. The heat sink for REG1 must dissipate (18.5 – [1 * 0.523] –12)* 0.523 W = 3.13W

As the operating range of the regulator is 0°C to 150°C a 19°C/W heat sink will be adequate.

Capacitors C2 and C3 are included in the design to prevent high frequency

noise and are 0.22µF and 0.47µF respectively. Let D2 (240V indication) be a Red LED with If = 10mA and Vf = 3V, then:

R2 = (12 – 3)/10 KΩ = 900Ω preferred value 910Ω Let D1 (110V indication) be a Green LED with If = 20mA and Vf = 3V, then:

R1 = (12 – 3)/20 KΩ = 450Ω preferred value 470Ω at power = 92/470 = 0.172W, say 0.25W.

Components List (Option 1 Secondary Winding Switching):

R1, 470Ω 0.25W MF R2, 910Ω 0.25W MF R3, 1Ω, 2.5W or 4W R4, 4K7Ω 0.25W MF R5, 560Ω 0.25W MF

C1, 4700µF 63V Electrolytic C2, 0.22µF 100V polyester C3, 0.47µF 100V polyester C4, 220µF 63V Electrolytic D1, Green LED Vf = 3V If = 20mA D2, Red LED Vf = 3V, If = 10mA D3, BZX85 15V D4, IN4001 REC1, 1A or 1.6A 100V Diode Bridge REC2, 1A or 1.6A 100V Diode Bridge REG1, MC7812

RL1, DPCO 12V relay (8.4V to 17.2V), 720Ω coil, contact rating 1A 30V dc, or 0.5A 120V ac and operating time 5mS. T1, 20VA 240V/120V primary winding, 2 off secondary windings 15V 0.6A ac. Sk1, IEC fused chassis plug

F1, 250mA anti surge, 20mm fuse. Heat Sink 19°C/W

Page 108: Electronics Made Easy

Design Option 2 Primary Winding Switching: Select Sk1 as IEC chassis plug with integral fuse holder (for connection to supply via 110V or 240V leads). Let f1 be 1A anti surge 20mm and T1 20VA with 15V secondary windings. The transformer must be able to withstand double its rated input voltage for half a cycle (10mS). With secondary windings in parallel maximum dc voltage at “switch on”= 30 * 1.414 – 1.2 = 41.2V Supply Selection Design: Allowing for a suitable safety margin let RL1 be energised when dc voltage is equal to 28V (max regulator input volts 35V). Steady state dc voltage = 20.0V at no load and 18.5V at full load.

Select RL1 as DPCO 12V relay, (9.9V to 19.8V), 290Ω coil and 3A, 240V ac contact rating, estimated operating time 10mS. The voltage across C4 will be 28V at “switch on” and 20.0V to 18.5V depending upon output load under steady state conditions. For RL1 to operate and latch the relay via Tr3 and Tr2 coil volts must be at least 9.9V, with 18.5V across C4 and must not exceed 19.8V with 28V across C4. Under steady state conditions the voltage across R4 must be sufficient to allow Tr3 to saturate, approximately 2V. When Tr3 saturates Tr2 is “switched on” via R7. Ic of Tr2 = 18.5/(R4 + 290) also Ic = 2/R4 18.5/(R4 + 290) = 2/R4 (R4 + 290)/R4 = 18.5/2 = 9.25 1 + 290/R4 = 9.25 290/R4 = 8.25

R4 = 290/8.25 = 35.15Ω (minimum value)

If R4 = 47Ω then Ic of Tr2 = 18.5/(47 + 290) = 54.9mA

If R4 = 56Ω then Ic of Tr2 = 18.5/(56 + 290) = 53.5mA

Let R4 = 56Ω then voltage across R4 = 3V If Tr2 and Tr4 are both BC182L transistors (hfe = 120 to 500) then Tr2 base current must be greater than 53.5/120 mA = 0.446mA. Let D3 (240V Indicator LED) be a red LED with If = 10mA and Vf = 3V then:

R9 = (12 – 3)/10 KΩ = 900Ω preferred value 910Ω Ib of Tr4 must be greater than 10/120 mA = 0.083mA

R7 ≤ (18.5 –0.6)/(0.446 + 0.083) KΩ = 33K8Ω

Let R7 = 20KΩ.

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If Tr5 is a BC182L transistor, and D4 (110V Supply Indicator LED) is a green LED with If = 20mA and Vf = 3V, then:

R10 = (12 – 3)/20 KΩ = 450Ω preferred value 470Ω Ic of Tr5 = 9/0.470 mA = 19.15, then:

Ib of Tr5 must be greater than 19.15/120 mA = 0.16mA Note: Tr5 is only “switched on” when RL1 is de-energised therefore: Tr5, Ib = (18.5 – 0.6)/(R4 + 290 + R8)

0.16 = 17.9/(0.056 + 0.290 + R8) where R8 is in KΩ 0.16(0.346 + R8) =17.9 0.346 + R8 = 17.9/0.16 = 111.9

R8 ≤ 111K55, let R8 = 47KΩ At “switch on” with 240V supply, RL1 will start to energise at 28V across C4. When Tr1 is saturated (ie fully switched on), the voltage across the relay coil must be greater than 9.9V but not exceed 19.8V. D2 is selected to prevent back EMF generated across the relay coil. Let D2 = IN4001. Let the voltage across the coil of RL1 equal 10V, then: Ic of Tr1 = 10/0.290 mA = 34.5mA.

The voltage across R4 = 56*0.0345 = 1.93V. If the PNP transistor Tr3 is a BC478 then hfe = 110 and Vbe = 0.6V.

The voltage across R6 = 1.93 – 0.6 = 1.33V and R7 is 20KΩ therefore: Ib of Tr3 = Ic/110 and Ic at switching point = (28 – 0.6)/20 mA = 1.37mA.

Therefore Ib must be greater than 12.45µA.

R6 ≤ 1.33/0.01245 KΩ = 107KΩ. Let R6 = 47KΩ R5 = (28 – 1.93 – 10)/(34.5 + Ib). The effect of R6 is negligible.

If hfe of Tr1 = 120 then Ib ≥ 34.5/120 mA = 0.29mA assume 0.5mA.

R5 = 16.07/35 KΩ = 459Ω as 470Ω would prevent operation of the relay select R5 = 430Ω.

To calculate voltage across R5: V = 28 – (R4 + 290)Ic = R5(Ic + Ib)

28 – 0.346Ic = 0.430*0.5 + 0.430Ic where Ic mA and resistors in KΩ. 28 – 0.215 = 0.776Ic Ic = 35.8mA therefore voltage across R5 = 0.430(35.8 + 0.5) = 15.6V. For Tr1 to “switch on” voltage across R3 = 15.6 + Vbe = 15.6 + 0.6 = 16.2V

If D1 is a BZX85, 11V zener then D1 will start to conduct when input voltage is greater than 12V. At 28V the voltage across R2 is 28 – 11 –16.2 = 0.8V.

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If current through D1 is approximately 10mA then R3 = 16.2/9.5 KΩ

R3 = 1K705 preferred value 1K8Ω.

If R3 = 1K8 then current through R3 = 16.2/1.8 mA = 9mA and current through R2 = 9.5mA.

R2 = 0.8/0.0095 Ω = 84.2Ω preferred value 82Ω Calculating the value of C4: The capacitor C4 must fulfil two functions, it must provide a suitable delay during the operation of RL1 and provide a sufficiently smoothed supply voltage to the relay latching circuit during the transition to steady state conditions. Assuming the operating time of the relay is 10mS, and the release time will ensure a voltage overshoot of at least 1V, the capacitance can be calculated as follows: T = C4*R*1/29, where T is the operating time of the relay, R is the resistive load. C4 = 29T/R at RL1 energised Ic of Tr1 = 35.8 mA and current through D1 = 9.5mA

load current before relay latches = 45.3mA at 28V. R = 28/0.0453 = 618Ω

Therefore: C4 = 29 * 10/0.618 µF = 469.3µF. When Relay Latches: Il = (28 – 11)/(R2 + R3) + 28/(R4 + 290) + (28 – 0.6)/R7 I load = 17/1.88 + 28/0.346 + 27.4/20 mA. = 9.04 + 80.9 + 1.37 = 91.31mA CV =IT where T = 10ms (due to full wave bridge rectifier). I = Load Current. V = permissible voltage ripple.

Let V =2V then: C4 = 91.31 * 10/2 µF = 456.6µF

Let C4 = 470µF 63V. Under steady state conditions the power supply capacitor C1 will also have an effect (after time out of R1*C1). Regulated Power Supply Design: As with the previous design select REG1 as MC7812L 1A regulator with a maximum input voltage of 35V dc. The regulator will require a heat sink to dissipate approximately (18.5 – 12 – V[R1])*0.523 W To calculate the value of C1:

CV = IT where T = 10mS, I = 0.523A + 0.003A = 0.526A and let voltage ripple = 2V.

C1 = 10 * 526/2 µF = 2630µF preferred value 4700µF 63V. R1 must be selected to provide a suitable time delay on “switch on” to prevent over voltage of the regulator input and provide enough delay to facilitate relay operation.

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Delay Time T = R1*C1. If R1 = 1R5Ω then T = 1.5 * 4700 µS = 7.05mS

If R1 = 2.2Ω then T = 2.2 * 4700 µS = 10.34mS

If R1 = 3.3Ω then T = 3.3 * 4700 µS = 15.5mS

If R1 = 3.3Ω then Power Rating ≥ 0.5262 * 3.3 = 0.913W, therefore power rating of R1 must be greater than 0.913W. As 1W and 2W resistors are not

generally available below 10Ω, use 3R3Ω, 4W wire wound ceramic body. The heat sink for REG1 must dissipate (18.5 – [3.3 * 0.523] –12)* 0.523 W = 2.5W

As the operating range of the regulator is 0°C to 150°C a 19°C/W heat sink will be adequate.

Capacitors C2 and C3 are included in the design to prevent high frequency

noise and are 0.22µF and 0.47µF respectively. Components List (Option 2 Primary Winding Switching):

R1, 3.3Ω 4W wire wound R2, 82Ω 0.25W MF R3, 1K8Ω, 0.25W MF R4, 56Ω 0.25W MF R5, 430Ω 0.25W MF R6, 47KΩ, 0.25W MF R7, 20KΩ 0.25W MF R8, 47KΩ 0.25W MF R9, 910Ω, 0.25W MF R10, 470Ω 0.25W MF

C1, 4700µF 63V Electrolytic C2, 0.22µF 100V polyester C3, 0.47µF 100V polyester C4, 470µF 63V Electrolytic D1, BZX85 11V D2, IN4001 D3, Red LED Vf = 3V If = 10mA D4, Green LED Vf = 3V, If = 20mA Tr1, BC182L Tr2, BC182L Tr3, BC478 Tr4, BC182L Tr5, BC182L REC1, 1A or 1.6A 100V Diode Bridge REG1, MC7812

RL1, DPCO 12V relay (9.9V to 19.8V), 290Ω coil, contact rating 3A at 240V ac. Estimated operating time 10mS. T1, 20VA 240V/120V primary winding, 2 off secondary windings 15V 0.6A ac. Sk1, IEC fused chassis plug F1, 1A anti surge, 20mm fuse.

Heat Sink 19°C/W

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8) Isolated Pulse Conditioning Circuit

Design an optically isolated pulse conditioning circuit to deliver positive negative or zero crossing pulses to instrumentation, from an existing pulse signal. The design should be compact enough to be contained within a small rail mounted module. The circuit diagram is shown in figure 9. Component Data:

BZX79 Zener Red LED BZX79 Zener IC1 CA3140 Vz = 5V1 Vf = 3V Vz = 6V8 Vs +4V to +36V

-0.8mV/°C If = 10mA 3mV/°C OL Gain 100db Pt = 0.5W Ifmax = 25mA Pt = 0.5W

6N139 Opto-isolator Pin Details: 1, NC 2, LED Anode Diode: If 0.5mA typ 3, LED Cathode 4, NC Vf max 1.7V 5, GND 6, Vo Vr min 5V 7, Vs 8, Vcc (supply) Coupling: 300Kbit/s Isolation 3000Vdc

BZX79 Vz = 2V4

-1.6mV/°C Pt = 0.5W

The pulse converter design shown in Figure 9 should be as versatile as

possible, these modules are ideal for the connection of signals from different measuring systems where any interconnection between systems would be undesirable. Power supplies should be connected as required for the different applications. The pulse converter modules can be rail mounted at any location but obviously the power supplies for the modules should be taken from the same source.

The isolated + and – inputs must accept a wide range of input pulses typically from 5V pk-pk to 20V pk-pk. The input signal may also have a dc offset of up to 20V (proximity transducers) Input Circuit: The opto-isolator requires a minimum drive current of 0.5mA, with a maximum input voltage of 1.7V. Select D1 as a BZX79 2V4 Zener diode, then voltage across R2 = 0.7V at 0.5mA,

for minimum drive and R2 (max) = 1K4Ω

If R2 = 470Ω, then If = 1.49mA at Vf = 1.7V. Minimum input voltage at D1 = 470*0.0005 + Vf(min). assuming Vf(min) = 0.6V, then minimum voltage at D1 = 0.835V (at typical If) Pt = 0.5W for BZX79, therefore maximum current through D1 = 500/2.4 mA = 208mA Maximum Input Current = 208.5 mA therefore for an input of 10V pk the minimum

value of R1 + Xc = 48Ω.

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C1 is used to block the dc signal level. If C1 is a non polar capacitor then the

maximum value is limited to 10µF. The input impedance of the capacitor can be approximated as follows:

Xc = 1/2πFC

For Frequency 2Hz, Xc = 106/2*3.142*2*10 = 8KΩ

For Frequency 50Hz, Xc = 106/2*3.142*50*10 = 318Ω

For Frequency 100Hz, Xc = 106/2*3.142*100 10 = 159Ω

For Frequency 1KHz, Xc = 106/2*3.142*1000 10 = 15.9Ω Note: These impedance calculations are only approximate as the input signal is a pulse not a sine wave, also the minimum input voltage and current to the opto-isolator is estimated. For the opto-isolator to operate at 2Hz with an input voltage of 5V pk-pk,

(R1+Xc)If ≤ 2.5 – 0.835, (R1+Xc) ≤ 1.665/0.5 KΩ) ≤ 3K3 With Input Signal 10V pk-pk at 2Hz

(R1+Xc)If ≤ 5 – 0.835, (R1+Xc) ≤ 4.165/0.5 KΩ) ≤ 8K3

If R1 = 1KΩ then with an input signal of 10V pk-pk the opto-isolator will operate at a frequency slightly above 2Hz. The maximum input signal can be calculated as follows: Vpk – 2.4 = R1* 208.5 V = 208V, note the value of Xc not significant. As C1 is a polyester capacitor with a working voltage of 63V this becomes the voltage limit of the design with an absolute maximum voltage across the input terminals of 65V. The maximum power dissipation of R1 = V2/1K Assuming worse case condition where input signal is a square wave with equal m-s ratio V = 32.5V. Allowing for D1 let V = 30.1V. Power (R1) = 30.12/1000 W = 0.9W

Select R1 as 1KΩ, 1W IC1 Output and Buffering: Select Vcc as 6.8V and LED with Vf = 3V, If = 10mA As the output stage of IC1 is a transistor switching between Vcc and 0V R3 is calculated as follows:

R3 = (6.8 – 3)10 KΩ = 380Ω preferred value 390Ω LED current = 3.8/390 = 9.7mA IC2 is an operational amplifier connected as a comparator. When the voltage at pin 3 is greater than pin 2 the output voltage on pin 6 will be at approximately

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2V below the supply voltage at pin 7. When the voltage at pin 2 is greater than pin 3 the voltage at pin 6 will be equal to the voltage at pin 4. The input resistor values (R5 and R6) are not critical and can be anything from

0Ω to 100KΩ. Select R5 and R6 as 10KΩ The voltage divider formed by R4 and R7 sets the switching point of IC2 which must be set between 0V and 6.8V. The set point voltage ideally should be set mid range for optimum performance, at either end of the range signal or power supply noise could produce additional pulses. Another consideration is that the higher the set point the less current drive is required to operate the opto isolator as the output stage need note be driven into saturation. A higher set point will increase the low frequency range.

Let the set point voltage be 4.5V and R7 = 9K1Ω Then the current through R7 = 4.5/9.1 mA = 0.495mA The voltage across R4 = 6.8 – 4.5 = 2.3V

Therefore R4 = 2.3/0.495 KΩ = 4K65 preferred value 4K7 Supply Design:

For the output pulse to equal +5V the voltage at pin 7 = 7V. The nearest preferred value of zener diode is 6.8V.

The pulse converter is designed to accept supplies of +12V, +24V or ±12V. For a 0V to 10V output +12V or +24V must be supplied. For a ±5V output a ±12V supply is required. The positive supply current load will vary between 0.495mA and approximately 21mA (9.7 + 0.5 + 0.495 + 10). To calculate R8: Let the current through D2 at full load = 6mA approximately,

then R8 = (12 –6.8)/27 KΩ = 193Ω preferred value 180Ω at Power 5.22/180 = 0.15W The maximum power dissipation of D2 occurs under minimum load conditions, The current through R8 = 5.2/.180 mA = 28.9mA therefore the current through D2 = 28.4mA and Pt = 6.8 * 28.4 mW = 193mW. The current through D4 = 28.9mA therefore Pt = 12 * 28.9 mW = 347mW. The power dissipation of the zener diodes D2 and D4 is less than 0.5W therefore select D2 as BZX79 6V8 and D4 as BZX79 12V. To provide a –5V output a negative 5V supply must be fed to pin 4 of IC2. Assuming the maximum load to be 10mA the value of R9 is calculated as follows: R9 = (12 – 5.1)/(10 + Id3), where Id3 is the current through D3 at full load

Let Id3 = 6mA then R9 = 6.9/16 KΩ = 431Ω preferred value 390Ω at Pt = 6.92/390W Pt = 122mW. The maximum current through D3 = 6.9/0.390 mA = 17.7mA therefore Pt = 5.1 * 17.7mW = 90.3mW therefore select D3 as BZX79 5V1

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Capacitors C2 and C3 limit high frequency noise a suitable value would be 0.1µF. Pulse Converter Connections:

Output (H,D) Power Supply Links

0V to 10V +12V at C, 0V at J B to C and E to D or +24V at G, 0V at J

0V to 5V +12V at C, 0V at J B to A and E to D

or +24V at G, 0V at J

±5V +12V at C, 0V at J B to A and E to F and -12V at M

Components List:

R1, 1KΩ 1W CF R2, 470Ω 0.25W MF R3, 390Ω 0.25W MF R4, 4K7Ω 0.25W MF R5, 10KΩ 0.25W MF R6, 10KΩ 0.25W MF R7, 9K1Ω 0.25W MF R8, 180Ω 0.5W MF R9, 390Ω 0.5W MF

C1, 10µF 63V Polyester C2, 0.1µF polyester or ceramic C3, 0.1µF polyester or ceramic D1, BZX79 2V4 D2, BZX79 6V8 D3, BZX79 5V1 D4, BZX79 24V LED, Red If 10mA Vf 3V IC1, 6N139 IC2, CA3140 2 off 8 way DIL turned pin sockets Rail mounting component box

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Page 118: Electronics Made Easy

9) Optically Coupled Frequency to Voltage Converter

Design an optically coupled frequency to voltage converter to provide speed indication of rotating machinery. The speed signal is to be provided from a proximity transducer giving 1 pulse/revolution at 5 to 20V. The unit output should be set at 9V DC for an input of 150Hz (1V/1000rpm).

The circuit must be compact enough to be mounted into a small rail mounted module. Component Data:

ZN458B Zener Red LED IN4148 OP77 Low Drift opamp

Vz = 2.49V Vf = 3V Vrrm = 75V Vs ±3V to ±18V Stab ± 2%/yr If = 10mA If = 75mA max OL Gain 132db

-55°C to +125°C Ifmax = 25mA Vf 1V,(If = 10mA)

6N139 Opto-isolator TC9401 (F-V) Diode: If 0.5mA typ Freq Range 10Hz to 100KHz Vf max 1.7V Linearity: at 10KHz 0.004% at 100KHz 0.04%

Vr min 5V Temp Coeff ±25 ppm/°C Coupling: 300Kbit/s Supply +8V to +15V or ±4 to ±7.5V Isolation 3000Vdc Pin Details: 1, I(bias) 14, Vdd Pin Details: 1, NC 2, Zero Adj 13, NC 2, LED Anode 3, I(in) 12, Amp out 3, LED Cathode 4, Vss 11, Comp in 4, NC 5, Vref out 10, F/2 out 5, GND 6, GND 9, OP Com 6, Vo 7, Vref 8, Pulse F out 7, Vs 8, Vcc (supply) The Input Stage Design:

The typical drive current necessary to drive the output stage of IC1 into saturation is approximately 0.5mA (1.6mA max). The input signal from a proximity transducer can be a low level zero crossing pulse but is typically conditioned providing a positive pulse of 5V to 10V from a base of approximately –20V with respect to earth.

If a pulse of 5V is generated the input level will drop to –15V, for a pulse of 12V the input level will drop to –8V. The input circuit must therefore accommodate a maximum voltage in excess of -20V and a minimum voltage of –8V.

R1 and R2 prevent damage to the input stage of the opto-isolator IC1. At

maximum current (1.6mA), and 20V input R1 + R2 = 20/1.6 KΩ.

The minimum value of R1 + R2 = 12K5Ω

For a 12V pulse (ie input level –8V) R1 + R2 = 8/0.5 KΩ = 16KΩ

For a 5V pulse R1 + R2 + Vr3 > 15/0.5 KΩ = 30KΩ

Let R1 = R2 = 7K5Ω and Vr3 = 100KΩ

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As the input of the frequency to voltage converter IC2 requires a zero

crossing pulse (clamped to ± 0.6V in this case) the output of IC1 must also cross zero.

IC2 must be supplied with a dual power supply ±4V to ±7.5V, therefore select the supply of IC2 to be ± 5V. For the output of IC1 to be zero crossing feed IC1 from the same supply.

The Red LED D7 requires Vf = 3V and If = 10mA. When the transistor output

of IC1 saturates the voltage across R3 = (10 – 3) = 7V, therefore:

R3 = 7/10 KΩ = 700Ω, 680Ω preferred value. The Frequency to Voltage Conversion Several good frequency to voltage converters are available, the TC9401 combines good linearity with relatively low cost.

As the input to IC2 (pin 11), must cross zero and operate effectively throughout the frequency range diodes are used to clamp the zero crossing signal rather than generating a zero crossing signal with a capacitor, therefore let D1

and D2 be IN4148 and current limiting resistor R4 be 10KΩ.A pull up resistor R5, 75KΩ holds the F-V converter input high when no input signal is present. Note the minimum input for TC9401 is ± 0.4V the diodes will clamp the input at ± 0.6V.

Pins 14 and 4 are supply connections and are +5V and –5V respectively. The

output common pin 9 and ground pin 6 are connected to 0V.

To provide a 10% zero offset, a voltage swing of approximately ± 100mV must be applied to pin 2 (zero Adj).

Let Vr2 = 50KΩ, connected across ± 5V supply rails. R11 and R10 form a voltage divider to allow approximately ± 100mV at pin 2.

If R11 = 100KΩ then 5/0.1 = (R11 + R10)/R10 50 = (100K + R10)/R10 50*R10 = 100K + R10, therefore 49*R10 = 100K

R10 = 2.04KΩ, Let R10 = 2K2Ω The output voltage of IC2 is related to the input frequency by the

transfer equation: Vo = (Vref*Cref* Rint)Fin Where Vo is the output voltage at pin 12, Vref is the reference voltage at

pin 7 and can be adjusted to give gain control. Maximum gain occurs when Vref = -5v.

Cref and Rint control the integration time Cint will adjust the response

time of the converter. The larger the value of Cint the smaller the voltage ripple on the output. Cref, Rint and Cint are C4, R12 and C1 respectively on the circuit diagram (see Fig 10).

At maximum gain Vref = -5V.

If C4 = 8200pF and R12 = 470KΩ at maximum input frequency of 150Hz:

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Vo = 5 * 8200 * 10-12 * 470 * 103 * 150 = 2.8905V The maximum possible output is supply voltage –1V (ie 4V). As the converter operates at low frequency a large value of Cint or C1 can

be chosen. This will significantly reduce the output ripple but adversely effect

the response time of the circuit. If C1 is 2.2µF an 80mV pk-pk ripple can be expected at the buffered output (150Hz, 9V).

If a fast response is required together with good ripple rejection a two

stage low pass filter could be used after output buffer, and the value of C1 could be significantly reduced (ie 1000pF). This would result in a larger more expensive unit.

The gain control is achieved by reducing the value of Vref. Vr1 and R7

form a voltage divider from the –5V rail to 0V.

If Vr1 = 1KΩ and R7 = 4K7Ω then Vref can be adjusted from –5V to –5*4K7/5K7 = -4.12V. This results in a gain variation of approximately 18%

(ie 100*4.12/5). Pin 1 of IC2 (I Bias), must be fed with a small –ve bias current.

Let R8 = 100KΩ R9 enables the buffered frequency output

Let R9 = 10KΩ. The Output Buffer At mid range gain Vref would be –4.56V this would relate to an output of 4.56*2.8905/5 = 2.636V at 150Hz. As an output of 9V is required a buffer amplifier must be used in the final stage. Amplifier Gain = Vo/Vin = 9/2.636 = 3.41*

The maximum output load of IC2 is 2KΩ thus must be greater than 2KΩ.

If R16 = 10KΩ, Gain = 3.41 = (R15 + 10K)/10K

R15 = 10(3.41 – 1) KΩ = 24.1KΩ preferred value 24KΩ. As the output impedance of IC2 is insignificant when compared with R16, let R16 = R14. As high accuracy and low drift is required select IC3 as OP77. The minimum dual supply voltage to produce required output is Vo + 2 or 11V. Power Requirements

If a dual 12V supply is used, a stable ±5V supply must be generated for IC1 and IC2. As high accuracy and low drift are required normal zener diodes would not have sufficient stability, so band gap zeners or regulators must be used. As band gap zeners take up less space than regulators and their associated circuitry, four 2.49V ZN458B band gap zeners have been selected. D3 and D4 form the negative rail while D5 and D6 form the positive rail.

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+5V Power Loading -5V Power Loading IC1 pin 8 1.6mA Vr1 (5/5.7) 0.9mA IC1 pin 6 10mA IC1 pin 5 10mA D5 and D6 10mA D3 and D4 10mA IC2 pin 11 (5/75K) 0.1mA IC2 pin 1 (5/100K) 0.1mA IC2 pin 14 (1.5mA typ) 5mA IC2 pin 4 (1.5mA typ) 5mA Vr2 (10/50K) 0.2mA 0.2mA IC2 pin 8 (5/10K) 0.5mA Total Load 27.4mA 26.2mA

For +12V Supply R13 = (12-4.8)/0.0274 Ω = 262.8Ω preferred value 240Ω At power 7.22/240 W = 0.216W, for 15V supply P = 10.22/240 W = 0.433W

For -12V Supply R6 = (12-4.8)/0.0262 Ω = 274.8Ω preferred value 270Ω At power 7.22/270 W = 0.192W, for 15V supply P = 10.22/270 W = 0.385W

Let R13 = 240Ω 0.5W and R6 = 270Ω 0.5W. All other resistors 0.25W. Capacitors C2 and C3 reduce high frequency noise on the 5V power rails.

Let C2 and C3 = 0.1µF Capacitors C5 and C6 reduce high frequency noise on the 12v or 15V power rails.

Let C5 and C6 = 0.1µF Components List

R1, 7K5Ω 0.25W MF R2, 7K5Ω 0.25W MF R3, 680Ω 0.25W MF R4, 10KΩ 0.25W MF R5, 75KΩ 0.25W MF R6, 270Ω 0.5W MF R7, 4K7Ω 0.25W MF R8, 100KΩ 0.25W MF R9, 10KΩ 0.25W MF R10, 2K2Ω 0.25W MF R11, 100KΩ 0.25W MF R12, 470KΩ 0.25W MF R13, 240Ω 0.5W MF R14, 10KΩ 0.25W MF R15, 24KΩ 0.25W MF R16, 10KΩ 0.25W MF

Vr1, 1KΩ, 20 turn Cermet Trimpot. Vr2, 50KΩ, 20 turn Cermet Trimpot Vr3, 100KΩ, 20 turn Cermet Trimpot.

C1, 2.2µF Polyester Min Layer C2, 0.1µF Disc Ceramic C3, 0.1µF Disc Ceramic C4, 8200pF Silvered Mica

C5, 0.1µF Disc Ceramic C6, 0.1µF Disc Ceramic D1, IN4148 D2, IN4148 D3, ZN458B (2.49V) D4, ZN458B (2.49V) D5, ZN458B (2.49V) D6, ZN458B (2.49V) D3, ZN458B (2.49V) D7, Red LED, Vf = 3V, If = 10mA IC1, 6N139 IC2, TC9401 IC3, OP77 2, 8 way DIL Turned Pin Sockets 1, 14 way DIL Turned Pin Sockets

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10) Precision Square Wave Oscillator

Design a precision square wave oscillator to use plug in crystals as a frequency standard, and provide multiple outputs by means of frequency division. The oscillator should have the following functions: Range (ie frequency division switching) Pulse Width Adjustment Pulse Invert Gain and Offset Controls ( max pulse 10V pk or 20V pkpk) Note for frequencies higher than 100KHz the unconditioned output must be used. The circuit diagrams are shown in figures 11 and 12. Component Data:

IN5359B Zener Red LED BZX85 Zener CA3140 Vz = 24V Vf = 3V Vz = 11V Vs +4V to +36V

20mV/°C If = 10mA 0.08mV/°C OL Gain 100db

Pt = 5W Ifmax = 25mA Pt = 1.3W Diff ip ±8V Pt 630mW

MC7812 Diode Bridge T1 Transformer DPDT Switch Vin 14.5 to 35V 1.6A, 100V Prim 240v/110v 240V/2A Vdiff = 2.5V Sec 2* 20v,0.3A Output 12V, 1A Droop at FL 10%

MC78L05 MC79L12 BC109 Vin 6.9V to 30V Vin –14.2V to –35V Ic max, 100mA Vdiff = 1.9V Vdiff = 2.2V hfe, 200-800 Output 5V,100mA Output –12V,100mA Vceo, 20V. Ft = 300MHz 74LS90 (TTL) MC14018BCP (CMOS) OP07

/n (/5 or /10) /n (/10) Vs ± 3V to ±18V Vs, 4.5V to 5.5V Vs, 3V to 18V OL Gain 132db Oscillator Design:

The crystal oscillator uses a single stage emitter follower transistor amplifier with positive feedback provided via the plug in quartz crystal. The frequency of oscillation is determined by the physical dimensions of the crystal (see fig 11). Select Tr1 as BC109 For DC bias: 12V = 2(Ic + Ib)R2 + (Ic + Ib)R3.

Select R2 4K7Ω and R3 (for approximately Ve 0.6V). Note this will provide an equal M-S ratio at the output of Tr2 0.6 = (Ic + Ib)R3 12 = 2(Ic + Ib)R2 + 0.6 Ic + Ib = 11.4/2*4.7 mA = 1.24mA

R3 = 0.6/1.24 KΩ = 484Ω preferred value 470Ω Ic + Ib = 12/(2R2 + R3) = 12/(9.2 +.47) mA = 1.24mA

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Vc = 12 – (Ic + Ib)R2 = 6.172V Ve = (Ic +Ib)R3 = 0.58V Vb = Ve + 0.6 = 1.18V IbR1 = Vc –Vb = 6.17 – 1.18 = 4.99V If hfe = 10, then Ic = 10Ib and 11Ib = 1.24mA

Ib = 0 113mA and R1 = 4.99/0.113 KΩ = 44.16KΩ

Let R1 = 47KΩ then Ib = 4.99/47 mA = 0.106mA and Ic = 1.24 – 0.106 = 1.13mA Therefore hfe = 1.13/0.106 = 10.7 The capacitors C1 and C2 should not be greater than 100pF for the frequency range 4MHz to 8MHz. Select C1 and C2 = 100pF. The trim capacitor in series with the crystal Ct should provide slight frequency adjustment. In practice it will be set at approximately mid range. Let Ct = 5pF-65pF. Sine-Square Conversion:

To convert the sinusoidal waveform to a TTL input a transistor is used in switch mode, powered from a 5V supply. To power the low power schottky divide

module select R5 = 1KΩ and Tr2, BC109. Note: TTL is used for the first divide stage as the frequency response of CMOS would be insufficient. Subsequent stages use CMOS due to its low power consumption. The switching point of the transistor Tr2 is achieved when the base voltage Vbe is 0.6V and sufficient drive current is provided to saturate the transistor. To drive the collector to 0V, Ic = V/R5 = 5/1K = 5mA

Gain hfe is 200 to 500* therefore Ib = 5/200 mA = 25µA

For Tr2 to saturate at 0.1V above Vbe the base resistor R4 = 0.1/0.025 KΩ = 4KΩ

It follows that for an input of 10mV above Vbe R4 = 400Ω As this could adversely affect the dc bias conditions of the previous stage a R-C network is used to feed Tr2.

Let R4 = 47KΩ. If C3 = 47pF then Xc = 1/(2πFC)

For Frequency 4MHz, Xc = 1012/(2π*4*106*47) = 848Ω

For Frequency 8MHz, Xc = 1012/(2π*8*106*47) = 424Ω First Divide Stage:

The first divide stage IC1, (74LS90) feeds ÷5 and ÷10 outputs via Sw2 to Sw1, which feeds subsequent divide stages via transistor switch Tr3. Switches 1, 2 and 3 are mechanically connected via a latching bar.

Sw1 when depressed connects 5V to the input of the transistor switch thus saturating Tr3 and preventing any oscillation. This is useful when setting up

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the offset control. When either Sw2 or Sw3 are depressed, Sw1 is reset and

connects the transistor switch to the ÷5 and the ÷10 outputs from IC1 via Sw2.

When Sw2 is depressed pin 12 of IC1, the ÷10 output, is connected to the transistor switch via Sw1. Pin 11 the ÷5 output of IC1 is connected to pin 14 of IC1. This then reduces the output frequency by 50%. When Sw3 is depressed Sw2 is

reset and the ÷5 output of IC1 is fed to the transistor switch. Sw3 exists only to provide reset for Sw2 and has no electrical connections.

To reduce high frequency noise select C4 0.1µF. CMOS Divide Stages: Transistor switch Tr3 buffers the 5V output from the TTL divide stage (IC1), to subsequent CMOS dividers. To drive IC2 (4018B)a peak voltage greater than 0.7Vs must be generated, where Vs is the CMOS supply voltage (12V). As the CMOS input current is small in

comparison with TTL R7 can be selected as 10KΩ fed from 12V. The switching point of the transistor Tr3 is achieved when the base voltage Vbe is 0.6V and sufficient drive current is provided to saturate the transistor. To drive the collector to 0V, Ic = V/R7 = 12/10K = 1.2mA

Gain hfe is 200 to 500* therefore Ib = 1.2/200 mA = 6µA The output of the divide stage IC1 is nominally 0V to +5V (square wave) Assume trigger point of Tr3 is set at an input of say +2.5V

For Tr3 to saturate at 1.9V above Vbe the base resistor R6 = 1.9/0.006 KΩ = 316KΩ, select R6 = 100KΩ As with the previous switching stage a R-C network is used to feed Tr3.

R6 = 100KΩ. If C6 = 100pF then Xc = 1/(2πFC)

For Frequency 400KHz, Xc = 1012/(2π*0.4*106*100) = 3.98KΩ

For Frequency 800KHz, Xc = 1012/(2π*0.8*106*100) = 1.99KΩ

For Frequency 1.6MHz, Xc = 1012/(2π*1.6*106*100) = 1KΩ The 4018B divider is a 16 pin package. Pin 8 is connected to 0V and pin 16 supply volts.

For ÷10 connections are as follows: Pin 14 input. Pins 1 and 13 are linked and form the output. Pins 15, 10 and 8 connected to 0V. Dividers IC2 to IC7 are cascaded to form the required number of divide stages. Sw4 (Range) selects the required output and feeds the signal to the pulse

conditioning stages. To reduce high frequency noise, select C5 as 0.1µF. Note: when switches 5 to 7 are set to “OFF” the raw divide signal is fed to the high output terminal Sk3.

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Page 127: Electronics Made Easy

Pulse Width Control: Sw4 (range) feeds the input of the pulse width circuit. IC8 (CA3140) is an operational amplifier in comparator mode, switching between 0V and 10V (Vs-2). The square wave pulse is fed to pin 3 via voltage divider R9, R10 and input resistor R11.

Let R9 = 10KΩ and R12 = 10KΩ then the voltage at pin 3 the non inverting input will be exactly half the square wave input. When the voltage at pin 2 is greater or equal to the voltage at pin 3 the output of IC8 will be zero. The output will be high when the square wave input is high until the capacitor C7 charges to the voltage at pin 3. The pulse width is calculated as follows: T = 0.5C7(R8 + Vr1)

If C7=0.01µF and R8 = 3KΩ (note: R8 chosen not to load square wave input).

When Vr1 = 0Ω then Pulse Width T = 0.5*0.01*3 mS = 0.015mS or 15µS.

When Vr1 = 1MΩ then Pulse Width T = 0.5*0.01*1003 mS = 5.015mS.

For Pulse Width Range 15µS to 5mS let R8 = 3KΩ, C7 = 0.01µF and Vr1 1MΩ

The values of R10 and R11 are not critical any value up to 47KΩ would be

acceptable. Let R10 and R11 be 10KΩ. Sw5 (Pulse Width) switches between pulse width stage input and output and feeds the next stage (Invert) at Sw6. Invert Stage: The invert stage is a conventional inverting amplifier with a gain of 1.As the amplifier is required to provide a negative pulse duel supplies are fed to the amplifier. Let the amplifier be OP07. Gain = R14/R13, and R15 = R13*R14/(R13 + R14)

If R13 = 10KΩ then for a gain of 1 R14 = 10KΩ

R15 = 10K*10K/(10K + 10K) = 5KΩ preferred value 4K7Ω. Sw6 (Invert) switches between input and output and feeds Sw7 gain. Gain Control Stage: The Gain stage is a conventional non-inverting amplifier with a gain of 2 (minimum gain), fed from a voltage divider formed by R16 and Vr2. As the amplifier is required to provide either a positive or a negative pulse duel supplies are fed to the amplifier. Let the amplifier be OP07, and the voltage

divider R16, 4K7KΩ and Vr2, 5KΩ. Gain = (R18 + R19)/R18 and R17 + Rin = R18

If R18 = 47KΩ then R19 = 47KΩ. As Rin varies between 2K4Ω and 0 its effect is negligible so let R17 = 47KΩ. Sw7 (Gain) selects input or output of the Gain stage and feeds the signal to Sk3 (Output High).

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Page 129: Electronics Made Easy

The Offset Stage: Without offset the precision oscillator output would be 0v to +12V without conditioning and either 0V to +10V or 0V to –10V. The minimum offset range at the low output socket Sk4 would be + 12V to –10V. If the oscillator were used to simulate proximity transducer outputs from a -24V system the positive offset range would be increased to +22V. If a CA3140 is selected for IC11 the maximum rail voltage differential is 36V. For an offset of +22V the positive rail voltage must be +24V. The negative rail voltage would be – 12V to provide a –12V offset but as this would run the operational amplifier at its absolute maximum supply volts. A compromise would be to limit the negative rail voltage to -11V, this would only slightly reduce the negative offset to –11V. If IC11 is configured as a non-inverting amplifier with a gain of 3* then the voltage at pins 1 and 3 of Vr3 must be +7.33V and –3.67V respectively. The voltages across R27 = 16.67V and R24 = 7.33V.

If R25 = 100KΩ then R28 = 200KΩ and R26 + Rin = R25

If Vr3 is 10KΩ then maximum impedance to 0V will be 10 * 7.33/(7.33 + 3) KΩ

Therefore Rin max = 7K1Ω, as this value is small compared with R25 it can be neglected, therefore let R26 =100KΩ. As the voltage across Vr3 is 11V then I = 11/10 mA = 1.1mA. Calculating R27 and R24:

R27 = 16.67/1.1 KΩ = 15K09Ω preferred value 15KΩ

R24 = 7.33/1.1 KΩ = 6K66 preferred value 6K8Ω. The current through resistor chain (R27-Vr3-R24) = 35/(15+10+6.8) mA = 1.101 mA The voltages at pin 1 and pin 3 of Vr3 are +7.48V and –3.53V respectively. Note

maximum differential input voltage of IC11 is ±8V. Pt for the CA3140 is 630mW this equates to a load current of 18mA. Typical load current say 5mA. Estimate 11V and 24V loads to be 2mA to 19mA. Power Supply: Load Estimations: +5V (R5, 5mA, IC1 10mA) say 15mA +12V (IC2 to IC10, 90mA, +5V, 20mA) say 110mA -12V (IC9 and IC10, 20mA, D9, 10mA, D2, 22mA) say 52mA +27V (+12V, 110mA, D1, 22mA REG, 5mA) say 137mA -27V (-12V, 52mA, REG 5mA) say 57mA Let T1 be rated at 12VA with 2* 20V, at 0.3A droop 10% at full load. As the loads are less than 1A , let REC1 and REC2 be 1A or 1.6A at 100V.

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Maximum Voltage Positive Supply = (20 –1)*1.414 – 1.2 = 25.67V Maximum Voltage Negative Supply = (20 –0.4)*1.414 – 1.2 = 26.51V Calculating C8 and C10: CV = IT C8 = IT/V = 137*10/1 (Max Ripple 1V)

C8 = 1370µF preferred value 2200µF 63V C10 = IT/V = 57*10/2 (Max Ripple 2V)

C10 = 285µF preferred value 470µF 63V Estimated load for +12V supply = 137mA therefore let REG1 be MC7812. The estimated loads for the –12V and +5V supply are less than 100mA, therefore let REG2 be MC78l05 and REG3 be MC79L12.

Each regulator requires an input capacitance of 0.22µF and an output capacitance of 0.47µF to eliminate high frequency noise. The regulators must also have a minimum load of approximately 2.5mA.

Let C9 and C11 = 0.22µF, C12, C13 and C15 = 0.47µF

R21 = 12/2.5 KΩ = 4K8Ω preferred value 4K7Ω

R22 = 5/2.5 KΩ = 2KΩ Assume the power “ON” LED D3 has an If of 10mA and Vf = 3V then the voltage across resistor R29 = (12 – 3)V.

R29 = 9/10 KΩ = 900Ω preferred value 910Ω 24V Supply Calculations: The 24V Zener D1 is fed from the raw positive supply via R20. Assume supply variation 25V to 27V, and load variation 2mA to 19mA. Let minimum current through D1 = 5mA then current through R20 at V = 25V is 24mA, and voltage across R20 = 1V.

R20 = 1/24 KΩ = 41.7Ω preferred value 39Ω Maximum current through R20 and D1 occurs when V=27V. I = 3/0.039 mA = 76.9mA Power Dissipation R20 = 3*76.9 mW = 231mW note use ½ W resistor. Current through zener diode D1 = 74.9mA, Pt = 24*74.9 mW = 1.8W Select D1 as IN 5359B (24V, 5W).

To limit high frequency noise select C16 = 0.1µF 11V Supply Calculations: The 11V Zener D2 is fed from the –12V supply via R23. Assume load variation 2mA to 19mA.

Page 131: Electronics Made Easy

Let minimum current through D2 = 5mA then current through R23 at V = -12V is 24mA, and voltage across R23 = 1V.

R23 = 1/24 KΩ = 41.7Ω preferred value 39Ω Power Dissipation R23 = 1*24 mW = 24mW note use 0.25 W resistor. Current through zener diode D2 = 22mA, Pt = 11*22 mW = 0.242W Select D2 as BZX85 11V (11V, 1.3W).

To limit high frequency noise select C14 = 0.1µF Component List:

R1, 47KΩ 0.25W MF R2, 4K7Ω 0.25W MF R3, 470Ω 0.25W MF R4, 47KΩ 0.25W MF R5, 1KΩ 0.25W MF R6, 100KΩ 0.25W MF R7, 10KΩ 0.25W MF R8, 3KΩ 0.25W MF R9, 10KΩ 0.25W MF R10, 10KΩ 0.25W MF R11, 10KΩ 0.25W MF R12, 10KΩ 0.25W MF R13, 10KΩ 0.25W MF R14, 10KΩ 0.25W MF R15, 4K7Ω 0.25W MF R16, 4K7Ω 0.25W MF R17, 47KΩ 0.25W MF R18, 47KΩ 0.25W MF R19, 47KΩ 0.25W MF R20, 39Ω 0.5W MF R21, 4K7Ω 0.25W MF R22, 2KΩ 0.25W MF R23, 39Ω 0.25W MF R24, 6K8Ω 0.25W MF R25, 100KΩ 0.25W MF R26, 100KΩ 0.25W MF R27, 15KΩ 0.25W MF R28, 200KΩ 0.25W MF R29, 910Ω 0.25W MF

Vr1 1MΩ linear Vr2 5KΩ 10 turn Vr3 10KΩ 10 turn C1, 100pF Silvered Mica C2, 100pF Silvered Mica

C3, 47pF Silvered Mica C4, 0.1µF polyester or ceramic C5, 0.1µF polyester or ceramic C6, 100pF Silvered Mica

C7, 0.01µF Miniature Layer Polyester C8, 2200µF Electrolytic 63V C9, 0.22µF polyester C10, 470µF Electrolytic 63V C11, 0.22µF polyester C12, 0.47µF polyester C13, 0.47µF polyester C14, 0.1µF polyester C15, 0.47µF polyester D1, IN5359B (5W 24V) D2, BZX85 11V D3, red led (Vf=3V, If=10mA) REC1, 1.6A, 100V Diode Bridge REC2, 1.6A, 100V Diode Bridge REG1, MC7812 REG2, MC78L05 REG3, MC79L12 Tr1, BC109 Tr2, BC109 Tr3, BC109 IC1, 74LS90 IC2, MC14018BCP IC3, MC14018BCP IC4, MC14018BCP IC5, MC14018BCP IC6, MC14018BCP IC7, MC14018BCP IC8, CA3140 IC9, OP07 IC10, OP07 IC11, 3140 Sw1 to Sw3, 3* push button switches DPDT latched together. Sw4, SP 12 way rotary switch (stop set for 7 way) Sw5, SPDT miniature toggle or rocker switch Sw6, SPDT miniature toggle or rocker switch Sw7, SPDT miniature toggle or rocker switch Sw8, DPDT miniature toggle or rocker switch (1A,240V)

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Sw9, SPDT miniature toggle or rocker switch. Sk1, Red 1mm Socket. Sk2, Red 1mm Socket. Sk3, Red 4mm Socket. Sk4, Black 4mm Socket. Sk5, Fused IEC Chassis Plug with 250mA fuse. 4 off 8 way Turned Pin DIL Sockets 1 off 14 way Turned Pin DIL Socket 6 off 16 way Turned Pin DIL Sockets T1, Transformer 12VA, 240V primary, 2* 20V 0.3A secondary winding.

Page 133: Electronics Made Easy

11) General Purpose Oscillator

Design a general purpose oscillator to provide sine or square wave output in the range 1Hz to 30KHz (see fig 13). The oscillator can either be battery powered or powered from a dual 12V or 15V supply.

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Component Data: CA3140

Vs + 4V to +36V or ±18V max, Pt 630mW Open Loop Gain 100db Calculating Frequency Ranges: F = 1/(2.684RC)

Selecting R to be variable between 100KΩ and 1M1Ω, the following frequency ranges can be calculated:

C R = 100KΩ R = 1M1Ω Freq Hz Freq Hz 100pF 37.3K 3.39K 1000pF 3.73K 339 10000pF 373 34

0.1µF 37 0.3 Therefore a frequency range of 0.3Hz to 37KHz can be achieved with 4 range switch positions. Select: Sw1 to be 2 pole 6 way rotary switch

C1 and C5, 0.1µF (Miniature Layer 10% tol) C2 and C6, 10000pF (Silvered Mica 1% tol) C3 and C7, 1000pF (Silvered Mica 1% tol) ..C4 and C8, 100pF (Silvered Mica 1% tol)

R1 and R2, 100KΩ Vr1 1MΩ Double ganged linear potentiometer. For the oscillator to produce sinusoidal oscillations the gain must be controlled at exactly 3 times.

Let R3 = 4K7Ω then as G1 = [R3 + R4 + Vr2(mid range)]/R3

3*4K7Ω - 4K7Ω = R4 + Vr2 (mid Range) = 9K4

Let R4 = 9K1Ω preferred value

therefore Vr2 = 2*300Ω = 600Ω preferred value 1KΩ For a square wave output the sine wave output of the first stage must be amplified at least 100 times for best results. This will result in the saturation of the waveform at approximately 2v below rail voltage.

Selecting R5 = 10KΩ and Gain greater than 100* R5 = R6 (as stage 1 output impedance is low compared with R5)

G2 = (R7 + R6)/R6 if R7 is 100* R6 then G2 = 101* and R7 = 1MΩ Sw2 selects either the sinusoidal waveform from IC1 or the square waveform from IC2.

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IC3 and IC4 have a minimum gain of 2* therefore let G3 and G4 equal 2*. The maximum input to IC3 for an unsaturated output is approximately half the output from either IC1 or IC2, therefore let Vr3 = R8. Vr3 + R8 must be selected to have a minimal load on the previous stage both to limit power consumption and not to overload the stage (Pt of CA3140 is 630mW). Vr3 must also have a low impedance in comparison with R9.

Let Vr3 = 1KΩ then R8 = 1KΩ

Select R9 = 30KΩ then for G3 = 2, R10 and R11 are also equal to 30KΩ. If the gain of IC4, G4 is equal to 2* then the maximum possible offset of Vr4 in either direction will be (V – 2V)/2. The mid position of Vr4 should be at zero volts.

Selecting Vr4 at 1KΩ, R14, R15 and R16 will be 30KΩ

For a power supply of ±9V: Maximum offset voltage at Vr4 = (9-2)/2 = 3.5V, 7V across Vr4, and 11V across R12 + R13.

If Vr4 = 1KΩ then R12 + R13 = 11/7 KΩ = 1.57KΩ.

As R12 = R13 let R12 = 750Ω and R13 = 750Ω preferred values.

For a power supply of ±12V: Maximum offset voltage at Vr4 = (12-2)/2 = 5V, 10V across Vr4, and 14V across R12 + R13.

If Vr4 = 1KΩ then R12 + R13 = 14/10 KΩ = 1.4KΩ.

As R12 = R13 let R12 = 680Ω and R13 = 680Ω preferred values.

For a power supply of ±15V: Maximum offset voltage at Vr4 = (15-2)/2 = 6.5V, 13V across Vr4, and 17V across R12 + R13.

If Vr4 = 1KΩ then R12 + R13 = 17/13 KΩ = 1.31KΩ.

As R12 = R13 let R12 = 620Ω and R13 = 620Ω preferred values. By inspection the maximum power dissipation occurs in resistor chain R12-Vr4-R13 at 15V. Power(R12) = (8.52)/620 = 0.117W, therefore all resistors are ¼ W. The total circuit load is in the region of 25 mA, therefore the oscillator could be powered from two 9V PP3 batteries. Components List:

R1, 100KΩ 0.25W MF R2, 100KΩ 0.25W MF R3, 4K7Ω 0.25W MF R4, 9K1Ω 0.25W MF R5, 10KΩ 0.25W MF R6, 10KΩ 0.25W MF R7, 1MΩ 0.25W MF R8, 1KΩ 0.25W MF R9, 30KΩ 0.25W MF R10, 30KΩ 0.25W MF R11, 30KΩ 0.25W MF R12, see text

R13, see text R14, 30KΩ 0.25W MF R15, 30KΩ 0.25W MF

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R16, 30KΩ 0.25W MF

Vr1, 1MΩ Double ganged linear potentiometer. Vr2, 1KΩ 10 turn lin potentiometer Vr3, 1KΩ 10 turn lin potentiometer Vr4, 1KΩ 10 turn lin potentiometer

C1, 0.1µF (Miniature Layer 10% tol) C2, 10000pF (Silvered Mica 1% tol) C3, 1000pF (Silvered Mica 1% tol) C4, 100pF (Silvered Mica 1% tol)

C5, 0.1µF (Miniature Layer 10% tol) C6, 10000pF (Silvered Mica 1% tol) C7, 1000pF (Silvered Mica 1% tol) C8, 100pF (Silvered Mica 1% tol) IC1 to IC4, CA3140 Sw1, 2 pole, 6 way rotary switch (locking pin set for 4 way) Sw2, SPDT toggle or rocker switch Sw3, SPDT toggle or rocker switch Sw4, DPDT toggle or rocker switch Note: power supply switching not shown on circuit diagram. Note: contact rating of switches must be greater than 25 mA at 15V dc. Sk1 BNC chassis mounting socket. 4 off 8 way DIL Turned pin sockets

Page 137: Electronics Made Easy

12) Pulse Counter

Design a five digit pulse counter with a sample time of 10µs to 100s and capable of sampling frequencies up to 1MHz. The sample error should be of the

order of ±1 digit. There should also be a facility for an external sample control. The pulse counter should accept pulses from 2V to 50V. Component Data: MC14082BCP MC14011BCP BC109 CMOS CMOS Ic max, 100mA Dual 4 Input AND Quad 2 Input NAND hfe, 200-800 Supply 3V to 18V Supply 3V to 18V Vceo, 20V. Ft = 300MHz MC14001BCP MC14018BCP (CMOS) MC14049BCP (CMOS) CMOS /n (/10) Hex Inverting Buffer

Quad 2 Input NOR Supply 3V to 18V Supply 3V to 18V Supply 3V to 18V MC14040BCP (CMOS) MC14511BCP (CMOS) XTAL 1MHz

12 bit Binary Counter BCD to 7-segment Temperature Stability

Supply 3V to 18V Latch/Driver 50ppm -10°C to +60°C Supply 3V to 18V Load Capacitance 30pF

7 Segment LED Display LED Red LED Green Colour-Green Vf = 3V Vf = 3V

Size 0.3 in If = 10mA If = 20mA Common Cathode If max = 25mA If max = 25mA Vf = 2V at If = 10mA IN4148 (fast signal diode) Vrrm = 75V, If av = 75mA Vf = 1V at If = 10mA Figure numbers 14, 15 and 16 show the circuit diagram of the pulse counter. The display is formed by five identical counter/driver circuits cascaded together. Each stage is reset at the count of 10 or a binary count of 1010 and the reset pulse is used to feed the next stage. The reset pulse of the final stage feeds a latch, which drives the display overflow indication. The sample time is controlled either by the precision crystal oscillator

which drives a series of ÷10 modules or an external pulse (first pulse to start, second pulse to stop), of 8.4V to 12V. The precision crystal oscillator provides the clock frequency which when combined with reset and start controls produces an accurate sample pulse, figure number 17 illustrates the timing functions involved in this process. Counter/Driver Design: As the 5 stages of the design are identical only the first stage need be considered.

The supply voltage Vs is selected at 12V (supply voltage range for CMOS, 3V to 18V) therefore the input pulse at pin 10 of the binary counter IC19 should be 0.7Vs to Vs. The binary output of IC19 feeds the display driver IC20 which provides a nominal 12V feed to the 7 segment common cathode display Disp1. Outputs Q0 to Q3 equate to 20 to 23, for the display to count 0 through to 9 the binary equivalent of 10 ie 1010 must be used to reset display Disp1 to 0 and increment the next display by 1.

Page 138: Electronics Made Easy

For binary 1010 or 10 decade: Q0 = 0, Q1 = 1, Q2 = 0, Q3 = 1 0 + 2 + 0 + 8 = 10 As the reset pulse is “Logic 1”, invert Q0 and Q2 (Ic14b and Ic14c) and feed into 4 input AND gate Ic15a. The output of Ic15a feeds the clock input (pin 10 of 4040B), of the next stage. As display reset is required either as a function of the count or to clear the 5 digit display prior to restarting diodes are used to buffer the reset signals. Let D4 and D5 be high speed switching diodes IN4148. To maintain 0V on

pin 11 of the 4040B until reset a 10KΩ resistor is used (R12 for stage 1). Each segment of Disp1 has Vf = 2V and If = 10mA therefore to limit If to 10mA a series resistor must be included in each segment feed.

R (R13 to R19) = (12 – 2)/10 KΩ = 1KΩ. Display Overflow Design:

The final display stage feeds a latch Ic13c and Ic13d, which is reset when the Reset push button switch PB2 is operated. If the final stage counts to 10 the latch output will switch from “Logic 1” to “Logic 0”. This is then fed via inverting buffer Ic11e to transistor switch Tr6 which operates the display overflow indicator LED1. When the output of Ic11e rises to “Logic 1” or 12V: Voltage across R56 = 12V - 0.6V = 11.4V If Tr6 is a BC109 (hfe 200) and LED1 Red LED (Vf 3V, If 10mA) then:

R57 = (12 – 3)/10 KΩ = 900Ω preferred value 910Ω

R56 ≤ 11.4/Ib where Ib = 10/200 mA

R56 ≤ 11.4 * 200/10 KΩ = 228KΩ

Let R56 = 47KΩ Reset Function: When the reset push button PB2 is operated 12V or “Logic 1” is fed to the latch Ic13a and Ic13b. R52 holds the latch input at 0V or Logic “0” until PB2 is

operated. Select R52 as 10KΩ, which is sufficient to hold the gate input at 0V.

The latch output (Logic 0) is fed to the timing circuit (NOT R) and buffered via inverter Ic14a to the reset line. The latch is reset by the timing pulse, which remains at “Logic 1” for the duration of the timing period (see figure 17). Input Circuit: The input circuit should be capable of responding to a 2V pulse while withstanding a 50V pulse. The circuit should not be damaged by inadvertent cross connection of the input. Select D1, D2 and D3 as IN4148, assume Vf = 0.6V at low current.

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If LED2 is a Green LED with If = 20mA and Vf = 3V then:

R53 = (12-3)/20 KΩ = 450Ω preferred value 470Ω Then Ic = 9/0.47 mA = 19.1mA.

If Tr5 is BC109 then hfe = 200 and Ib = 19.1/200 mA = 95.7µA

R55 = (0.6 + 0.6 –0.6)/0.0957 KΩ = 6K27Ω, select R55 as 4K7Ω Voltage across R55 for Tr5 to “switch on” = 4.7 * 0.0957 V = 0.45V

For a 2V pulse R54 ≤ (2 – 0.45 – 0.6)/0.0957 KΩ = 9K93Ω

Let R54 = 9K1Ω The maximum input voltage is limited by the power rating of R54. For 0.5W: P = V2/R54 where V is the voltage across R54. V2 = 0.5 * 9K1 therefore V2 = 4550, and V = 67.5V Maximum input voltage = 67.5 + 1.2 V = 68.7V The inverted input signal from Tr5 is fed via a NAND gate Ic10b to the display input at pin 10 of IC19. The Timing Pulse is fed to Ic10b via inverter Ic11f to gate the input signal (ie only enable the input signal during the timing pulse). Precision Oscillator Design:

The crystal oscillator uses a single stage emitter follower transistor amplifier with positive feedback provided via the 1MHz quartz crystal. The frequency of oscillation is determined by the physical dimensions of the crystal (see fig 14). Select Tr1 as BC109 For DC bias: 12V = 2(Ic + Ib)R2 + (Ic + Ib)R3.

Select R2 4K7Ω and select R3 for approximately Ve 0.6V. Note this will provide an equal M-S ratio at the output of Tr2 0.6 = (Ic + Ib)R3 12 = 2(Ic + Ib)R2 + 0.6 Ic + Ib = 11.4/2*4.7 mA = 1.24mA

R3 = 0.6/1.24 KΩ = 484Ω preferred value 470Ω Ic + Ib = 12/(2R2 + R3) = 12/(9.2 +.47) mA = 1.24mA Vc = 12 – (Ic + Ib)R2 = 6.172V Ve = (Ic +Ib)R3 = 0.58V Vb = Ve + 0.6 = 1.18V IbR1 = Vc –Vb = 6.17 – 1.18 = 4.99V If hfe = 10, then Ic = 10Ib and 11Ib = 1.24mA

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Ib = 0 113mA and R1 = 4.99/0.113 KΩ = 44.16KΩ

Let R1 = 47KΩ then Ib = 4.99/47 mA = 0.106mA and Ic = 1.24 – 0.106 = 1.13mA Therefore hfe = 1.13/0.106 = 10.7. Select C1 and C2 = 100pF. The trim capacitor in series with the crystal Ct should provide slight frequency adjustment. In practice it will be set at approximately mid range. Let Ct = 5pF-65pF.

To convert the sinusoidal waveform to a CMOS compatible input a transistor

is used in switch mode, powered from the 12V supply. Select R5 = 10KΩ and Tr2, BC109. The switching point of the transistor Tr2 is achieved when the base voltage Vbe is 0.6V and sufficient drive current is provided to saturate the transistor. To drive the collector to 0V, Ic = V/R5 = 5/10K = 0.5mA

Gain hfe is 200 to 500* therefore Ib = 0.5/200 mA = 2.5µA

For Tr2 to saturate at 0.1V above Vbe the base resistor R4 = 0.1/0.0025 KΩ R4 =40KΩ

It follows that for an input of 1mV above Vbe R4 = 400Ω As this could adversely affect the dc bias conditions of the previous stage a R-C network is used to feed Tr2.

Let R4 = 47KΩ. If C3 = 47pF then Xc = 1/(2πFC)

For Frequency 1MHz, Xc = 1012/(2π*1*106*47) = 3K39Ω To drive IC1 (4018B) a peak voltage greater than 0.7 * 12V must be generated. The 4018B divider is a 16 pin package. Pin 8 is connected to 0V and pin 16 supply volts.

For ÷10 connections are as follows: Pin 14 input. Pins 1 and 13 are linked and form the output. Pins 15, 10 and 8 connected to 0V. Dividers IC1 to IC8 are cascaded to form the required number of divide stages. Sw1 (Sample Time) selects the required output and feeds the signal to the pulse conditioning stages. An additional position fed to a BNC chassis socket provides external sample time control. To reduce high frequency noise, select C4 as

0.1µF. The period of the clock pulse (leading edge of first pulse to leading edge of second pulse) is as follows: Switch Position Time

1 10µs 2 100µs 3 1ms 4 10ms 5 100ms 6 1s 7 10s 8 100s

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Timing Logic:

Until the start push button PB1 is operated R6 holds the start input of NOR gate Ic9a at “Logic 1”, the other input is taken from Sw1 (Clock Pulse). The output of Ic9a will only go to “Logic 1” when the clock pulse is 0 and PB1 is depressed. Ic9a feeds latch IC9b and Ic9c, the latch is then reset by the clock

pulse (ie when clock pulse goes to “Logic 1”). Let R6 = 10KΩ which will be sufficient to hold the start input at +12V or “Logic 1”. The output of Ic9b, the start latch output, will go to “Logic 0” and reset at the next clock pulse (see Fig 17). The start latch output then feeds NAND gate Ic10a. If the reset is not operated the “NOT R” input to Ic10a will be at “Logic 1”. When the start latch output resets to “Logic 1” the output of Ic10a will go to “logic 0”, Ic11a then inverts the signal to produce a “Logic 1” Timer Start signal (see Fig 17).

The timing pulse generated from the timer logic circuit must be at “logic 1” until the start of the next clock pulse. To achieve this, a stop pulse must

be generated significantly faster than the minimum sample time (greater than 1µs and less than 5µs as the minimum sample time is 10µs and pulse width 5µs).

When the clock pulse is fed to the junction of R8 and R9, Tr4 is “switched ON” via R8 when the clock pulse goes high (ie 12V). R9 then charges capacitor C6 until the base voltage of Tr3 is greater than 0.6V. The transistor Tr3 “switches ON”, pulling the base voltage of Tr4 below 0.6V, thus “switching OFF” Tr4. When the clock pulse goes to “logic 0” capacitor C6 discharges through the parallel combination of R9 and R10 to reset the circuit. The pulse generator circuit produces a negative pulse on the leading edge of each clock pulse, as the first pulse at timer start is not required a delay circuit must be incorporated into the design to remove it. The delay time must

be greater than 5µs but less than 10µs. Select Tr3 and Tr4 as BC109 Transistors with hfe = 200

If R11 is 10KΩ, then maximum value of R8 and R9 will be 200*10KΩ approx.

Select R8 and R9 as 10KΩ, R10 > 0.6R9/12 to allow Tr3 to saturate.

R10 > 500Ω, let R10 = 1KΩ.

Neglecting Tr3 Ib, the voltage across C6 = 1K*12/(1K + 10K) = 1.09V.

Pulse Width T = 0.6*C6*R9/12 = C6*R9/20

For Pulse Width of 5µs C6 = 5*20/10000 µF = 0.01µF To reset the transistor switch C6 must discharge through the parallel

combination of R9 and R10. C6 should be discharged fully before the next positive going clock pulse.

Discharge Time T = C6*Rt where Rt = 1*10/(1 + 10) KΩ

Discharge Time T = 0.01* 909 µs = 9.09µs

As at minimum pulse width discharge time should be 5µs or less for full discharge of capacitor C6, base voltage should be as follows:

Discharged Voltage = 5*1.09/9.09 = 0.600V

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As the base voltage was 1.09V then the base voltage at the next clock pulse would be 0.49V which would significantly shorten the pulse width of the stop pulse as C6 would start to charge from 0.49V instead of 0V. In practice the base current of Tr3 would tend to offset this effect by increasing the discharge current of C6.

The timer start signal from the output of Ic11a and the pulse signal from the collector of Tr4 are used to generate the stop signal. As Ic9d is a NOR gate the output will only be Logic “1” (Stop pulse) when the output of Tr4 and Ic11b are Logic “0”. To prevent both start and stop pulses occurring the timer start signal is fed through a time delay circuit formed by R7 and C5.

T = 0.7CR where C = C5, R = R7 T must be greater than the pulse width of the pulses from Tr4 but less

than the fastest timing pulse (ie T > 5µs but < 10µs).

Let T = 7µs and C5 = 0.001µF (1000pF), then R7 = T/0.7*C5

R7 = 7*10-6/0.7*0.001*10-6 = 1/0.0001 = 10KΩ The stop pulse is then fed to a latch formed by Ic12a and Ic12b. The

output of Ic12a will go to Logic “0” until reset by the inverted NOT R signal from the Reset Push Button latch. The output from Ic12a and the Timer Start pulse from Ic11a are then fed to NOR gate Ic12c, the output is then inverted via Ic11d to produce the timing pulse.

The Timing Pulse is then used to reset the reset latch and enable the

input pulse signal via Ic11f and Ic10b. Power Calculations:

Display Resistors, R = 1KΩ, I = 10mA, P = I2R = 0.012*1000 = 100mW. With all segments “ON” (number 8), Current Load per Display = 70mA Assume Total Load per Display 80mA (includes 4040B and 4511B) Display Overflow Load is approximately 10mA. Input Circuit Load = 20mA. R53 power = (V – Vf)If = 9*0.02 = 180mW Precision Oscillator Load = 3.4mA (osc)+ 40mA(dividers) = 43mA. Timing Logic Load say 15mA approx. Estimated Total Load = 488mA at 12V. Use 12V, 0.5A Power Supply to power the pulse counter.

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Component List:

R1, 47KΩ 0.25W MF R2, 4K7Ω 0.25W MF R3, 470Ω 0.25W MF R4, 47KΩ 0.25W MF R5, 10KΩ 0.25W MF R6, 10KΩ 0.25W MF R7, 10KΩ 0.25W MF R8, 10KΩ 0.25W MF R9, 10KΩ 0.25W MF R10, 1KΩ 0.25W MF R11, 10KΩ 0.25W MF R12, 10KΩ 0.25W MF R13, 1KΩ 0.25W MF R14, 1KΩ 0.25W MF R15, 1KΩ 0.25W MF R16, 1KΩ 0.25W MF R17, 1KΩ 0.25W MF R18, 1KΩ 0.25W MF R19, 1KΩ 0.25W MF R20, 10KΩ 0.25W MF R21, 1KΩ 0.25W MF R22, 1KΩ 0.25W MF R23, 1KΩ 0.25W MF R24, 1KΩ 0.25W MF R25, 1KΩ 0.25W MF R26, 1KΩ 0.25W MF R27, 1KΩ 0.25W MF R28, 10KΩ 0.25W MF R29, 1KΩ 0.25W MF R30, 1KΩ 0.25W MF R31, 1KΩ 0.25W MF R32, 1KΩ 0.25W MF R33, 1KΩ 0.25W MF R34, 1KΩ 0.25W MF R35, 1KΩ 0.25W MF R36, 10KΩ 0.25W MF R37, 1KΩ 0.25W MF R38, 1KΩ 0.25W MF R39, 1KΩ 0.25W MF R40, 1KΩ 0.25W MF R41, 1KΩ 0.25W MF R42, 1KΩ 0.25W MF R43, 1KΩ 0.25W MF R44, 10KΩ 0.25W MF R45, 1KΩ 0.25W MF R46, 1KΩ 0.25W MF R47, 1KΩ 0.25W MF R48, 1KΩ 0.25W MF R49, 1KΩ 0.25W MF R50, 1KΩ 0.25W MF R51, 1KΩ 0.25W MF R52, 10KΩ 0.25W MF R53, 470Ω 0.25W MF R54, 9K1Ω 0.5W MF R55, 4K7Ω 0.25W MF, R56, 47KΩ 0.25W MF R57, 910Ω 0.25W MF C1, 100pF Silvered Mica C2, 100pF Silvered Mica

C3, 47pF Silvered Mica C4, 0.1µF polyester or ceramic C5, 1000pF polystyrene C6, 0.01µF Miniature Layer Polyester D1 to D13, IN4148 LED1, Red LED (Vf=3V, If=10mA) LED2, Green LED (Vf = 3V, If = 20mA) Disp1 to Disp5, 7 Segment, Common cathode, Green LED Display, Size 0.3 inch.

(Vf = 2V, If = 10mA) Tr1, BC109 Tr2, BC109 Tr3, BC109 Tr4, BC109 Tr5, BC109 Tr6, BC109 IC1, MC14018BCP IC2, MC14018BCP IC3, MC14018BCP IC4, MC14018BCP IC5, MC14018BCP IC6, MC14018BCP IC7, MC14018BCP IC8, MC14018BCP IC9, MC14001BCP IC10, MC14011BCP IC11, MC14049BCP IC12, MC14001BCP IC13, MC14001BCP IC14, MC14049BCP IC15, MC14082BCP IC16, MC14082BCP IC17, MC14049BCP IC18, MC14082BCP IC19, MC14040BCP IC20, MC14511BCP IC21, MC14040BCP IC22, MC14511BCP IC23, MC14040BCP IC24, MC14511BCP IC25, MC14511BCP IC26, MC14040BCP IC27, MC14511BCP IC28, MC14040BCP PB1 and PB2, push button switches. Sw1, Single pole, 12 way, rotary switch. Sk1, Chassis mounted BNC socket. 15 off, 14 way DIL Turned Pin Sockets. 13 off, 16 way DIL Turned Pin Sockets.

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13) Notch Filter Design a notch filter to operate between 50Hz and 25KHz. The filter unit must be capable of either amplifying or rejecting selected frequencies over the bandwidth of the filter. The maximum input signal will be a function of supply

voltage, but it is unlikely to rise above ±1V. Component Data: CA3140

Supply Voltage, +4V to +36V or ±2V to ±18V. Max Diff Input Voltage, ±8V Slew Rate, 9V/µs Design of low Pass and High Pass Elements: Low Pass Filter

The cut off frequency is defined as 1/2πRC.

Assuming 1MΩ log scaled potentiometers are used, and a series resistance of 1KΩ, then the value of R will range from 1KΩ to 1M01Ω.

Calculating Values of Fc:

R Ω C pF Fc Hz 1K 2200 72.3K 1K 3300 48.2K 1K 4700 33.9K 1K 6800 23.4K 2K 2200 36.2K 2K 3300 24.1K 2K 4700 16.9K 2K 6800 11.7K 11K 2200 6.58K 11K 3300 4.38K 11K 4700 3.08K 11K 6800 2.13K 101K 2200 716 101K 3300 477 101K 4700 335 101K 6800 232 1M001 2200 72.3 1M001 3300 48.2 1M001 4700 33.8 1M001 6800 23.4 It follows that capacitors of either 3300pF or 4700pF would satisfy the

design requirements. Let C1 and C2 be 3300pF extended foil polystyrene, R1 and

R2 be 1KΩ 0.25W MF, Vr1 = 1MΩ Log double ganged potentiometers. As a single stage filter will produce an attenuation of 40db/decade a two

stage design should be unnecessary for this application.

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As high impedance components are used select IC1 as CMOS operational amplifier CA3140.

For a single stage design K = 1.58. R3 =(K-1)R4 if K = 1.58 then:

If R4 = 3K3Ω then R3 = 0.58 * 3K3 = 1.914KΩ preferred value 2KΩ If R4 = 4K7Ω then R3 = 0.58 * 4K7 = 2.726KΩ preferred value 2K7Ω If R4 = 6K2Ω then R3 = 0.58 * 6K2 = 3.596KΩ preferred value 3K6Ω

Let R4 = 6K2Ω 0.25W MF and R3 = 3K6Ω 0.25W MF. The circuit diagram is shown in Fig 18. The LPF plot in fig 19 shows a cut

off frequency Fc of approximately 48Hz at the maximum resistance. The stage gain of the filter is shown to be 4db.

G db = 20log G* The filter constant K = 1.58 and K is a significant factor in the gain of

the filter.

If gain, G* = 1.58. G db = 20log 1.58 = 20 * 0.1987 = 3.97db. As the cut off frequency of the high pass filter is the same as the low

pass filter, the design values can be identical, see fig 20, therefore:

R5 = R1 = 1KΩ 0.25W MF, R6 = R2 = 1KΩ 0.25W MF, Vr1 = Vr2 = 1MΩ log double ganged potentiometer R7 = R3 = 3K6Ω 0.25W MF, R8 = R4 = 6K2Ω 0.25W MF, IC1 = IC2 = CA3140. Note: Vr1 and Vr2 are ganged together. It is important that when the shaft

or spindle of Vr2 is joined to the spindle end of Vr1, that mechanical adjustment is possible as the potentiometers must be aligned for correct resistance.

Attenuated Notch Design With DPDT switch Sw1 in – position the inputs of Low Pass and High Pass

filters are linked (Sw1a). The filter outputs are then fed to a Summer Amplifier IC3 the output of which is fed to the final follower stage via Sw1b, see fig 18.

The summing amplifier is a non inverting amplifier with a nominal gain of

2*. The non inverting input at pin 3 has two inputs fed via R10 and R11. At all frequencies outside the notch either the HPF or the LPF will have a maximum output while the other output will be at approximately 0V, therefore a voltage divider is formed by R10 and R11. As R10 = R11 then under stable conditions the overall gain will be at unity.

Summer Gain = (R12 + R9)/R9 where R9 = Ri Ri = (R10 + Ro1)(R11 + Ro2)/(R10 + R11 + Ro1 + Ro2) Where, Ro1 and Ro2 are the output impedances of IC1 and IC2.

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If R9 = R12 then gain =2. Let R9 = 10KΩ then R12 = 10KΩ and Ri = 10KΩ If Ro1 and Ro2 are small with respect to R10 and R11 they can be

neglected. In this case Ro1 and Ro2 are approximately 5Ω. If R10 and R11 are 20KΩ then Ri = 10KΩ.

The summer output is then fed via Sw1b to voltage divider R13-Vr3-R14 to

set the overall gain to unity. The voltage follower IC3 provides a low impedance output. In this mode overall gain before attenuation, is approximately 1.58* or 4db. Fig 22 and 23 show gain and frequency plots for the attenuating notch filter. The overall gain has been adjusted to unity.

The Amplifying Notch With Sw1 in the + position all frequencies above or below the cut off

frequency Fc are attenuated at 40db per decade. The input is fed initially to the HPF the output then feeds the LPF. The

output of the LPF is switched to the voltage divider R13-Vr3-R14 via Sw1b. Fig 21 shows the output plot with Vr3 set for unity gain in the attenuating notch mode (switch position -). The plot shows a slight attenuation at Fc, approximately 2db.

The resistor chain must therefore accommodate a filter gain of 4db in one

mode and 2db in the other. Gain db = 20log G* For a gain of 2db, G* = 1.26*. Minimum variation in attenuation: 1/1.26 to 1/1.58 or 0.79 to 0.63

If Vr3 is 2K2Ω and R14 = R15 = 1KΩ then attenuation will vary between: 1/4.2 = 0.24 and 3.2/4.2 = 0.76.

If R14 =1K2Ω and R13 = 680Ω then attenuation will vary between: 1.2/4.08 = 0.29 and 3.4/4.08 = 0.83

If R14 =1K5Ω and R13 = 390Ω then attenuation will vary between: 1.5/4.09 = 0.37 and 3.7/4.09 = 0.90

Let R14 = 1K5Ω and R13 = 390Ω. Power Requirements

The input signal level will be limited to ±8V or 2V less than the rail voltages. Assuming the maximum input is required the supply should be between

±10V and ±15V.

For an input of ±1V the minimum supply must be greater than ±3V. The supply loading is estimated as 10mA per operational amplifier (ie 40mA). All resistors are rated at 0.25W.

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Components List

R1, 1KΩ 0.25W MF, R2, 1KΩ 0.25W MF, R3, 3K6Ω 0.25W MF, R4, 6K2Ω 0.25W MF, R5, 1KΩ 0.25W MF R6, 1KΩ 0.25W MF, R7, 3K6Ω 0.25W MF, R8, 6K2Ω 0.25W MF, R9, 10KΩ 0.25W MF, R10, 20KΩ 0.25W MF, R11, 20KΩ 0.25W MF, R12, 10KΩ 0.25W MF, R13, 390Ω 0.25W MF, R14, 1K5Ω 0.25W MF,

Vr1, 1MΩ log double ganged potentiometer. Vr2, 1MΩ log double ganged potentiometer. Vr3, 2K2 Lin potentiometer. C1 to C4, 3300pF extended foil polystyrene IC1 to IC4, CA3140.

Sw1 DPDT Toggle Switch

4 off, 8 way DIL Turned Pin Sockets

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14) Non Linear Amplifier or Characteriser When a transducer signal is non-linear it is sometimes necessary to

linearise the signal where direct measurement is required or when the signal is to be used in a control system. Develop a non-linear amplifier that can be used to linearise a range of input signals and provide a 0V to 1V output.

The obvious solution would be to use a series of amplifiers set at

different gains to correct the non-linearity in stages. Each amplifier would be selected at the required set point and de-selected at the next set point. The subsequent stage would have an offset equal to the maximum output of the previous stage to ensure a “bump-less transition.

A pre-amplifier should be used to condition the input signal to range 0V

to 1V. Stage switching can be achieved by switching with reed relays, at the desired set point, but the switching should be anti-bounce and “make before break”.

It is proposed to use eight stages of amplification to condition the non

linear signal (Conditioned to 0V-1V, by the pre-amplifier). Figures 24 to 26 illustrate a range of non-linear signals conditioned to 0V to 1V. Producing correction data for these characteristics should illustrate the majority of conditions.

Using a plot of the characteristic curve a ruler can be used to create

eight sections where the straight line best approximates the curve. The start of each stage is defined by the set point with respect to the input signal and the slope of the straight line necessary to linearise the signal or amplifier gain. The offset of the next stage is determined by the required output at the end of each stage. The offset for stage 2 (O2) would be the desired output at SP2.

To define the Stage Gain:

Gain = δVout/δVin

Where δ is the rate of change at that point. For Stage 2: Gain 2 = (O3 – O2)/(SP3 – SP2) At Offset O2 Note: for stage 1 both O1 and SP1 are 0V, and for stage 8 the final offset

and set point readings are 1V. Figure 24 shows a square law characteristic. To achieve best linearity the

positions of the set points are not regular. The co-ordinates are shown below: Set Point Offset Set Point Offset SP1 0V O1 0V SP2 0.174V O2 0.031V SP3 0.319V O3 0.109V SP4 0.450V O4 0.200V SP5 0.593V O5 0.351V SP6 0.778V O6 0.620V SP7 0.869V O7 0.757V SP8 0.926V O8 0.854V

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Calculating Gain: 1st Stage Gain G1 = (0.031 – 0)/(0.174 – 0) = 0.178*

(Offset = 0V) 2nd Stage Gain G2 = (0.109 – 0.031)/(0.317 – 0.174) = 0.078/0.143 = 0.545* (Offset = +31mV) 3rd Stage Gain G3 = (0.200 – 0.109)/(0.450 – 0.319) = 0.091/0.131 = 0.695* (Offset = +109mV) 4th Stage Gain G4 = (0.351 – 0.200)/(0.593 – 0.450) = 0.151/0.143 = 1.056* (Offset = +200mV) 5th Stage Gain G5 = (0.620 – 0.351)/(0.778 – 0.593) = 0.269/0.185 = 1.454* (Offset = +351mV) 6th Stage Gain G6 = (0.757 – 0.620)/(0.869 – 0.778) = 0.137/0.091 = 1.505* (Offset = +620mV) 7th Stage Gain G7 = (0.854 – 0.757)/(0.962 – 0.869) = 0.097/0.093 = 1.043* (Offset = +757mV) 8th Stage Gain G8 = (1.000 – 0.854)/(1.000 – 0.962) = 0.146/0.038 = 3.842* (Offset = 854mV) For the square law characteristic the gain variation was 0.178* to 3.842*

and maximum offset 854mV.

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The co-ordinates for Figure 25 are shown below: Set Point Offset Set Point Offset SP1 0V O1 0V SP2 0.061V O2 0.280V SP3 0.104V O3 0.443V SP4 0.138V O4 0.531V SP5 0.185V O5 0.629V SP6 0.287V O6 0.730V SP7 0.467V O7 0.839V SP8 0.651V O8 0.916V

Calculating Gain: 1st Stage Gain G1 = (0.280 – 0)/(0.061 – 0) = 4.590*

(Offset = 0V) 2nd Stage Gain G2 = (0.443 – 0.280)/(0.104 – 0.061) = 0.163/0.043 = 3.791* (Offset = +280mV) 3rd Stage Gain G3 = (0.531 – 0.443)/(0.138 – 0.104) = 0.088/0.034 = 2.588* (Offset = +443mV) 4th Stage Gain G4 = (0.629 – 0.531)/(0.185 – 0.138) = 0.098/0.047 = 2.085* (Offset = +531mV) 5th Stage Gain G5 = (0.730 – 0.629)/(0.287 – 0.185) = 0.101/0.102 = 0.990* (Offset = +629mV)

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6th Stage Gain G6 = (0.839 – 0.730)/(0.467 – 0.287) = 0.109/0.180 = 0.606* (Offset = +730mV) 7th Stage Gain G7 = (0.916 – 0.839)/(0.651 – 0.467) = 0.077/0.184 = 0.418* (Offset = +837mV) 8th Stage Gain G8 = (1.000 – 0.916)/(1.000 – 0.651) = 0.084/0.349 = 0.241* (Offset = 854mV) For the log characteristic the gain variation was 0.241* to 4.590* and

maximum offset 916mV.

The co-ordinates for Figure 26 are shown below: Set Point Offset Set Point Offset SP1 0V O1 0V SP2 0.120V O2 0.217V SP3 0.201V O3 0.320V SP4 0.282V O4 0.383V SP5 0.722V O5 0.640V SP6 0.799V O6 0.693V SP7 0.836V O7 0.733V SP8 0.899V O8 0.821V

Calculating Gain: 1st Stage Gain G1 = (0.217 – 0)/(0.120 – 0) = 1.808*

(Offset = 0V)

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2nd Stage Gain G2 = (0.320 – 0.217)/(0.201 – 0.120) = 0.103/0.081 = 1.272* (Offset = +217mV) 3rd Stage Gain G3 = (0.382 – 0.320)/(0.282 – 0.201) = 0.063/0.081 = 0.778* (Offset = +320mV) 4th Stage Gain G4 = (0.640 – 0.383)/(0.722 – 0.282) = 0.257/0.440 = 0.584* (Offset = +383mV) 5th Stage Gain G5 = (0.693 – 0.640)/(0.799 – 0.722) = 0.053/0.077 = 0.688* (Offset = +640mV) 6th Stage Gain G6 = (0.733 – 0.693)/(0.836 – 0.799) = 0.040/0.037 = 1.081* (Offset = +693mV) 7th Stage Gain G7 = (0.821 – 0.733)/(0.899 – 0.836) = 0.088/0.063 = 1.397* (Offset = +733mV) 8th Stage Gain G8 = (1.000 – 0.821)/(1.000 – 0.899) = 0.179/0.101 = 1.772* (Offset = 821mV) For the S Curve characteristic the gain variation was 0.584* to 1.808* and

maximum offset 821mV. Figures 24 to 26 show a gain variation of 0.178* to 4.59*, with a maximum offset of 0.916V.

The offset and set point potentiometers should therefore be ranged 0V to

1V and the stage amplifiers should have a gain variation of 0.1* to 10*. Let the pre-amplifier gain be 1* to 10* with offset potentiometer

variation ±1V.

The Pre-Amplifier Design: The pre-amplifier must condition the input signal for 0V to 1V. If the

pre-amplifier is a non-inverting summing amplifier then for a gain of 2* to 20*, the overall gain will be 1* to 10*. This is due to the voltage divider formed by the summing junction. If R1 = R2 then the input signal will be attenuated by 50%, see figure 27.

Let all operational amplifiers be CA3140 as the amplifier must accept

either single or dual supplies.

Component Data: CA3140

Supply Voltage, +4V to +36V or ±2V to ±18V. Max Diff Input Voltage, ±8V Slew Rate, 9V/µs

Maximum Amplifier Gain = (R5 + R6 + Vr2)/R5 Minimum Amplifier Gain = (R5 + R6)/R5 = 2*, therefore let R5 = R6.

Select Vr2 as 1MΩ, then for maximum gain, (R5 + R6 + 1M)/R5 = 20*. As R5 = R6 then (2R5 + 1M)/R5 = 20

20R5 – 2R5 = 1MΩ, therefore R5 = 1000K/18 Ω = 55K6Ω preferred value 56KΩ

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As the input impedance must equal R5, and R1 = R2 (for overall gain 1*), R1 = 2*R5 approx.

R1 = R2 = 2*56KΩ = 112KΩ preferred value 110KΩ

The offset potentiometer Vr1 must provide an offset of ±1V.

Let Vr1 = 2KΩ then voltage gradient 1V/KΩ, if supply voltage ±12V then R3 and R4 will have 11V across them. For ±1V across Vr1 then R3 = R4 = 11KΩ.

The operational amplifier IC1 should be provided with a dual power supply

(ie +12V at pin 7, -12V at pin 4) to allow correct ranging of the input signal. The output of the pre-amplifier feeds each of the eight switched amplifier

stages. To enable the pre-amplifier to be set up correctly, a test point (TP1) should be provided at the amplifier output (terminal post).

Design of the Eight Switched Amplifier Stages:

The design of each stage is identical apart from stage 1 which does not

require a set point potentiometer as SP1 is effectively controlled by the pre-amplifier offset. The first operational amplifier is configured as a differential amplifier, the amplifier output only goes positive when the input at pin 3 is greater than the input at pin 2. If the amplifier is fed with a +12V supply it will have a zero volt output until the input at pin 2 is greater than pin 3.

The output of the differential amplifier feeds a non-inverting summing

amplifier with a gain of 2*. As the offset voltage is also fed to the summing input the overall summer gain can be set at unity.

As the design of each of the eight stages is identical the design of stage

2 will be considered. The following parameters were determined by plotting typical

characteristics see figures 24 to 26: Gain = 0.1 to 10*. Set point variation = 0V to 1V. Offset variation = 0V to 1V.

If Vr4 is 1KΩ then for a 12V supply R17 = 11KΩ.

If Vr18 is 1KΩ then R130 = 11KΩ. To provide a gain variation of 0.1 to 10*, the only practical solution is

to feed the summing amplifier from a voltage divider at the output of the differential amplifier, therefore the gain of the differential amplifier must be set at 10*.

For a differential amplifier, Gain = (Rf + Rin)/Rin

Rf = R, Rin = Rs +Ri.

For stage 2: Rf = R21, R= R20 and Ri = R18 and R19.

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As set point adjustment will marginally affect the value of the input resistance (Rs + R18 and Rs + R19), R18 should be selected to be significantly

greater than Vr4 (1KΩ). Note: Vr4 also feeds the relay switching circuit.

Let R18 be 100KΩ, therefore R19 = 100KΩ.

Gain = 10 = (R21 + 100K)/100K, therefore R21 = 1MΩ – 100KΩ = 900KΩ

Preferred value for R21 = 910KΩ. As R21 = R20, R20 = 910KΩ. For a Gain of 10* with an input of 1V the output of IC4 will be 10V. The

desired output will be 10V to 100mV.

If Vr5 is 2KΩ, then R22/(2K + R22) = 0.1/10 10*R22 = 0.1(R22 + 2K)

9.9*R22 = 200Ω, therefore R22 = 20.2Ω, preferred value 20Ω. The wiper of Vr5 feeds the summing amplifier. The resulting source

impedance will vary between 19.6Ω and 1KΩ approximately, similarly the offset potentiometer will affect the source impedance by 0Ω to 1KΩ. The values of R23 and R24 should therefore be significantly higher than 1KΩ.

For a non-inverting amplifier Gain = (R26 + R25)/R25 and R25 = Rin. If R26 = R25 the amplifier gain = 2*. If R23 = R24 then overall gain will be unity.

Selecting R26 as 100KΩ:

R25 = 100KΩ, and Rin = 100KΩ. Neglecting source resistances, Rin = (R23 * R24)/(R23 + R24).

As R23 = R24, 100KΩ = R23/2, therefore R23 = R24 = 200KΩ. The output of IC5 feeds a voltage follower IC38 via R27 and RL2 contact.

R27 allows connection of two stages during the relay switching process. It would be undesirable to open circuit the input to the voltage follower as output spikes would be generated at the switching point. R27 should be selected to not

load IC5 (ie greater than 1KΩ). Let R27 be 10KΩ. At the switching point the voltage output of the stage switching in and

the stage switching off should be equal hence a “bump less” transfer should be achieved.

Design of the Relay Switching Circuit:

The relay switching circuit selects the required stage when triggered by

the conditioned input (input at TP1), compared to the set point value (ie the wiper of Vr4 for stage 2, SP2). When the input is above the set point the comparitor output goes from logic “0” to logic “1” (ie 0V to 10V). The logic circuit must then switch in the desired stage whilst maintaining the existing connection for the operating time of the relay. This delay must be maintained for a rising or a falling input.

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The operation is best described considering the operation of the stage 2 relay RL2 and the adjacent stages. For an increasing input signal: The output of IC20 goes to 10V or Logic “1”. One input of NOR gate IC22b goes to logic “1”, as any logic “1” on the input will produce a logic “0” on the output. The output of IC22b goes to logic “0”, and feeds NOR gate IC22c. If the other input to IC22c is at logic “0” then Tr2 is switched “ON” and RL2 energised, hence connecting Stage 2 to the voltage follower output. Note the other input to IC22c will be at logic “0” if the input voltage is below the SP3 level. One input of IC18a (NAND Gate) goes to logic “1”, then after the timer (R94-C1) times out at 0.7CR, the second input goes to logic “1” and the output of IC18a goes to logic “0”. This switches “OFF” Tr1 hence de-energising RL1. Stage 1 is then disconnected from the voltage follower output. The output of IC23 goes to 10V or Logic “1”. One input of NOR gate IC24a goes to logic “1”, as any logic “1” on the input will produce a logic “0” on the output. The output of IC24a goes to logic “0”, and feeds NOR gate IC24b. If the other input to IC24b is at logic “0” then Tr3 is switched “ON” and RL3 energised, hence connecting Stage 3 to the voltage follower output. Note the other input to IC24b will be at logic “0” if the input voltage is below the SP4 level. Both inputs of AND gate IC21a are at logic “1”, hence the output of IC21a goes to logic “1”, after the timer (R99-C3) times out at 0.7CR, the second input of IC18b goes to logic “1” and the output of IC18b goes to logic “0” if the output of IC23 is still at logic “1”. IC18b feeds NOR gate IC22c via inverter IC19d. As any logic “1” on the input of a NOR gate produces a logic “0” on its output, Tr2 is switched “OFF” hence de-energising RL2. Stage 2 is then disconnected from the voltage follower output. For a decreasing input signal: The output of IC23 goes to 0V or logic “0”. The output of IC21a goes to logic “0” and discharges timer (R99-C3). After 0.3CR Tr2 is enabled via IC22c. If the input signal is greater than SP2 then both inputs of IC22c are at logic “0” hence the output will be at logic “1”. Tr2 will then be switched “ON” energising RL2 and connecting Stage 2 to the voltage follower output. If the input signal is above SP2 then the inputs of IC21b are at logic “1” then the output will be at logic “1”, after the timer (R100-C4) times out at 0.7CR, the output of IC22a will be at logic “0”. If IC23 is still at logic “0”, then the output of IC24a will go to logic “1”, thus driving the output of IC24b to 0V. Tr3 will then be switched “OFF” and RL3 de-energised, disconnecting Stage 3 from the voltage follower output. In the event of a voltage surge where the input rises above SP3 and the output of IC25 is at 0V then timer (R105-C6) will enable RL4. Timer (R99-C3) disables in this case. Figure 30 gives logic and relay connection details. Switching of the remaining stages is a direct copy of Stage 3 except for the final stage where it is possible to over-run the 1V output without switching out the stage.

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Component Details: MC14082BCP MC14011BCP BC109 CMOS CMOS Ic max, 100mA Dual 4 Input AND Quad 2 Input NAND hfe, 200-800 Supply 3V to 18V Supply 3V to 18V Vceo, 20V. Ft = 300MHz MC14001BCP MC14049BCP (CMOS) DIL Reed Relay SPNO CMOS Hex Inverting Buffer Contact Rating 0.5A, 100V

Quad 2 Input NOR Supply 3V to 18V Coil 500Ω, 5V (3.7V-10V). Supply 3V to 18V Operating Time 0.5mS Integral Diode LED Red LED Green Vf = 3V Vf = 3V

If = 10mA If = 20mA If max = 25mA If max = 25mA

Note: If a relay with an integral diode is used diodes D1 to D8 need not

be fitted. To avoid loading input and set point potentiometers let comparitor input

resistors be 100KΩ. Timing Circuit: The timer must delay the operation of the relay to be de-energised to

allow the relay to be energised to operate (operating time 0.5mS). The timer should therefore have a time greater than 0.5mS.

T = 0.7CR. IF C = 0.1µF then R = 5/(0.7*0.1) KΩ = 71.4KΩ

R = 75KΩ. Time to reset timers = CR = 0.1 * 75mS = 0.75mS. This will directly

effect the response time of the circuit. Relay Drive Circuit:

Assume 5V, 500Ω relays are used then the relay operating voltage is 3.7V to 10V. If the LED is the red or green LED specified in the component data then the volt drop across the LED will be 3V, therefore the voltage drop across the relay coil will be 9V. The transistor collector current will be:

Ic = 9/0.5 mA = 18mA. (Green LED, If = 20mA Ifmax = 25mA) For red LED If = 10mA, Ifmax = 25mA. Using BC109 transistor: Hfe = 200* to 800* therefore assume Hfe = 200*.

Ib > 18/200 mA = 0.09mA or 90µA. As the drive voltage from the CMOS gates will be 12V, the base resistor <

12/0.09 KΩ = 133KΩ.

Select the base resistor as 47KΩ. Addition connection details are shown in figure 30.

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Power Requirements: All resistors 0.25W MF as maximum power is less than 0.1W for any of the resistors. +12V Supply estimated 250mA max -12V Supply 11mA max.

As the negative supply power requirement is so small it may be cost effective to use a voltage converter powered from the positive supply. Setting Up Procedure 1) Plot characteristic as shown in figures 24 to 26, note the input

characteristic should be referenced to an input of 0V to 1V. 2) Using a rule determine best fit for the eight set points (note SP1 is

0V), then note set points, offsets, and calculate gain for each stage. 3) Injecting 0% and 100% of the desired input signal set the input pre-

amplifier to produce a 0V to 1V signal at TP1. Inject the input with a voltage equivalent to each set point and adjust set point potentiometers until the appropriate LED is illuminated.

4) With input at 0V, set the desired offset for each stage. Monitor TP2

to TP9 with a voltmeter (preferably a DVM) until the desired value is reached.

5) Inject the input with the equivalent set point values and adjust the

stage gain potentiometers until the desired output is produced at TP2 to TP9. For example inject SP2 value and monitor the output of stage 1, at TP2, note this should be the maximum output voltage. Continue the process until the equivalent of 1V at the pre-amplifier output is injected for stage 8.

6) Inject values around the set point settings (±2mV) and observe the operation of the relays by checking LED illumination, and monitor the output (at IC38) with a DVM to ensure a bump less transfer.

7) Repeat stage offset and gain adjust as necessary.

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Components List

R1, 110KΩ 0.25W MF R2, 110KΩ 0.25W MF R3, 11KΩ 0.25W MF R4, 11KΩ 0.25W MF R5, 56KΩ 0.25W MF R6, 56KΩ 0.25W MF R7, 100KΩ 0.25W MF R8, 100KΩ 0.25W MF R9, 910KΩ 0.25W MF R10, 910KΩ 0.25W MF R11, 20Ω 0.25W MF R12, 200KΩ 0.25W MF R13, 200KΩ 0.25W MF R14, 100KΩ 0.25W MF R15, 100KΩ 0.25W MF R16, 10KΩ 0.25W MF R17, 11KΩ 0.25W MF R18, 100KΩ 0.25W MF R19, 100KΩ 0.25W MF R20, 910KΩ 0.25W MF R21, 910KΩ 0.25W MF

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R22, 20Ω 0.25W MF R23, 200KΩ 0.25W MF R24, 200KΩ 0.25W MF R25, 100KΩ 0.25W MF R26, 100KΩ 0.25W MF R27, 10KΩ 0.25W MF R28, 11KΩ 0.25W MF R29, 100KΩ 0.25W MF R30, 100KΩ 0.25W MF R31, 910KΩ 0.25W MF R32, 910KΩ 0.25W MF R33, 20Ω 0.25W MF R34, 200KΩ 0.25W MF R35, 200KΩ 0.25W MF R36, 100KΩ 0.25W MF R37, 100KΩ 0.25W MF R38, 10KΩ 0.25W MF R39, 11KΩ 0.25W MF R40, 100KΩ 0.25W MF R41, 100KΩ 0.25W MF R42, 910KΩ 0.25W MF R43, 910KΩ 0.25W MF R44, 20Ω 0.25W MF R45, 200KΩ 0.25W MF R46, 200KΩ 0.25W MF R47, 100KΩ 0.25W MF R48, 100KΩ 0.25W MF R49, 10KΩ 0.25W MF R50, 11KΩ 0.25W MF R51, 100KΩ 0.25W MF R52, 100KΩ 0.25W MF R53, 910KΩ 0.25W MF R54, 910KΩ 0.25W MF R55, 20Ω 0.25W MF R56, 200KΩ 0.25W MF R57, 200KΩ 0.25W MF R58, 100KΩ 0.25W MF R59, 100KΩ 0.25W MF R60, 10KΩ 0.25W MF R61, 11KΩ 0.25W MF R62, 100KΩ 0.25W MF R63, 100KΩ 0.25W MF R64, 910KΩ 0.25W MF R65, 910KΩ 0.25W MF R66, 20Ω 0.25W MF R67, 200KΩ 0.25W MF R68, 200KΩ 0.25W MF R69, 100KΩ 0.25W MF R70, 200KΩ 0.25W MF R71, 10KΩ 0.25W MF R72, 11KΩ 0.25W MF R73, 100KΩ 0.25W MF R74, 100KΩ 0.25W MF R75, 910KΩ 0.25W MF R76, 910KΩ 0.25W MF R77, 20Ω 0.25W MF R78, 200KΩ 0.25W MF R79, 200KΩ 0.25W MF R80, 100KΩ 0.25W MF R81, 100KΩ 0.25W MF R82, 10KΩ 0.25W MF R83, 11KΩ 0.25W MF R84, 100KΩ 0.25W MF R85, 100KΩ 0.25W MF R86, 910KΩ 0.25W MF R87, 910KΩ 0.25W MF R88, 20Ω 0.25W MF R89, 200KΩ 0.25W MF R90, 200KΩ 0.25W MF R91, 100KΩ 0.25W MF R92, 100KΩ 0.25W MF R93, 10KΩ 0.25W MF R94, 75KΩ 0.25W MF R95, 75KΩ 0.25W MF R96, 47KΩ 0.25W MF R97, 100KΩ 0.25W MF R98, 100KΩ 0.25W MF R99, 75KΩ 0.25W MF R100, 75KΩ 0.25W MF R101, 47KΩ 0.25W MF R102, 100KΩ 0.25W MF R103, 100KΩ 0.25W MF R104, 75KΩ 0.25W MF R105, 75KΩ 0.25W MF R106, 47KΩ 0.25W MF R107, 100KΩ 0.25W MF R108, 100KΩ 0.25W MF R109, 75KΩ 0.25W MF R110, 75KΩ 0.25W MF R111, 47KΩ 0.25W MF R112, 100KΩ 0.25W MF R113, 100KΩ 0.25W MF R114, 75KΩ 0.25W MF R115, 75KΩ 0.25W MF R116, 47KΩ 0.25W MF R117, 100KΩ 0.25W MF R118, 100KΩ 0.25W MF R119, 75KΩ 0.25W MF R120, 75KΩ 0.25W MF R121, 47KΩ 0.25W MF R122, 100KΩ 0.25W MF R123, 100KΩ 0.25W MF R124, 75KΩ 0.25W MF R125, 75KΩ 0.25W MF R126, 47KΩ 0.25W MF R127, 100KΩ 0.25W MF R128, 100KΩ 0.25W MF R129, 47KΩ 0.25W MF R130, 11KΩ 0.25W MF R131, 11KΩ 0.25W MF R132, 11KΩ 0.25W MF R133, 11KΩ 0.25W MF R134, 11KΩ 0.25W MF R135, 11KΩ 0.25W MF R136, 11KΩ 0.25W MF

Vr1, 2KΩ, 25 turn Cermet Trimmer. Vr2, 1MΩ, 25 turn Cermet Trimmer. Vr3, 2KΩ, 25 turn Cermet Trimmer. Vr4, 1KΩ, 25 turn Cermet Trimmer. Vr5, 2KΩ, 25 turn Cermet Trimmer. Vr6, 1KΩ, 25 turn Cermet Trimmer. Vr7, 2KΩ, 25 turn Cermet Trimmer. Vr8, 1KΩ, 25 turn Cermet Trimmer. Vr9, 2KΩ, 25 turn Cermet Trimmer. Vr10, 1KΩ, 25 turn Cermet Trimmer. Vr11 2KΩ, 25 turn Cermet Trimmer. Vr12, 1KΩ, 25 turn Cermet Trimmer. Vr13, 2KΩ, 25 turn Cermet Trimmer. Vr14, 1KΩ, 25 turn Cermet Trimmer. Vr15, 2KΩ, 25 turn Cermet Trimmer. Vr16, 1KΩ, 25 turn Cermet Trimmer. Vr17, 2KΩ, 25 turn Cermet Trimmer. Vr18, 1KΩ, 25 turn Cermet Trimmer. Vr19, 1KΩ, 25 turn Cermet Trimmer. Vr20, 1KΩ, 25 turn Cermet Trimmer. Vr21, 1KΩ, 25 turn Cermet Trimmer. Vr22, 1KΩ, 25 turn Cermet Trimmer. Vr23, 1KΩ, 25 turn Cermet Trimmer. Vr24, 1KΩ, 25 turn Cermet Trimmer.

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C1 to C14, 0.1µF polyester miniature case, tol ± 5%. Tr1 to Tr8, BC109. LED1 to LED8, Red LED, Vf = 3V, If = 10mA, Ifmax = 25mA. IC1 to IC17, CA3140 IC18, MC14011BCP IC19, MC14049BCP IC20, CA3140 IC21, MC14081BCP IC22, MC14001BCP IC23, CA3140 IC24, MC14001BCP IC25, CA3140 IC26, MC14081BCP IC27, MC14049BCP IC28, MC14001BCP IC29, MC14011BCP IC30, CA3140 IC31, CA3140 IC32, MC14081BCP IC33, MC14001BCP IC34, CA3140 IC35, MC14001BCP IC36, MC14049BCP IC37, CA3140 IC38, CA3140 Note D1 to D8 are integral to the relay package.

RL1 to RL8, SPNO, DIL Reed Relays, 5V, 500Ω Coil. 18, 8 way DIL Turned Pin Sockets 22, 14 way DIL Turned Pin Sockets 3, 16 way DIL Turned Pin Sockets TP1 to TP9, PCB terminal posts

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15) Scanner Produce a 32 channel scanner to feed a digital volt meter for a signal range of 0V to 1.999V. The scanner should have a variable sample time of 2 to 10 seconds and the channel number should be displayed on two 7 segment displays. The scanner should also have a hold and a fast scan facility for quick channel selection. Component Data: MC14011BCP DG508AC CMOS 8 Channel Multiplexer with 3 bit Decoder

Dual 4 Input NAND Input Range ±15V Supply 3V to 18V Supply ±15V MC14001BCP MC14049BCP (CMOS) MC14029B (CMOS) CMOS Hex Inverting Buffer Binary/Decade Up/Down

Quad 2 Input NOR Supply 3V to 18V Counter. Pt = 500mW Supply 3V to 18V Supply 3V to 18V MC14020B (CMOS) MC14511BCP (CMOS) 7 Segment LED Display

14 bit Binary Counter BCD to 7-segment Colour Green Supply 3V to 18V Latch/Driver Size 0.3 in

Supply 3V to 18V Common Cathode Vf = 2V at If = 10mA

The Multiplex Stage: The DG508 is a eight channel multiplexer with a 3 bit decoder on pins 1, 16 and 15, and enable on pin 2 (see figure 31). Generating the following code enables the eight switches:

Channel Number A0 A1 A2 1 0 0 0

2 1 0 0 3 0 1 0

4 1 1 0 5 0 0 1

6 1 0 1

7 0 1 1 8 1 1 1

The code can be generated using a binary counter integrated circuit driven

by an oscillator to produce a clock pulse. The scan can be stopped at any time by disabling the clock pulse and fast-forwarded by increasing the clock frequency.

Let the counter be a MC14020 14 bit binary counter. The counter is

designed with an input wave shaping circuit and 14 stages of ripple-carry binary counter. The count is advanced by the negative going edge of the clock pulse.

A simple square wave oscillator can be constructed using two CMOS

inverting buffers or gates configured as inverting buffers. The Oscillator Design:

The counter uses Q7 to Q11 to enable the DG508 multiplexers, and Q6 to provide a clock pulse via inverter IC7e to the display. As outputs Q1 to Q5 are unused output Q6 becomes the timing pulse, the frequency of the oscillator is therefore 64 times greater than the clock or timing pulse (see Figs 31 and 32).

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Time Period T = 0.7CR For a scan period of 2 seconds T = 2/64 s = 31.25ms.

If C2 = 0.47µF then 31.25 = 0.7*0.47*R3 and R3 = 31.25/0.7*0.47 KΩ

R3 = 94.98KΩ preferred value 100KΩ

To increase the scan period to a maximum of say 12s Vr1 must be 5*R3 = 500KΩ Let the fast scan be approximately 0.5s. Then the parallel combination of R2 and

R3 should be R3/4 or 25KΩ. 25K = R2*R3/R2+R3 = 100K*R2/100K+R2, therefore 25K*100K + 25K*R2 = 100K*R2

R2 = 25K*100K/75K = 33.3KΩ preferred value 33KΩ NAND gate IC8c and NOR gate IC6d are configured as inverting buffers forming the oscillator. The output of NAND gate IC8d will be held at logic “1” if the hold switch Sw1 is closed, and will only go to logic “0” if Sw1 is open, note the counter only triggers on a negative going pulse ie from logic “1” to logic “0”.

Let R4 = 100KΩ. The truth table for timing the four eight channel multiplexers is shown below:

Ch No’s Q7 Q8 Q9 Q10 Q11 Q12 Mux Enable

1 0 0 0 0 0 0

2 1 0 0 0 0 0 3 0 1 0 0 0 0

4 1 1 0 0 0 0 5 0 0 1 0 0 0

6 1 0 1 0 0 0 7 0 1 1 0 0 0

8 1 1 1 0 0 0

Q10 = 0 Q11 = 0 Use NOR Gate for logic“1” to Enable Mux

9 0 0 0 1 0 0 10 1 0 0 1 0 0

11 0 1 0 1 0 0 12 1 1 0 1 0 0

13 0 0 1 1 0 0 14 1 0 1 1 0 0

15 0 1 1 1 0 0

16 1 1 1 1 0 0

Q10 = 1 Q11 = 0 Use Inverter to feed Q10 to NOR Gate, and feed Q11 to NOR Gate. When NOR Gate output is Logic “1” the Mux is enabled.

17 0 0 0 0 1 0

18 1 0 0 0 1 0 19 0 1 0 0 1 0

20 1 1 0 0 1 0 21 0 0 1 0 1 0

22 1 0 1 0 1 0

23 0 1 1 0 1 0 24 1 1 1 0 1 0

Q10 = 0 Q11 = 1 Use Inverter to feed Q11 to NOR Gate, and feed Q10 to NOR Gate. When NOR Gate output is Logic “1” the Mux is enabled.

25 0 0 0 1 1 0 26 1 0 0 1 1 0

27 0 1 0 1 1 0 28 1 1 0 1 1 0

29 0 0 1 1 1 0 30 1 0 1 1 1 0

31 0 1 1 1 1 0

32 1 1 1 1 1 0 Reset 1

Q10 = 1 Q11 = 1 Feed Q10 and Q11 to NAND Gate then invert output to enable the Mux.

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Q12 resets the MC14020 counter IC5 via IC7d and IC8b. This will also reset the display counters IC9 and IC11. As NAND gate IC8b will give a logic “1” output if either or both inputs are at logic “0” timer R1/C1 will provide a reset pulse on “Switch ON”. The reset pulse duration T can be calculated as follows:

T = 0.7C1*R1

The minimum reset pulse width for IC5 (4020) is 320ms and minimum setup time for IC9 and IC11 (4029) varies between 320ns and 340ns. T must therefore be greater than 340ns.

If T = 400ns and R1 = 100KΩ C1 = T/0.7R1 = 400/0.07 pF = 5710pF or 0.0057µF If the scanner is supplied from a battery pack where the supply is already

established at switch on then let R1 = 100KΩ and C1 = 0.1µF, but if a mains power supply is used T should be greater than 10ms.

If T = 10ms then C1 = 10/0.7*100 µF = 0.143µF.

Let R1 = 100KΩ and C1 = 2.2µF 16V wkg. Display Stage Design:

The tens and units display stages are almost identical, the only significant difference being that the units counter presets to logic “1” and the tens counter presets to logic “0”.

The supply voltage Vs is selected at 12V (supply voltage range for CMOS, 3V to 18V) therefore the input pulse at pins 5 and 15 of the binary/decade counter IC9 will be 0.7Vs to Vs. The binary output of IC9 feeds the display driver IC10 which provides a nominal 12V feed to the 7 segment common cathode display Disp1. The decade output (pin 7 of IC9), feeds the input of the tens display counter The reset pulse, (Logic “1”) resets the multiplex counter, (IC5) and the display counters, (IC9 and IC11). This serves to synchronize the counters.

Each segment of Disp1 and Disp2 have Vf = 2V and If = 10mA therefore to limit If to 10mA a series resistor must be included in each segment feed.

R (R5 to R18) = (12 – 2)/10 KΩ = 1KΩ. Power Requirements:

The 4, DG508 require a dual supply, power dissipation is unlikely to be greater than 2W,say 1W per supply. + 12V Supply Quantity Device Maximum Power Dissipation 4 DG508 1W 1 MC14020B 0.5W 2 MC14029B 1W 2 MC14511B 1W 3 Gate Packages 0.2W

2 Displays + Series Resistors 1.44W Total 5.14W (12V, 428mA)

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Note the maximum number of segments used are 7 for the units display and 5 for the tens display. This equates to a load of 12 times 10mA, ie 120mA or 1.44W. If a voltage converter is used to provide the –12V supply then a 12V, 0.5A power supply will be required. The resistors with the greatest power dissipation will be the series resistors used to limit the display segment current. P = VI = 10*0.01 W = 0.1W, therefore let all resistors be 0.25W. Components List

R1, 100KΩ 0.25W MF R2, 33KΩ 0.25W MF R3, 100KΩ 0.25W MF R4, 100KΩ 0.25W MF R5, 1KΩ 0.25W MF R6, 1KΩ 0.25W MF R7, 1KΩ 0.25W MF R8, 1KΩ 0.25W MF R9, 1KΩ 0.25W MF R10, 1KΩ 0.25W MF R11, 1KΩ 0.25W MF R12, 1KΩ 0.25W MF R13, 1KΩ 0.25W MF R14, 1KΩ 0.25W MF R15, 1KΩ 0.25W MF R16, 1KΩ 0.25W MF R17, 1KΩ 0.25W MF R18, 1KΩ 0.25W MF

Vr1, 500KΩ Lin potentiometer.

C1, 2.2µF, 16V wkg, solid tantalum capacitor C2, 0.47µF polyester

IC1, DG508AC IC2, DG508AC IC3, DG508AC IC4, DG508AC IC5, MC14020B IC6, MC14001BCP IC7, MC14049BCP IC8, MC14011BCP IC9, MC14029B IC10, MC14511BCP IC11, MC14029B IC12, MC14511BCP Disp1 and Disp2, 7 Segment LED Display, Common Cathode 0.3” (Vf = 2V, If = 10mA) PB1, NO push button switch Sw1, SPDT switch or latching push button switch 4, 14 way DIL turned pin sockets 10, 16 way DIL turned pin sockets Note: 4mm terminal posts can be used to connect the DPM.

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16) Dice Produce an electronic (dice numbers 1 to 6) using LED’s to mimic the face of the dice. The throw should be simulated by the operation of a push button switch and the value totally random ie the dice should not be biased. The dice should be battery powered so power consumption should be reduced to a minimum. Component Data: 4017B 4072B 4049B BC109 CMOS CMOS CMOS Ic max 100mA Counter 4 input OR Inverter hfe 200 to 800 Supply 3v to18v Supply 3v to 18v Supply 3v to 18v Vceo 20v fc 300MHz LED Red Vf = 2.2v If = 10mA Assume that six states, (ie a score of 1 to 6) are generated by a counter driven by an oscillator. The dice face must contain all options from 1 to 6 requiring seven LED’s (see dice circuit diagram). The table below shows the LED’s illuminated for each score: For the scores to be represented on the dice face the following counter outputs must illuminate LED’s as shown in the following table:

The counter outputs O0 to O5 relate to scores 1 to 6. O6 resets the counter. By inspection of the previous table no more than four inputs are required to operate any LED. Also any input must operate the appropriate LED (this is an OR function). LED1 and LED5 require the same set of conditions, similarly LED3 and LED7. LED2 and LED6 only require the counter output O5.

Score LED’s Illuminated 1 4

2 3 + 7 3 1 + 4 + 5

4 1 + 3 + 7 + 5

5 1 + 3 + 7 + 5 + 4 6 1 + 2 + 3 + 5 + 6 + 7

LED O0 O1 O2 O3 O4 O5

1 * * * * 2 *

3 * * * * 4 * * *

5 * * * * 6 *

7 * * * *

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Three 4 input OR gates are required to provide the appropriate outputs to the LED’s. As the minimum current requirement for the LED’s is 10mA a transistor is required as a buffer. Let Tr1 to Tr4 be BC109 with Gain hfe of 200x. Calculating base resistors ( R3, R5, R7, R9 ): If Ic = 10mA then Ib > 10/200 mA The voltage across Rb = 9v – 0.6v = 8.4v Thus Rb < 8.4 x 200/10 K ohms. Let Rb = 20K ohms. Calculating R4: With Tr1 saturated LED4 Vf = 2.2v therefore voltage across R4 = 9v – 2.2v. As Ic = 10mA R4 = (9 –2.2)/10 K ohms. R4 = 680 ohms. Power Dissipation = 6.8 x 10 mW = 68 mW. Let R4 = 680 ohm 0.25W . Calculating R6, R8 and R10: As Vf = 2.2v, voltage across collector resistor Rc = 9v – 4.4v = 4.6v Therefore Rc = 4.6/10 K ohms = 460 ohms Let R6, R8, and R10 = 470 ohms 0.25W. The counter must be reset under two conditions, when the power is switched ON via Sw1 and when the maximum count is achieved ie score 6. The remaining OR gate is used to feed the reset signals to the counter reset pin 15. At switch on, R2 charges C3. At voltage across C3 = 0.7 x 9v the input to inverting buffer IC1d is at logic ‘1’, and the counter is enabled. T = 0.7 x C2 x R2 Let C2 = 22µF and R2 = 100K ohm then T = 0.7 x 22 x 10-6 x 100 x 103 s T = 154ms. If C2 is a Tantalum capacitor the leakage current may become significant. For logic “ 1” to be achieved at the input to IC1d: R2 x Il must be significantly less than 0.3 x 9v ie 2.7v. Tantalum Leakage Current = 0.02 x µF x V µA or 1µA whichever is larger. Il = 0.02 x 22 x 9 = 3.96µA R2 x Il = 100 x 3.96 mV = 0.396v The Oscillator Design:

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To prevent anticipation of the score the oscillator frequency should be set above 20Hz. The oscillator is formed by R1,C1 and IC1 “a” and “b” sections. The output is buffered by IC1c. Pulse Width = 0.7CR (for CMOS) therefore Frequency f = 1/(1.4CR) Let R1 = 100 K ohms then C1 = 1/(1.4 x 20 x 100 x 103) = 0.357µF For f > 20Hz Let C1 = 0.33µF. Sw2 interrupts the oscillator output to the counter input hence stopping the count. The counter input would then be open circuit and possibly susceptible to noise. Resistor R11 connects the counter input to 0v providing logic “0” to the counter input when the oscillator is disconnected. Let R11 = 20K ohms. To save power consumption Sw2 only energizes the LED’s when Sw2 is depressed and a score is required. Sw2 can be either a SPDT double break push button switch or a biased DPDT switch. Power Consumption: The load current of the dice circuit should be in the region of 2mA until Sw2 is depressed when maximum consumption should increase to approximately 34mA (at any one time a maximum of three transistors can be switched “ON”).

Fig. 33

Page 180: Electronics Made Easy

Component List R1, 100K ohm 0.25w Metal Film R2, 100K ohm 0.25w Metal Film R3, 20K ohm 0.25w Metal Film R4, 680 ohm 0.25w Metal Film R5, 20K ohm 0.25w Metal Film R6, 470 ohm 0.25w Metal Film R7, 20K ohm 0.25w Metal Film R8, 470 ohm 0.25w Metal Film R9, 20K ohm 0.25w Metal Film R10,470 ohm 0.25w Metal Film R11,20K ohm 0.25w Metal Film C1, 0.33µF Polyester C2, 22µF Tantalum 16v Tr1 to Tr4, BC109 IC1, 4049B IC2, 4017B IC3 and IC4, 4072B LED1 to LED7, Red LED Vf = 2.2v, If = 10mA Sw1, Single Pole Switch Sw2, SPDT double break push button. Note: A biased DPDT switch can also be used for Sw2. Turned Pin DIL sockets as required 9v PP3 battery and connector.

Page 181: Electronics Made Easy

17) Pulse Multiplier Produce a pulse multiplier to provide exact multiples from 1x to 9x of an input pulse. The input pulse could be either positive or negative going at amplitude 100mV to 10V at frequencies up to 1KHz. Component Data: 4046B 4081B 4018B BC109 CMOS CMOS CMOS Ic max 100mA PLL Quad 2input AND Divide by n counter hfe 200 to 800 Supply 3v to 18v Supply 3v to 18v Supply 3v to 18v Vceo 20v fc 300MHz CA3140 LED Red Supply Voltage, +4V to +36V or ±2V to ±18V Vf = 2.2v Max Diff Input Voltage, ±8V If = 10mA Slew Rate, 9V/µs

The CMOS circuitry requires a positive pulse at an amplitude greater than 0.7x the supply voltage assuming a ±12V supply is used the pulse amplitude into the PLL (IC4) must be greater than 8.4v. This necessitates an inverter option at the input and an amplifier stage for low signal levels. If the input signal has noise present it may be necessary to select the trigger point on the waveform and provide a true square wave output. The amplitude of the output when passed through a comparitor will be approximately 2v below supply voltage. Inverter Design: G = Rf/Rin where Rin = Rs + Ri, assuming Rs << Ri let Rin = Ri As minimum gain is required: If G = 1 then R1 = R2. R3 = R1 x R2/(R1+R2) Let R1 = 20K ohm then R2 = 20K ohm and R3 = 10K ohm. As IC1 is configured as an inverting amplifier where the input can be negative wrt ground it must be fed with a dual power supply. The Amplifier Stage: The amplifier stage is fed via input polarity switch Sw1 which either feeds the signal from the input or via the inverter. For non inverting amplifier: G = (Rf + R5)/R5 and R5 = R4 + Rs As Rs (the output impedance of the previous stage) is small wrt R4 let R5 = R4. Let R5 = 20K ohm then R4 = 20K ohms. Rf is selected for a gain of 1x or 5x by Sw2. For G = 5, Rf = 4 x R5 = 80K ohm. For G = 1, Rf = 0 ohms. Let R6 = 82K ohms.

Page 182: Electronics Made Easy

Pins 4 and 7 of IC2 are connected to 0v and +12v respectively giving a maximum output between 0v and 10v (2v below supply). The Comparitor Stage: The conditioned pulse is then fed into the positive input of IC3. When the voltage at pin 3 is greater than the set voltage at pin 2 the output at pin 6 will be above zero. In practice the comparitor will have gain equivalent to the open loop gain of the op amp. Pins 4 and 7 of IC3 are connected to 0v and +12v respectively giving a square wave output between 0v and 10v (2v below supply). The voltage divider R8, Vr1 and R7 sets the trigger level of the comparitor. If the minimum input level is 100mV then the amplifier output will either be 0 to 500mV or 0 to 100mV. The maximum signal level the maximum level will be 0v to 10v. Vr1 must range between 200mV and say 9.5v. The voltage across R8 will be 2.5v and the voltage across R7 will be 200mV. If Vr1 = 1K ohms then the current in the divider chain will be (9.5v – 0.2v)/1 mA. Calculating Values of R7 and R8: R8 = 2.5/9.3 K ohms = 268.8 ohms Let R8 = 270 ohms R7 = 0.2/9.3 K ohms = 21.5 ohms Let R7 = 22 ohms Let Vr1 = 1K ohm Resistors R9 and R10 could be any value between 0 ohms and 100K ohms. Let R9 and R10 = 20K ohms. Pin 6 of IC3 feeds the PLL chip IC4 and the trigger indicator. LED1 has Vf = 2.2v and If = 10mA. When the transistor is saturated: Voltage across R12 = 12v – 2.2v = 9.8v R12 = 9.8/10 K ohms = 980 ohms. Let R12 = 1K ohms Then Ic = 9.8/1 mA = 9.8mA As hfe > 200 then R11 < (10 –Vbe) x 200/9.8 = 198K ohms Maximum output current of IC3 = 10mA therefore R11 should be between 1K ohm and 198K ohm. Let R11 = 20K ohm Phase Locked Loop Design: The Phase Locked Loop (IC4) has the feedback path interrupted by a divide function of 1 to 9. This produces an output of 1x to 9x the input frequency whilst maintaining the phase relationship to the input pulse. R13 and C1 select the frequency range and minimum frequency of the 4046 PLL.

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From Data Sheet: Let R13 = 22K ohms and C1 = 0.01µF Components R14, R15, and C2 form a low pass filter. R15 provides an offset to the frequency range. The filter effects the response time of the PLL. Let R14 = 470K ohms, R15 = 75K ohms and C2 = 0.47µF The pulse input is fed into pin 14 of IC4. The output, pin 4 feeds the output socket Sk2 and the input to the divider IC5 (4018B, ÷n). With thumbwheel switch Sw3 selected to1x, pin 3 of IC4 is connected to the input, pin 14. For other multiples pin 3 is fed via the divider stage. Pin 1, data input and pin15, reset on IC5 are connected to 0v. The Divide Function: The divide by n counter has outputs, ÷2, ÷4, ÷6, ÷8 and ÷10. The remaining outputs must be generated using AND gates. The following table gives the connection details.

The outputs of IC5 and IC6 are then fed to the appropriate switch segments of Sw3. The slider or common of Sw3 then feeds to pin 3 of IC4 and pin1 (data input) of IC5. In my experience, when the 4046B phase locked loop has been in continual use for in excess of one year or the equivalent casual use for a longer period of time it has been known to become unstable. Power Requirements: R12 has the highest power consumption P = 12v x 10mA = 120mW. Let all resistors be 0.25W. Power Supply dual 12v supply +12V at 42mA max -12V at 10mA max

Counter IC5 ÷ n Outputs

Pin No’s

2 0 5

4 1 4 6 2 6

8 3 11 10 4 13

÷ n Pin No’s AND Gates

3 p4, p5 IC6b

5 p4, p6 IC6d 7 p6, p11 IC6c

9 p11, p13 IC6a

Page 184: Electronics Made Easy

Component List R1, 20K ohm 0.25w Metal Film R2, 20K ohm 0.25w Metal Film R3, 10K ohm 0.25w Metal Film R4, 20K ohm 0.25w Metal Film R5, 20K ohm 0.25w Metal Film R6, 82K ohm 0.25w Metal Film R7, 22 ohm 0.25w Metal Film R8, 270 ohm 0.25w Metal Film R9, 20K ohm 0.25w Metal Film R10, 20K ohm 0.25w Metal Film R11, 20K ohm 0.25w Metal Film R12, 1K ohm 0.25w Metal Film R13, 22K ohm 0.25w Metal Film R14, 470K ohm 0.25w Metal Film R15, 75K ohm 0.25w Metal Film Vr1, 1K ohm potentiometer C1, 0.01µF Polyester C2, 0.47µF Polyester Tr1, BC109 IC1 to IC3, CA3140 IC4, 4046B IC5, 4018B IC6, 4081B LED1, Red LED Vf = 2.2v, If = 10mA Sw1 and Sw2, SPDT Sw3, Thumbwheel Decade Switch Sk1 and Sk2, 50 ohm BNC sockets Turned Pin DIL sockets as required.

Fig. 34 Pulse Multiplier