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EmbeddedSystems Design

••• Portfolio of FP7 projectsDir. G: Components and Systems

Unit G3: Embedded Systems and Control

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LEGAL NOTICE

By the Commission of the European Union, Information Society & Media Directorate-General, Soft-

ware & Service Architectures and Infrastructures Unit.

Neither the European Commission nor any person acting on its behalf is responsible for the use which

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publication.

The views expressed in this publication are those of the authors and do not necessarily refl ect the

offi cial European Commission’s view on the subject.

More information on the European Union is available on the Internet (http://europa.eu).

Cataloguing data can be found at the end of this publication.

Luxembourg: Publications Offi ce of the European Union, 2010

ISBN 978-92-79-16409-5

doi:10.2759/35125

© European Union, 2010

Reproduction is authorised provided the source is acknowledged.

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••• Portfolio of FP7 projectsDir. G: Components and Systems

Unit G3: Embedded Systems and Control

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Table of contents

ACTORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

ADAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

ALL-TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

ARCADIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

ArtistDesign. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

COCONUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

COMBEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

COMPLEX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

COSINE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

DESTECS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

EMBOCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

ENOSYS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

ERA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

GALAXY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

INTERESTED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

MADES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

MADNESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

MEDEIA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

MNEMEE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

MOBY-DIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

MOGENTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49


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MULTICUBE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

PREDATOR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

PROARTIS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

ProSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Quasimodo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

SATURN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

TERESA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63


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Embedded Systems Design

This brochure contains an overview of our projects

STREPs- Specific Targeted Research Projects: ACTORS ALL-TIMES COCONUT COMBEST COMPLEX DESTECS EMBOCON ENOSYS ERA GALAXY MADES MADNESS MEDEIA MNEMEE MOBY-DIC MOGENTES MULTICUBE PREDATOR PROARTIS Quasimodo SATURN TERESA IPs- Integrated Projects: COMPLEX INTERESTED

CSA- Coordination and Support Action: ADAMS ARCADIA COSINE2 ProSE NoE- Network of Excellence: ArtistDesign

For further information: European Commission - Information Society and Media DG Directorate G – Components and Systems Unit G3 – Embedded Systems and Control Office: BU31 05/03 B-1049 Brussels Email: [email protected] Tel: +32 2 296 64 07 Fax: +32 2 296 83 89 http://europa.eu/information_society

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At A Glance: ACTORS

Adaptivity and Control of Resources in Embedded Systems

Project Coordinator/ Technical Manager: Name: Johan Eker Institution: Ericsson AB Email: [email protected]

Project website: www.actors-project.eu

Partners:Ericsson AB (Sweden) Scuola Superiore Sant’ Anna (Italy) Technische Universität Kaiserslautern (Germany) Evidence S.r.l. (Italy) Ecole Polytechnique Fédérale de Lausanne (Switzerland) Lund University (Sweden) AKAtech SA.

Duration: 36 months Start: 2008.02.01 Total Cost: 3412454 € EC Contribution: 2479214€

Contract Number: INFSO-ICT- 216586

ACTORSAdaptivity and Control of Resources in Embedded Systems KEYWORDS: Adaptivity, Resource Management, Reservation based scheduling, MPEG, Data flow modeling, Code generation, FPGA

Main Objectives

ACTORS addresses the challenging problem of efficient design of embedded systems for complex and demanding high-performance applications. The project approach is to raise the abstraction level of the project approach is to raise the abstraction level of the specifications and computing models, to include resource-constrained design exploration stages and real- time resource adaptation by developing the appropriate models and tools supporting the design from the specification down to the embedded implementation. Three main innovative technologies will be employed: high level dataflow specification and programming models for design space exploration, virtualization and feedback-based resource scheduling. The targeted execution platforms are Linux-based multiprocessor/multicore systems and FPGAs. Three design cases will be developed to validate and demonstrate the new approach: multimedia processing on cellular phone terminals, embedded control, and high-performance video systems.

Key Issues

The project is based on a set of main observations and ideas: � Embedded systems are vital to Europe's industry

and society. In parallel with miniaturization and the necessity to handle severely resource-constrained implementation platforms, the functionality and complexity of large classes of embedded systems continue to increase making them from many respects comparable to ordinary desktop PCs. A mixture of different types of timing, application driven QoS constraints and the migration to the new generation of multi-core and SoC platforms make overall system architecture design, resource allocation and scheduling more important and challenging topics than ever before.

The ACTORS consortium is led by Ericsson. It contains two SMEs (AKAtech and Evidence) and four university beneficiaries (SSSA, TUKL, ULUND, and EPFL). Associated partner to the project is Xilinx, US.

ACTORS focus on design of adaptive and efficient real-time applications

for multicore hardware using

data flow tools and methodologies.

RESEARCH PROJECTS Embedded Systems Design

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COOPERATIONEuropean Commission

Information Society and Media

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� While the success of Si CMOS scaling has been the main driving force for performance progress of embedded systems in the last 30 years, it has at the same time practically restricted the way system specification SW development, HW design and all related tools and formalisms have evolved so far. No common formalism, language or design methodology is available to map concurrency and parallelism for embedded SW and HW from the specification level down through all the different levels of abstractions to final system design/implementation. A radical change in necessary in order to master the complexity of future generations of embedded systems and to utilize the possibilities of new multicore platforms. Parallelism and resource allocation must be included in the design flow from the very beginning. A unified approach is required that combines ideas from computer science, control systems, and electronic engineering.

� Execution efficiency as well development efficiency requires abstractions on a higher level than what is provided with C and threads/priorities. For a large class of embedded system applications including feedback control, signal processing and multimedia streaming and processing, dataflow models and dataflow languages, in particular actor languages have superior properties. Actors provides the proper foundation for implementation of efficient, component based, parallel and adaptive algorithms for both media applications in embedded consumer electronics and embedded control and signal processing applications.

� Virtualization techniques such as reservation-based scheduling is a very good way of providing temporal and spatial isolation between different functions and, hence improve dependability, predictability, composability, security and development productivity for embedded systems. Important research advances have been made in the area, which ACTORS will build upon, but much remains before this becomes industrial practice.

� Adaptivity to changes and uncertainties in resource requirements, objectives, external conditions and use cases is a necessity in large classes of embedded systems. This requires a unification of approaches from computer science and control. Adaptivity and virtualization is a natural match. Control techniques can be used globally to dynamically adapt the reservation budgets to changes, as well as locally, within each reservation to adjust the resource requirements.

Technical Approach

The project consists of three fundamental components: � Data-flow programming using actors o Actor programming is suitable for

applications that perform sequential operations on data (signal processing, control, media processing, etc), i.e. operate on streams.

o Actors are implemented using the CAL Actor Language and the OpenDF compilation and simulation framework. CAL is part of coming MPEG RVC standard.

o Actors provide a programming model that is well suited for building components that are parametric in resource requirements �enable adaptivity

o The design of the CAL Actor Language allows for generation of efficient code.

o Actors is the fundamental user level component

� Feedback based resource management o Distribute resources based on execution

conditions and application requirements o Will allow for dynamic, yet predictable,

system behavior o Based on control theory

� Reservation based scheduling o Provide a logical abstraction layer for

distribution of system resources o Fundamental mechanism for distributing

resources among applications o Extend and improve current implementation

available in the main line Linux kernel

Expected Impact

The project will show how to build flexible and efficient system using dataflow technologies. The resulting systems will be robust due to the underlying feedback based resource management. Project members work closely with the MPEG standardization body on tools and methodologies for data flow programming. The work on scheduling will be done with the explicit goal of acceptance of the open source community. All developed software will, as far as possible, be made available as free open source, and this includes compilers and runtimes for the CAL actor language. Our intention is to through a set of powerful use cases and a working, free tool-chain demonstrate the superiority of our approach. CPU reservation #1 CPU reservation #2

CPU reservation #3

Resource Manager

RBS Kernel

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At A Glance: ADAMS

Action for the Dissemination and Adoption of the MARTE and related Standards for

component based middleware

Project Coordinator: Name: Dr. Sébastien Gérard Institution: CEA LIST Email: [email protected]

Project website: www.adams-project.org

Partners:Commissariat à l’Energie Atomique (France) THALES Group (France) Universidad de Cantabria (Spain) Volvo Technology Corporation (Sweden)

Duration: 24 months Start: 2008-05-01Total Cost: € 300000 EC Contribution: € 300000

Contract Number: Grant agreement n°224330

ADAMSAction for the Dissemination and Adoption of the MARTE and related Standards for component based middleware The ADAMS project aims at promoting the usage of the MARTE standard for the development of real-time and embedded systems using both model and component design paradigms.

KEYWORDS: UML, MARTE, MDE/MDD, real-time and embedded applications, component-based design.

Main Objectives

The recent adoption of the UML MARTE standard is a great success issued from an intensive work launched four years ago by THALES, CEA LIST and INRIA and supported by a large international and representative consortium including important tool editors (ARTISAN, IBM/Rational/ Telelogic/I-Logix, MathWorks, Mentor Graphics…), users (Alcatel-Lucent, France Telecom, Loocked-Martin, THALES…) and academics (CEA LIST, INRIA, SEI/Carnegie Mellon Univ., Univ. Cantabria, Univ. Carleton…).

These activities are by essence strongly linked to the modelling approaches, in particular regarding architecture descriptions and non-functional requirements. The two domains automotive and avionics have developed their own specification and execution platform standards (AADL, ARINC, AUTOSAR, EAST-ADL2, OSEK…) and are looking to integrate some other related approaches such as LwCCM or UML/SysML profiles with particular interests on non-functional property descriptions (this covers, namely, resource, timing, and safety requirements). Interfaces to these standards have already been proposed and defined in MARTE. However, the knowledge of MARTE in the embedded community, both on industry and on academia side, is not sufficient to ensure a good level of understanding of its capacities and its use. The objective of ADAMS is thus to trigger the knowledge dissemination by exploiting MARTE in industrial practice amongst others by restructuring or refining MARTE methods and tools based on feedback from practice.

In parallel we observe an intense activity in embedded domains, in particular for automotive and avionics, to standardise and deploy component-based middleware technologies.

ADAMS will focus on promoting the usage of the OMG’s MARTE standard for MDD in both avionics and

automotive domains.

COORDINATION AND SUPPORT ACTIONEmbedded Systems Design

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WP2 - MARTE and automotive domain

WP3 - MARTE and avionics domain

EAST-ADL2 AUTOSAR (OSEK)

Continental Corporation Support for extern analysis

Non Functional Properties

Point of view Architecture description Point of view

Execution infrastructure Point of view

Airbus

SAE-AADL IMA, ARINC

MARTE

Support for extern analysis

Key Issues

MARTE has been a great success resulting mainly from a European initiative. The challenge now is to disseminate and promote its adoption through the European industry and trigger enhancements reflecting the practitioners’ needs. This is valuable for Europe due to its very strong economic activity in development of embedded, real time and distributed systems. Key point for its adoption is to demonstrate and convince about its conformance, usability and efficiency to deal with current middleware technologies used by the embedded system industry, and adapt it as necessary to related standards of the automotive and avionics domain (strongly structured, respectively, on AUTOSAR, EAST-ADL2, IMA/ARINC, and SAE-AADL).

Expected Impact

The emergence and dissemination of high quality standards supporting modelling, design and deployment of embedded systems software is a key factor for the emergence of new services as well as cross domain products and solutions. As such, the MARTE OMG standard has the potential to support and standardize future embedded systems design flows and middleware for several application domains, especially automotive and avionics. By being proactive in the dissemination and feedback gathering of MARTE through a series of concrete tasks as indicated above in the work-package description, the ADAMS project will effectively contribute to deliver the value of the MARTE standard.

Technical Approach

Several projects have been and are being launched to enhance, evaluate, and demonstrate the benefits of MARTE and other standards. The analysis of the ADAMS partners is that the current entering point for ensuring successful deployment of the MARTE standard is a focussed effort to disseminate knowledge on MARTE and to coordinate feedback and update proposition on MARTE from the practice. This is why the instrument chosen to push the dissemination of MARTE was “Support Action”. By structuring the ADAMS project around the two target industrial domains, automotive and avionics, the ADAMS project will more specifically commit itself to achieve its objectives. The main objective of ADAMS is to favour the exploitation of the MARTE standard in domains having requirements similar to those that have triggered the standard elaboration process four years ago. Two domains are particularly active to standardize modelling approaches and deploy them on component-based middleware technologies: automotive and avionics. They share a large set of requirements with MARTE and thus are particularly relevant for focused dissemination and critical analysis of the current standard version. In addition, ADAMS will work on promoting MARTE on the one hand to the whole embedded systems community. On the other hand, ADAMS will also use all developed results to influence the related standardisation bodies, in order to close the feedback loop by organizing and delivering the feedback gathered from the automotive and avionics domains in the form of recommendation actions towards both OMG for MARTE evolution and domain initiatives and standards for convergence and evolution towards MARTE. To ensure a pertinent dissemination to both automotive and avionics domains, the specific work performed within ADAMS is organised around two working groups of experts from the corresponding domain. These working groups will deal with the concerns of the three following technical points of view: � The ways to specify non-functional properties.

� The ways to describe application architecture and deployment.

� The ways to specify the execution and communication infrastructure (middleware & OS).

Project organisation for both working groups will be similar as denoted in following picture:

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At A Glance: ALL-TIMES

Integrating European Timing Analysis Technology

Project Coordinator: Name: Björn Lisper Institution: Mälardalen University Email: [email protected]

Project website: www.ICT-ALL-TIMES.eu

Partners:AbsInt Angewandte Informatik GmbH (Germany) Vienna University of Technology (Austria) Gliwa GmbH (Germany) Symtavision GmbH (Germany) Rapita Systems Ltd (UK)

Duration: 27 months Start: 2007-11-01Total Cost: € 2 094 492 EC Contribution: € 1 600 000

Contract Number: INFSO-ICT-215068

ALL-TIMESIntegrating European Timing Analysis Technology The ALL-TIMES aims at interoperability of tools from SMEs and universities, and integrated tool chains using open tool frameworks and interfaces and thus an increase the productivity of embedded systems development projects by 25%

KEYWORDS: timing analysis, WCET, worst case execution time, timing tools, integrated tool chains, scheduling analysis

Main Objectives

The ALL-TIMES project aims at combining and developing research results and timing tools currently available and thus to strengthen the European lead in the timing analysis area. The ALL-TIMES project will enable interoperability of tools from SMEs and universities, and develop integrated tool chains using open tool frameworks and interfaces. By combining research results and commercial tools, ALL-TIMES will ensure the flow of ideas from basic research to practice. The two principal project objectives are:

One of the overall objectives of the project is the provision of new integrated toolsets for timing analysis targeted at the embedded real-time systems market. This relates to the advancement of new analysis techniques for integrated scheduling analysis, WCET analysis and measurement. In particular, the project will deliver new methods for timing analysis at both the system level and the code level in an open framework. Another objective is achieving demonstrable increase of 25% in productivity in the timing domain of embedded systems development by enabling a quick, safe, and automatic efficient mechanism for deriving timing data as opposed to the manual, laborious traditional approach.

Technical Approach

The project will provide a detailed requirements study with the aim at setting the scene for future timing analysis research. A secondary objective is therefore the increase in productivity of embedded systems development by enabling a quick and automatic efficient mechanism for deriving timing data as opposed to the manual, laborious traditional approach.

� Integration of timing analysis tools

� Increase of productivity of embedded systems development projects by 25% of the design time pertaining to timing issues

ALL-TIMES will focus on combining and

developing research results and timing

tools currently available and thus to

strengthen the European lead in the timing analysis area.


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Theme 2: Integration into build process The adoption of a new technology implies change, which demands clear demonstrable benefits in perspective, and may be costly. Thus, new technology may be slow to deploy and integrate into the end-customer process. Academic prototypes are not usable by large companies that require commercial quality tools with long-term support guarantees. A second issue is the large number of evolved procedures and constraints, which can make it difficult to exploit a technology simply because required input data cannot be obtained, or because parameters yielding the biggest improvements cannot be changed. This project will address these issues by targeted pilot studies to demonstrate the added value that investing in timing analysis tools brings to customers. Theme 3: Education, and dissemination of knowledge The number of experts in timing analysis is fragmented over universities and small companies, and their impact to reach a wider audience is limited.The current level of education and knowledge of timing issues of engineers is not sufficient.

Expected Impact

ALL-TIMES will strengthen the competitiveness of several key industries in Europe, most notably the automotive and aerospace areas. Beyond these industries, automation, manufacturing, robotics, medical, communication, and multimedia are markets where timing is important. The ALL-TIMES project will thus� Interface the five different analysis techniques

listed above (three code-level and two system-level techniques) that are represented in the project

� Provide an open (quasi-standard) interface to integrate additional timing analysis techniques and tools, aiming at becoming a de-facto standard.

� Provide solutions for timing analysis/estimation in early design phases as part of design-space exploration and architecture optimization.

The technological objectives relate to the actual implementation of the theories, analysis methods, and tools developed in this project. These will be validated with prototypes and demonstrated with targeted pilot case studies at industrial companies towards the end of the project. A key component is the investigation of methods for the interoperability of tools, to facilitate easier integration into the customer build processes. An important objective of the project is the validation and dissemination of the technology to a wide potential customer base as a mechanism for providing a path to exploitation of the results developed within the project. These dissemination activities will be accompanied by publication of results in form of guidelines for non-expert users on applying timing analysis technologies, as well as other means such as academic conferences and participation in trade shows.

Key Issues

EU industries face a difficult task to improve the reliability, safety, performance and resourceefficiency of systems with regard to timing. Even though EU is leading in research and development, as well as technology transfer, the take up by industry is still low. This project aims at improving the lead of EU in the development and provision of advanced timing analysis techniques. There are several aspects to this problem; we classify them in the following themes: Theme 1: Interoperation, scale and automation There are fundamental research problems that need to be fully addressed to ensure that Europe continues its lead in the technology adoption process. The first one is the interoperation of tools. Furthermore, some of the current analysis techniques have serious scalability issues relating to the size of the programs to be analysed. Finally, a major issue is the full automation of the analysis process.

Timing analysis

Code analysis

Measurement based analysisMeasurement Tracing and

displayingStatic code

analysisStatic scheduling

analysis

System analysis

Figure 1 Relations between different timing analysis techniques

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At A Glance: ARCADIA

Aligning ResearCh AgenDas In ARTEMIS

Project Coordinator: Name: Sergio bandinnelli Institution: ESI-Tecnalia Email: [email protected]

Project Technical Manager: Name: Inaki Eguia Institution: ESI-Tecnalia Email: [email protected]

Project website: www.arcadia-project.eu

Partners:ESI-Tecnalia (Spain) Thales (France) SafeTrans (Germany) NKTH (Hungary) TU Vienna (Austria) UJF Filiale (France) Siemens (Germany) Eutema (Austria) ST-Microelectronics (Italy)

Duration: 24 months Start: 2010.11.01Total Cost: 750.000€ EC Contribution: 750.000€


ARCADIAAligning ResearCh AgenDas In ARTEMIS The ARCADIA project main objective is to have better and effective coordination of the efforts in order to optimize the use of the resources for the Embedded System field to strengthening Europe´s future growth, competitiveness and sustainable development. KEYWORDS: Alignment of Strategic Research Agendas, aligning roadmaps in Embedded Systems, identifying international, national and cluster programs.

Main Objectives

European companies and other research and development organisations active in the field of Embedded Computing Systems took the lead in establishing, under the Sixth Framework Programme, the European Technology Platform on Embedded Computing Systems (referred as the "ARTEMIS Technology Platform").

One of the main ambitions of ARTEMIS, the Advanced Research and Technology in the Embedded Intelligent Systems Technology Platform when started in 2004, was to overcome the fragmentation in the Embedded Systems, by cutting barriers between application sectors so as to ‘de-verticalize’ the industry, sharing across sectors tools and technology that are today quite separate and establishing a new embedded system industry that supplies tools and technology that are applicable to a wide range of application sectors.

The ARCADIA project main objective is to have better and effective coordination of the efforts in order to optimize the use of the resources, and to contribute in to the advance of an ERA for the Embedded System field to strengthening Europe's future growth, competitiveness and sustainable development.

The ARTEMIS Technology Platform developed a Strategic Research Agenda based on an extensive consultation with public and private stakeholders. An update of this SRA is planned for end of 2010.

ARCADIA will focus on aligning

National and Regional European

Agendas in EmbeddedSystems


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Technical Approach

Indeed, there is a strong need to pursue the efforts to consolidate these achievements in order to advance the European Research Area building, particularly for coordinating national, regional and EU-wide R&D strategies and in undertaking actions and initiatives to advance the European Research Area and to align research agendas in the field of embedded systems.

ARCADIA – Joining forces ARCADIA Project aims at building on top of these solid grounds. ARCADIA is conceived as an effective coordination among these initiatives, using the results obtained so far and closely collaborating in the execution of the project tasks. This will be achieved by:

� Joining the multiple initiatives in the embedded system field, benefiting from the work done so far, avoiding duplication of efforts and aiming at ONE common vision.

� Mobilising resources from partners that are active members of ARTEMISIA representatives of the SME, academia and research organisations as well as large industrial groups.

� Actively seeking coordination with on-going initiatives, in particular COSINE2 and ARTEMISIA SRA WG, facilitating the bridge between a large number of National/regional authorities in Europe and industrial groups.

� Establishing relationships with embedded systems education and training, linking with the working groups in ARTEMISIA.

� Giving more visibility to all stake holders of the different perspectives (political, technical, national and European) through common dissemination events

Key Issues

ARCADIA process will follow the next key issues in order to success:

1. Transparency: as the decision taking procedures within the process are clearly and openly stated and each decision is properly justified on the basis of pre-defined criteria.

2. Open participation: that are public and known to every participant will allow the participation of all relevant stakeholders and any interested party

3. Commitment: the Participants will explicitly accept the rules and commit to the process, which involves supporting the outcome of it.

4. Consensus building: As the overall idea of the process is not to find an equidistant point from different positions but to reason together to enlarge the area of agreements: making the pie larger, rather than playing a zero sum game.

Expected Impact

The benefits for embedded systems research gained through ARCADIA can be summarised as follows:

� Advice on an effective and efficient use of the scarce R&D resources to advance the European Research Area

� Make particular focus on research priorities, such as the Embedded Systems Design, to advice on the best funding scheme to address them: FP7, ARTEMIS JU, National/Regional, Eureka

� Practical approach for aligning national and regional programmes sharing a common vision, but addressing specificities in their areas of competence.

� A comprehensive understanding of expected impact of R&D programmes in business and society.

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At A Glance: ArtistDesign

ArtistDesign Network of Excellenceon Embedded Systems Design

Project Scientific Coordinator Name: Joseph Sifakis Institution: Verimag Laboratory Email: [email protected]

Project Technical Coordinator Name: Bruno Bouyssounouse Institution: Verimag Lab/UJF Filiale Email: [email protected]

Project website: http://www.artist-embedded.org/

Partners:Univ. Joseph Fourier/VERIMAG UJF Filiale SAS – Floralis RWTH Aachen, Aalborg University Univ Aveiro Univ of Bologna, TU Braunschweig Univ of Cantabria CEATU Denmark TU Dortmund EPFLESIETHZIMECINRIA

Univ of Kaiserslautern KTHLinköpingUniv of Lund Mälardalen Univ OFFISPARADESUniv of Passau Scuola Superiore Sant’Anna Porto Polytech Saarland Univ Univ of Salzburg Uppsala University TU Vienna Univ. of York

Duration: 48 Months Start: 2008.01.01EC Contribution: € 4.5 M

Contract Number: NoE 214373

NETWORK OF EXCELLENCE Embedded Systems Design

ArtistDesign ArtistDesign Network of Excellence on Embedded Systems DesignThe ArtistDesign NoE is the visible result of the ongoing integration of a community. It builds on existing international visibility and recognition, to play a leading role in structuring the area. KEYWORDS: Embedded Systems Design, Systems Architecture, Systems Engineering, Real-Time Programming, Applications, SoC, Dependability, Modelling, Model-based Design, Hard Real Time, Adaptive Real Time, Component-based Design, Compilers, WCET, Timing Analysis, Execution Platforms, Control for Embedded, Testing, Verification, Integrated Modular Avionics, Autosar, Wireless Sensor Networks, Distributed Systems

Main Objectives

The central objective for ArtistDesign is to build on existing structures and links forged in Artist2, to become a virtual Center of Excellence in Embedded Systems Design. This will be mainly achieved through tight integration between the central players of the European research community. Also, the consortium is smaller, and integrates several new partners. These teams have already established a long-term vision for embedded systems in Europe, which advances the emergence of Embedded Systems as a mature discipline.

ArtistDesign is the main focal point for

dissemination in Embedded Systems Design, leveraging on well-established infrastructure and

links.

ArtistDesign will extend its dissemination activities, including Education and Training, Industrial Applications, as well as International Collaboration.

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ArtistDesign will establish durable relationships with industry and SMEs in the area, especially through ARTEMISIA / ARTEMIS. ArtistDesign will build on existing international visibility and recognition, to play a leading role in structuring the area. The research effort aims to integrate topics, teams, and competencies, grouped into 4 Thematic Clusters: “Modelling and Validation”, “Software Synthesis, Code Generation, and Timing Analysis”, “Operating Systems and Networks”, “Platforms and MPSoC”. “Transversal Integration” covering both industrial applications and design issues aims for integration between clusters.

Technical Approach The ArtistDesign NoE implements a Joint Programme of Activities, composed of:

� Joint Programme of Management Activities(JPMA) plan, organize, direct and monitor the integrated effort to efficiently achieve the technical objectives within the ArtistDesign constraints of time schedule and budget.

� Joint Programme of Activities for Spreading Excellence (JPASE) These activities serve as a relay between the NoE and the international embedded systems design community at large. They are managed at the NoE level, and are mostly not specific to any cluster.

� Joint Programme of Integration Activities(JPIA) The JPIA activities are carried out on a global, NoE level, transcending the clusters. They form the supporting background for integration of the NoE, and are executed in phase and in interplay with the JPRA research activities.

� Joint Programme of Research Activities(JPRA) The JPRA is structured into 4 Thematic (horizontal) Clusters, and a Transversal Integration workpackage. Thematic clusters are autonomous entities, with specific objectives, teams, leader(s), and a dedicated yearly budget.

The set of Thematic Clusters cover all the main topics in Embedded Systems Design. The thematic activities in the Transversal Integration workpackage focus on Design methodologies, with specific objectives (Predictability, Adaptivity).

Expected Impact

The ArtistDesign NoE actions target the embedded systems community as a whole, at 2 levels:

1. Actions targeted towards the affiliated partners Affiliated partners are not core members in the consortium, but receive support for travelling to ArtistDesign meetings, and actively contribute to the implementation of the Joint Programme of Activities (JPA). These affiliated partners include industrial, SME,academic, and international affiliates.

2. Targeted towards the scientific and technical community in the largeThis is achieved mainly bottom-up through the organization of scientific events, publications,distribution of tools and components, industrial partnerships (not funded by ArtistDesign), education; and through the Artist2 web pages.

Regarding Scientific events, we distinguish between conferences and workshops, schools, and high-level events mainly for International Collaboration.

Key Issues

The research effort aims to integrate topics, teams, and competencies, grouped into 4 Thematic Clusters: “Modelling and Validation”, “Software Synthesis, Code Generation, and Timing Analysis”, “Operating Systems and Networks”, “Platforms and MPSoC”. “Transversal Integration” covering both industrial applications and design issues aims for integration between clusters.

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At A Glance: COCONUT

A Correct-by-Construction Workbench for Design and Verification of Embedded

Systems

Project Coordinator: Name: Franco Fummi Institution: University of Verona Email: [email protected]

Project Technical Managers: Name: Graziano Pravadelli, Tiziano Villa Institution: University of Verona Email: [email protected] , [email protected]

Project website: www.coconut-project.eu

Partners:Aerielogic (France) CEA-LETI (France) Certess S.A. (France) Fondazione Bruno Kessler (Italy) University of Southampton (UK) Graz University of Technology (Austria) Universität Paderborn (Germany) Università di Verona (Italy)

Duration: 30 months Start: 2008.01.01Total Cost: € 3.348.224 EC Contribution: € 2.550.000

Contract Number: INFSO-ICT-IST-1-217069


COCONUTA Correct-by-Construction Workbench for Design and Verification of Embedded Systems The COCONUT project is intended to propose a modelling and verification flow to enhance and speed-up embedded platform’s design and configuration of mixed continuous/discrete models KEYWORDS: embedded systems, hybrid systems, modelling, verification

Main Objectives

The COCONUT methodology follows the entire embedded platform design flow starting from specifications through all TLM levels down to RTL synthesis for hardware components, and compilation for software modules. The project addresses refinements related to the design of hardware, software and middleware with particular regards to application fields related to mixed continuous/discrete models, like for example networked multimedia and sensor network management. In this context, the S&T objective of the COCONUT project consists of developing a systematic methodology and a set of tools to integrate correct-by-construction refinement/abstraction and post-refinement verification methods into a platform-based design flow.

1. To define a methodology, supported by tools, to identify system requirements for platform modelling and verification by identifying a connection between hybrid and discrete domains.

2. To provide a methodology to express useful properties at the hybrid and TLM domains, validate their consistency and completeness and use them for semi-automatically synthesizing critical components.

3. To improve and integrate different modelling techniques operating at both hybrid and discrete domains, based on correct-by-construction abstraction/refinement of models and properties.

4. To integrate dynamic and static post-refinement verification around a coherent assertion-based approach.

5. To apply the COCONUT methodology and tools to a real platform for validating the approach and showing its effectiveness in the industry.

COCONUT will focus on the definition of a formal framework based on a

tight integration of designand verification through

all refinement steps of an embedded platform

design flow.

Hereafter, a list ofhigh-level requirements to be considered for the success ofCOCONUT project follows.

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Technical Approach

The embedded platform market is converging on a limited but more powerful set of embedded platforms, mainly due to increasing design cost which requires higher production volume. Differentiation among effective platform configurations is thus a key advantage for a platform user to approach the market with innovative solutions. Design and verification of such a kind of embedded platforms are two highly related problems which are still mainly faced by using unrelated methodologies. The complexity of both platform design and platform configuration requires an innovative design and verification flow able to effectively reduce the number of design errors and design recycles. This is a key factor for increasing system development productivity while achieving predictable system properties. Moreover, an incremental and hierarchical verification strategy is fundamental to manage the huge complexity of this embedded platform that cannot be verified in the whole at a structural level such as the RTL. Even at TLM the platform modelling would be difficult due to the presence of complex networks and continuous-time information. As a result, the addition of hybrid automata to SystemC TLM models will be proposed for tackling the modelling complexity. In both platform design and platform configuration, this very abstracted platform description requires correct-by-construction refinements and/or automatic verification of manual refinements, to translate, without design errors, the abstract description into an actual application. This is the main objective of the COCONUT project. In this context, the key idea of COCONUT is depicted in the next Figure. Platform design and platform configuration are considered as a continuous mix of the following processes:

� definition and validation of properties that represent the specification;

� automatic synthesis of properties into code;

� mapping of models between hybrid and discrete domains;

� correct-by-construction abstraction/ refinement;

� post-refinement verification with respect to the specification.

Such activities will be implemented in a set of tools working on more than one abstraction level whose correctness will be formally proved. Each model/property can be refined to a lower abstraction level or abstracted to a higher abstraction level, and verification should not be only a post-refinement step, but it should guide the design with a correct-by-construction methodology.

Key Issues

The key issue of the COCONUT project can be summarized in the following aspects: 1. Definition of system requirements and validation

of specifications.

2. Automatic synthesis of properties.

3. Mapping between hybrid and discrete domains.

4. Correct by construction abstraction/refinement

5. Post refinement verification

6. Proof of correctness of the COCONUT activities.

Expected Impact

The COCONUT project is in line with the general target of ensuring “improving the competitiveness of European industry and research”, and particularly it is expected to: � Increase the quality of both European research

and industry by putting academia in touch with industrial challenges and allowing SMEs to access the research results they need for anticipating clients’ demand.

� Let European research centres and SMEs increase the productivity of the embedded platform configuration phase, thus allowing a more effective design of innovative embedded systems.

� Fit the objective of “greatly improve industrial production processes” thereby “increasing productivity” and final quality. Indeed, the goal of the project is to ensure system quality at design phase and detect design errors and faults when they are easy to repair.

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Duration: 36 Month Start: 2008.01.01EC Contribution: 2.75 M€

Contract Number: STREP 215543

At a Glance: COMBEST

COMponent-Based Embedded Systems design Techniques

Project Scientific Coordinator: Name: Joseph Sifakis Institution: Verimag Laboratory Email: [email protected]

Project Technical Coordinator: Name: Bruno Bouyssounouse Institution: Verimag Lab/UJF Filiale Email: [email protected]

Project website: http://www.combest.eu/

Partners:Univ. Joseph Fourier UJF/VERIMAG (France) UJF Filiale SAS - Floralis (France) TU Braunschweig (Germany) EADS (Germany), EPFL (Switzerland) ETHZ (Switzerland) INRIA (France) IAI (Israel), OFFIS (Germany) PARADES (Italy) Università Trento (Italy)


COMBESTCOMponent-Based Embedded Systems design Techniques COMBEST will provide a formal framework for component based design of complex embedded systems: 1) formal integration of heterogeneous components; 2) encapsulation of components; 3) prediction of emergent key system characteristics; 4) corresponding certificates.

KEYWORDS: formal frameworks, component based design, complex embedded systems, formal integration, heterogeneous components, models of communication, models of execution, encapsulation functional properties, extra-functional properties, composability, compositionality, system characteristics, performance, robustness, distributed HW-architectures, design theory, heterogeneity, interface specifications, SPEEDS, rich components, compositional analysis

Main Objectives

COMBEST will provide a formal framework for component based design of complex embedded systems. This framework will:

1. Enable formal integration of heterogeneous components, such as with different models of communication or execution;

2. Provide complete encapsulation of components both for functional and extrafunctional properties and develop foundations and methods ensuring composability of components; 3. Enable prediction of emergent key system characteristics such as performance and robustness (timing, safety) from such characterizations of its subcomponents;

To achieve these objectives, COMBEST will:

� Develop a design theory for complex embedded systems, fully covering heterogeneity, interface specifications, composability, compositionality, and refinement for functional and extra-functional properties.

� Build on substantial highly recognized background results of the academic partners, partly carried out within the integrated project SPEEDS.

COMBEST will focus on formal

integration of heterogeneous components.

4. Provide certificates forguarantees of such keysystem characteristics when deployed on distributed HW-architectures

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� Extend results of the Integrated Project SPEEDS, both regarding heterogeneous rich components and compositional analysis methods.

� Collaborate with the best US groups in embedded system design to build critical mass in a strategic area of vital interest to the European industrial ecosystem

Technical Approach

The project pursues a dual approach, combining fundamental work with methods and tools for rigorous embedded systems design.

The fundamental work in COMBEST studies component-based design, by tackling two main problems:

� Developing frameworks for the composition of heterogeneous components.

� For such frameworks, develop theory allowing constructivity: inferring global properties of a system from the properties of its components.

The methods and tools developed use results of the theoretical work, to ensure a rigorous design for heterogeneous systems.

The tools cover modelling, verification, and performance analysis. Their use is supported by a global design methodology. In addition, we use two case studies, provided by industrial partners, to evaluate the relevance and applicability of the tools.

Key Issues

For embedded systems, component-based design techniques should address both hardware and software components in a unified way. They should be able to handle hard constraints on performance and dependability as well as dissimilarities between levels of abstraction and communication primitives. The two main difficulties to handle are: � The presence of heterogeneous components. In

software engineering, components are mainly used for structuring functions and associated data. In contrast, hardware components are inherently parallel, and synchronous.

� Predictability of basic properties of the designed system. We argue in favour of constructivity, which is reasoning about global system properties based on properties of its individual components. Constructivity should allow satisfaction of essential properties by construction, to avoid costly a posteriori global system validation.

Providing formal frameworks which overcome these difficulties is only a first step towards disciplined system design. It is essential that theoretical results be integrated in coherent component-based design flows, validated through comparison with existing industrial practice. Furthermore, theoretical results should be implemented in scalable supporting methods and tools.

Expected Impact

COMBEST will deliver significantly advanced technology for strengthening European excellence in embedded systems design. COMBEST will provide the basis for mastering holistic design methodologies, allowing European industries to maintain and even improve their technological leadership. More specifically, we expect a positive impact for: � Component re-use and domain

independence. The emergence of component-based design as the primary design method for embedded system should allow component reuse across multiple domains. A concentration of the efforts in the European supplier industry will become possible due to emergence of cross-domain tools and methods. This reduction of fragmentation and the focused use of resources will speed up the development cycles in the supplier industry.

� Decreased development cost. Decreasing the development cost is of particular importance in Europe, which tends to have a competitive disadvantage due to high cost of labour.

� Decreased time-to-market. A shorter time to market will give the European industry is a decisive competitive advantage in today’s fast paced business world.

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At a Glance: COMPLEX

COdesign and power Management in PLatform-based design space EXploration

Project Coordinator: Name: Wolfgang Nebel Institution: OFFIS e.V. Email: [email protected]

Project Technical Manager: Name: Kim Grüttner Institution: OFFIS e.V. Email: [email protected]

Project website: http://complex.offis.de

Partners:OFFIS (DE) STMicroelectronics (IT) STMicroelectronics (CN) NXP (NL) Thales Communications (FR) GMV (ES) CoWare (BE) ChipVision (DE) EDALab (IT) Magillem (FR) Politecnico di Milano (IT) Universidad de Cantabria (ES) Politecnico di Torino (IT) IMEC (BE) ECSI (FR)

Duration: 36 Month Start: 2009.12.01Total Cost: 7.2 M€EC Contribution: 4.8 M€

Contract Number: IP 247999


COMPLEXCOdesign and power Management in PLatform-based design space EXploration The primary objective of COMPLEX is to develop an innovative, highly efficient and productive design methodology and a holistic framework for iteratively exploring the design space of embedded hardware/software (HW/SW) systems. KEYWORDS: Design Methodology, Electronic System-Level, Design Space Exploration, Timing, Power Consumption, Platform-based Design, Virtual Platform, UML, MARTE, SystemC™, TLM, IP-XACT

Main Objectives

The COMPLEX consortium develops a new design environment for platform-based design-space exploration offering developers of next-generation mobile embedded systems a highly efficient design methodology and tool chain. The integrated environment allows iterative exploration and refinement of advanced applications to meet market requirements. The design technology in particular enables fast simulation and explores the use of different implementations at Electronic System Level (ESL) with up to bus-cycle accuracy at the earliest instant in the design cycle. The main objectives are: � Highly efficient and productive design

methodology and holistic framework for design space exploration of embedded HW/SW systems. The framework will be platform independent and application domain independent and will provide open interfaces for new industry players.

� Combination and augmentation of well established ESL synthesis & analysis tools into a seamless design flow enabling performance & power aware virtual prototyping of the HW/SW system.

� Multi-objective co-exploration for assessing design quality and optimizing the system platform with respect to performance, power, and reliability metrics.

� Fast simulation and assessment of the platform at ESL with up to bus-cycle accuracy at the earliest instant in the design cycle.

� Optimization benefits from run-time mode adaptation techniques, such as dynamic power management or application adaptation to varying workloads.

COMPLEX will focus on early, fast yet

accurate platform-based design space

exploration at the system-level.

� Interfacing next-generation model-driven SW design approach and industry standard model-based design environments.

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Technical Approach

The COMPLEX framework is a design flow with performance and power aware virtual prototyping of an embedded HW/SW system. Several well established ESL synthesis and analysis tools from vendors such as CoWare, ChipVision, EDALab, and Magillem will be augmented and combined into the seamless COMPLEX design flow.

For co-development the COMPLEX framework follows a new approach using a unified internal representation of the HW and SW, called block annotated C++ (BAC++). It is generated by SW cross-compilers and HW behavioural synthesis tools. In the COMPLEX framework, the generated BAC++ code is integrated into a SystemC™/TLM2 virtual platform model, enabling fast system simulation.

The hardware/software co-exploration considers both the architecture design space and the application space to assess trade-offs when designing next-generation embedded systems. The co-exploration is multi-objectively assessing the design quality and optimizing the system platform with respect to performance, power, reliability metrics, etc. The optimization benefits from run-time mode adaption techniques, such as dynamic power management or application adaption to evolving workloads, can be maximised and reported to successive synthesis steps using standardized output formats.

The framework combines several standards for system modelling and integration: Possible design entry is either in C++/SystemC or a MARTE/UML model, offering seamless integration into a model-driven design approach.

Key Issues

Existing barriers between HW and SW developers are lowered, allowing SW designers to explore various HW implementations and hiding irrelevant technical details, thus having a clear view on the results of the application code transformations in terms of timing behaviour and power consumption.

The COMPLEX framework enables system integrators to find the ideal technology platform. Technology providers benefit from COMPLEX since they can now offer fast and accurate platform models to their customers. EDA companies are offering a more complete solution to their customers with the COMPLEX framework.

Expected Impact

The COMPLEX results are expected to support the overcoming of technology roadblocks by reinforcing Europe's industrial strengths for building increasingly smaller, cheaper, more reliable and less power consuming electronic components and systems, taking into account the alternative paths to next generation technologies and sustainable development. The provision of environmentally friendly sustainable systems is a key differentiating factor in various applications. Moreover, this will support the competitiveness of industrial players such as automotive, avionics, industrial automation, consumer electronics, telecoms, and health. Consequently, COMPLEX will lay the foundations for innovation in various major products and services.

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At A Glance: COSINE2

Co-ordinating Strategies for Embedded Systems in the European Research

Area Follow-up Project

Project Coordinator Name: Dr. Erich Prem Institution: eutema Technology Management GmbH

Project Technical Manager Name: Martin Marek Institution: eutema Technology Management GmbH Email:[email protected]

Project website: www.cosine-ist.org

Partners:Eutema (Austria) Tekes (Finland) DLR (Germany) ISERD (Israel) UTIA (Czech Republic) VINNOVA (Sweden) BMVIT (Austria) NKTH (Hungary) IWT (Belgium) MUR (Italy) CEA (France)

Duration: 30 months Start: 2007.12.01Total Cost: € 600.000EC Funding: € 600.000


COSINE2Co-ordinating Strategies for Embedded Systems in the European Research Area Follow-up Project COSINE2 aims to enhance the impact of European RTD strategies in the area of Embedded Systems. To achieve this, it will be necessary to better align national research strategies with each other, with the EC programmes, and with new initiatives such as the ARTEMIS ETP (European Technology Platform) and the JTI (Joint Technology Initiative) on Embedded Systems. KEYWORDS: European Research Area (ERA), ERA-Net, Embedded Systems, Embedded Intelligence, National research funding programmes.

Main Objectives

The core aim of the Support Action is to improve co-operation between EU, national, and regional ES RTD programmes and policies and to realize the vision of European Embedded Systems Research Area. One particular aim is to open more national EU ES programmes for participants from other EU member states. COSINE2 will offer support for policy representatives and programme managers willing to co-operate. COSINE2 aims at offering a service to all European RTD policy actors willing to co-ordinate their programmes, regardless of their representation in the Support Action.

An important sub-goal of COSINE2 is to install a process for continuous monitoring of ES strategies, policy and programme actors, and funding opportunities. This should also include links to selected international activities to allow informed decision making and to inform the research community, policy actors, and programme managers. In close co-operation with other EU projects such as ARTIST, COSINE2 aims to improve co-operation in the areas of education and training which are rather isolated today in the EU’s member states. COSINE2 aims at establishing and maintaining close contacts with the ARTEMIS Joint Technology Initiative taking opportunity of the representation of COSINE members in the ARTEMIS public authorities institutions. COSINE2 aims to interact with EU ES industry, to support the member states’ actors, and to assist at the level of national public policies. Also, COSINE aims at monitoring SME issues in ARTEMIS and in the JTI on Embedded systems.

COSINE2 also intends to collect success stories of other co-operative programmes. Alignment and co-ordination of strategies requires information on ES policies at EU and member states level.

COSINE2 will further improve co-operation between EU, national, and

regional Embedded Systems

programmes and policies.


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Technical Approach

COSINE2 will achieve its goals based on linking Embedded Systems programme managers and policy makers, the EC and regional actors and creating the basis for informed strategic policy choices. It will distribute best-practice examples for trans-national co-operation and facilitate focused interaction with the industry driven ARTEMIS technology platform. COSINE2 will support countries developing or implementing Embedded Systems RTD strategies regardless of their participation in the project. Dedicated co-operation with regional organisations will improve the involvement of small and medium sized enterprises in research actions and accelerate the take-up of ES technology. COSINE2 will create wide impact with information services on ES RTD initiatives for policy makers, programme managers, and the research community. In this way, COSINE2 will realize the vision of a European Embedded Systems Research Area. Work is structured in four packages and project management. WP1 addresses European strategies and programmes for Embedded Systems. WP2 deals with the important relation to the ARTEMIS initiative. WP3 targets public relation and dissemination of project results. And WP4 tackles strategies for small and medium sized enterprises. Although COSINE2 as a Support Action cannot address SMEs individually, COSINE2 aims at getting the attention of important regional actors in the innovation system for the ES topic. COSINE2 aims at receiving public awareness and interaction with the stake holders. Instead, COSINE2 aims at linking and pinpointing existing information and combining it with newly collected and generated information for research policy makers but also for researchers. Also in this line, COSINE2 aims at fostering a discussion with the ES research on community on strategic research areas. COSINE2 aims at an efficiently managed policy support action that remains sensitive to the individual interests of the member states.

Key Issues

Embedded Systems are a key driving innovation factor in leading European industry sectors such as consumer electronics, automotive, or aerospace. As a reaction, policy makers in the EU and members states have created a collection of dedicated RTD initiatives. It is now time to improve their impact through opening, co-operation, and co-ordination with key strategic initiatives such as the ARTEMIS technology platform. COSINE2 will facilitate the opening of national research programmes, and create synergy among EU, national, and regional programmes and policies to improve the European Research Area for Embedded Systems. While the advent of the ARTEMIS technology platform and the Joint Technology Initiative have generated considerable dynamics in the area of embedded systems research and technology, many member states or regions in Europe still run their own programmes. COSINE2 is an effort to align these programmes. Also, COSINE2 aims at supporting countries in developing their first or new ES programmes and, most importantly, in trans-national co-operation of programmes.

Expected Impact

COSINE2 will enhance research and technology in the area of Embedded Systems in Europe through optimizing the alignment of national research strategies. COSINE2 also aims at leveraging the co-operation of research programmes to a new level. It will tune RTD policies optimally to the new European Embedded Systems Research environment currently under significant change in the EU. The consortium joins national authorities and research agencies with the power to durably influence the European research area.COSINE2 is a strategic initiative to maintain Europe’s strong international position in the area of Embedded Systems technologies.

WP 5Management

WP 2ARTEMIS(IA) support

ES RTD Strategies

WP 1 PoliciesProgrammes

WP 4SMEsupport

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At A Glance: DESTECS

Design Support and Tooling for Embedded Control Software

Project Coordinator Name: Jan F. Broenink Institution: University of Twente Email: [email protected]

Project website: www.destecs.org

Partners:University of Twente (Netherlands) Newcastle University (United Kingdom) Engineering College Aarhus (Denmark) CHeSS B.V. (Netherlands) Controllab Products B.V. (Netherlands) Neopost Technologies B.V. (Netherlands) Verhaert New Products & Services N.V. (Belgium)

Duration: 36 monthsStart: 2010.01.01Total Cost: € 3 622 190 EC Contribution: € 2 739 175


1 Co-simulation is running executable, heterogeneous models of parts of the system and its environment in one harness together, allowing communication between them with the aim of understanding how well or badly the resulting embedded system may perform in practice. 1 Fault injection means explicitly modelling abnormal behaviour of the environment and introducing faults to certain primitives. This allows early exploration of the consequences of defects and errors, and hence improved selection of design alternatives, including fault tolerance strategies.

Main Objectives

The goal of DESTECS is to improve the productivity of innovative embedded system design by providing new methods and tools that can be used to design fault-tolerant, embedded systems using a multidisciplinary, collaborative model-driven approach, with the following objectives: � To reduce the effort spent in design iterations

compared to current best practice for fault-tolerant embedded control systems by means of multidisciplinary collaborative modelling.

� To evaluate, in an industrial setting, the effectiveness of collaborative modelling methods and tools for rapid design exploration and tool support.

� To build a user and research community in collaborative modelling and co-simulation for embedded systems development.

Technical Approach

We will develop methods and tools for the construc-tion, co-simulation1, multi-domain fault injection2 tests and maintenance of collaborative models of control systems. Maintenance encompasses managing the evolution of models under change (including refactoring) so as to maintain their compatibility and traceability.

DESTECS will focus on model-driven

methods & tools for fault-tolerant

embedded control software design

� To demonstrate the viability of industry-strength open tool support for collaborative modelling and co-simulation.

DESTECSDesign Support and Tooling for Embedded Control Software

DESTECS will develop a methodology that combines continuous-time models with discrete-event models through co-simulation and multi-domain fault injection tests to faster build more dependable real-time embedded systems.

KEYWORDS: embedded control software, dependability, fault-injection co-simulation, model-based design, design tools, formal methods.


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Leading research challenges are: providing support for potentially large multi disciplinary models, and describing faults and fault tolerance mechanisms. In effect, we develop a specification of a “Model Base” for collaborative design. In DESTECS, we will develop tools and methods in three phases of 1 year each, thus giving annual intermediate results. Industry-led evaluations (industrial case studies) run concurrently with the methods and tool development work. In each phase, the same case studies are conducted, but using increasingly developed methods and tools. In phase 1, existing tools (20-sim and Overture/VDM++) are used for the cases; in phases 2 and 3, the methods and tools developed within DESTECS in the previous phase are used. Feedback from these test cases is used in the next methods / tool development phase. The industrial case studies are: (1) modular document handling system, to be made more reconfigurable using DESTECS results; (2) an inertial measurement unit, to be faster incorporated in applications; and (3) a bi-wheeled personal transporter, being a demanding test case for DESTECS model-driven approaches, as the system is intrinsically unstable. Additionally, new examples will be gathered from industry via the Industry Follow Group (IFG), in order to gain an evaluation of the potential benefits and challenges of deploying collaborative modelling and co-simulation in real industrial contexts.

Key Issues

DESTECS will advance model-driven development by focusing on two engineering domains: (1) discrete event modeling of controllers and architectures and (2) continuous-time modeling of physical systems. By coupling these domains through co-simulation, cross-domain design issues can be tackled even in the early stages of a design process.

DESTECS will exploit co-simulation as a basis for modelling faults and analysing fault tolerant designs for embedded systems that need to be predictably resilient. We will develop an Integrated Development Environment (IDE) with plug-in tools that support the integration of continuous and discrete modelling tools. This helps to close the gap between the discrete-event and the continuous-time models. DESTECS will not replace current practice but it will support the heterogeneity of tools and encourage collaborative design by allowing best practices in different engineering domains to be integrated.

Expected Impact

The DESTECS technology will increase productivity because it will provide a common framework (methods and tools) in which models may be developed and simulated rapidly together at an early stage. This means that the most abstract models in both worlds can be co-simulated and feedback can be provided between the different disciplines “up front”. This common framework makes it natural and easier to explore fault tolerance of the full system at a much earlier stage, potentially saving significant amounts of rework. So the DESTECS technology impacts the cost of development (due to reduced rework), the time to market (due to better ability to do the development in parallel and synchronise across disciplinary boundaries) and the dependability (through earlier and more reliable handling of potential faults and fault tolerance) of the product.

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At A Glance: EMBOCON

EMBedded Optimization for resource CONstrained platforms

Project Coordinator: Name: Dr. Paul Goulart Institution: Imperial College London Email: [email protected]

Project website: www.embocon.org

Partners:Imperial College London (UK) Katholieke Universiteit Leuven (Belgium) ETH Zurich (Switzerland) University of Heidelberg (Germany) University Politehnica Bucharest (Romania) Technische Universität Dortmund (Germany) LMS International LMS (Belgium) IPCOS NV (Belgium) BASF SE (Germany)

Duration: 36 monthsStart: 2010.01.15Total Cost: € 4514950EC Contribution: € 3249814

Contract Number: ICT-

EMBOCONEMBedded Optimization for resource CONstrained platforms The EMBOCON project aims to radically expand the scope of embedded systems applications to which embedded optimization and control methods can be applied. KEYWORDS: Embedded systems, real-time optimization, numerical algorithms.


Main Objectives

An embedded system must be able to make reliable decisions with limited or no human assistance, often in real-time, drawing on observations made of its environment. This applies, for example, to ABS in cars, engine controllers, aircraft autopilots, dispatching systems in electrical and gas networks and to various medical systems. To date, most of these decisions are computed either with simple algorithms or by look-up tables generated through simulation and extensive testing. The simplicity of these algorithms facilitates an intuitive understanding as well as their real-time implementation, often on low-cost and low-performance hardware.

In contrast, an embedded optimizer takes sensor input and chooses the best action to follow based on criteria specifying desirable outcomes and a model of how the environment would respond to system actions. This procedure would typically be repeated periodically, or be triggered by external stimuli, thus enabling the embedded system to adapt to changes in its environment. This optimization-based embedded system design paradigm has been proven to offer dramatic improvement over traditional schemes, which are largely designed around heuristic rules requiring extensive tuning and experience.

Widespread deployment has been hindered primarily by the non-determinism of current algorithms, the inability of existing optimizers to function on competitively priced hardware and a lack of robust design methods. EMBOCON addresses these issues through a comprehensive work program focused on optimization under real-time, resource and reliability constraints.

EMBOCON is founded on close collaboration between mathematical algorithm developers,

control theorists, hardware specialists

and industrial partners.

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Technical Approach

In order to enable the use of real-time optimization on embedded systems, it is not possible to consider the behaviour and performance of optimization and control algorithms in isolation for the particular embedded systems hardware on which they are implemented. Instead, it will be necessary to bring about a unification of methods in control theory, mathematical optimization, electronic engineering and computer science.

Optimization for Embedded Systems The challenges addressed by the EMBOCON consortium focus on systems that are pushing the boundaries of what is possible: either very fast or complex dynamics and/or very limited computational resources. The consortium will focus specifically on developing optimization algorithms that provide firm run-time guarantees, stability and robustness guarantees, and graceful performance degradation in the presence of tight computational constraints. A variety of algorithmic methods, tailored to embedded systems applications and addressing the most common classes of optimization problem, will form a set of EMBOCON core optimization modules.

An Open Platform for Embedded Optimization Uptake of embedded optimization methods in European industry, including the EMBOCON core modules, will be enabled through the release of an open-source software platform for embedded optimization. This platform will serve as a common interface for algorithm developers and industrial practitioners, enabling rapid prototyping of optimization-enabled systems. EMBOCON will act as a driver for the development of this platform, whose lifetime will far exceed that of the proposed program.

Industrial Benchmarks EMBOCON will demonstrate that embedded optimization is ready for widespread industrial application across many sectors. A selection of industrial benchmarking studies, drawn from the automotive, process control, aeronautics and robotics industries, will demonstrate the feasibility and benefits of real-time optimization. These demonstrators will show both the benefits of embedded optimization in real-world settings, as well as the ease of application and effectiveness of the EMBOCON open software platform.

Expected Impact Real-time optimization has already revolutionized industrial practice in some industries, particularly in process control. Advances in modern computing hardware and algorithmic methods now offer an opportunity to bring these same benefits to a huge range of new industries.

The EMBOCON project will bring embedded optimization into standard practice on ubiquitous resource-constrained hardware found in real-time and mission-critical applications across Europe. The creation of a standard software platform for developers and practitioners will improve substantially the uptake of embedded optimization in industrial practice.

The EMBOCON consortium will strengthen a network of world-leading academic and industrial partners with complementary expertise in control, optimization and embedded systems in a range of industrial applications. Particular emphasis is placed on close collaboration between mathematical algorithm developers, control theorists, hardware specialists and industrial application engineers. The consortium will consolidate and extend Europe’s position as the world research leader in these areas and foster strong collaborative links between European academia and industry.

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At A Glance: ENOSYS

intEgrated modelliNg and synthesis tOol flow for embedded SYStems design

Project Coordinator Name: Dr. Andrey Sadovykh Institution: SOFTEAM Email: [email protected]

Project website: www.enosys-project.eu

Partners:SOFTEAM, Thalès Communications (France) Axilica, Loughborough University (United Kingdom) Intracom Telecom, University of Peloponnese (Greece)

Duration: 36 months Start: 2010.01.01Total Cost: €3,97 M€ EC Contribution: €2,6 M€


ENOSYSintEgrated modelliNg and synthesis tOol flow for embedded SYStems design ENOSYS will provide an integrated design flow for a rapid development of SoC embedded systems a) by the automated generation of SystemC code from the high-level specification; b) by rapidly determining near-optimal solutions for hardware/software partitioning.

KEYWORDS: MARTE, SysML, SoC, integrated design flow, co-design, design space exploration, automated partitioning, automated hardware and software synthesis

Main Objectives

The aim of the ENOSYS project is to specify and develop a tool supported design flow for designing and implementing embedded systems by seamless integration of high-level system specifications, software code generation, hardware synthesis and design space exploration. ENOSYS will provide an integrated workbench combining SysML, MARTE and FalconML. The OMG SysML and MARTE will be evaluated and extended to address end-user demands and requirements for integration. The approach and the tool flow will be evaluated and validated with representative scenarios from the telecoms domain. The results will be reported and presented at OMG in order to influence standardization and improve opportunities for adoption. The specific scientific and technological objectives include: � Develop MARTE extensions that address the

needs for capturing high level specificationand for design synthesis.

� Develop the means for the rapid and automated determination of near-optimal embedded system implementations using design space exploration.

� Develop the tool support required for seamless software/hardware co-design.

ENOSYS will focus on an integrated design

flow including advanced system modelling, design

space exploration and hardware/software synthesis of SoC

systems.

� Integrate the MARTE profile into the existing tool flow, permitting the automaticgeneration of SystemC and the hardware synthesis of HDL.


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Technical Approach

The proposed ENOSYS integrated tool chain will allow the development of arbitrary-complexity silicon processing platforms using both automatic and semi-automatic methodologies. Starting at the specification level, design intent is captured precisely and unambiguously in an object-oriented language based on UML MARTE profile. In addition, existing hardware and software intellectual property (IP) blocks are seamlessly accommodated in the design flow. The later is driven by graphical design entry at the UML level. The ENOSYS tool chain undertakes the process of code generation for a programmable platform, including the SoC interconnect backbone and the multi-level wrappers, resulting in a high-performance simulation engine and more importantly, the behavioural synthesis of the non-CPU mapped UML objects into hardwired, streaming engines. The tool chain (fully automatic mode) or the designer (semi-automatic mode) can quickly analyze the performance of candidate architectures and determine which will be the most effective, according to the given optimization criteria, such as embedded memory optimisation and interconnect architecture, bandwidth, silicon area, operating frequency and power consumption. The tool will prune and perform exploration of the design space using a search-based approach, such as a genetic algorithm, to analyse candidate architecture and micro-architecture solutions at rates of tens of configurations per minute. Finally, the few configurations that satisfy the performance criteria will be presented and further refined in the process of converging to a near-optimal solution.

Key Issues

Today, SoC vendors realize that critical decisions must be made long before development teams engage in the hardware and software design for new SoC and programmable SoC-based products. It is becoming clear that hardware-software design and verification must form part of a single, unified effort, whereas the methodologies currently available were intended to aid either hardware-only or software-only development. That these tools are no longer adequate for modern SoC designs is confirmed by the recent emergence of new concepts that are disrupting the traditional design flow; these include system-level specification (specification capture), functional and architectural analysis, and high-level estimation, partitioning and software synthesis.

Sys

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YS

Sys

tem

Mo

del

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Flo

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System and Requirements Modeling

System Model Refinement (MARTE conceptual

modelling)

Detailed System Modeling (Action code insertion)

Native Code Generation

Native mode execution

Vectors passed?

N

Automatic Action Code Source-Source transformation

(1)

Ver

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n (

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1)

System Specification

(Textual)

Hardware System Behavioural Synthesis

Target Platform Model

Automatic Hardware/Software Partitioning

Software System Synthesis

Cycle/Bit-true System Model (Software and Hardware)

Multicore CPU System Synthesis

Performance Evaluation (System Execution, RTL/SystemC)

Area/Performance objectives achieved

Y

SystemC Execution

Vectors passed?

NY

N

Y

Software Component

Hardware Component

Downstream Implementation Flow Standard-Cell/FPGA)

EN

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SMF: 1

SMF: 2

SMF: 3

SMF: 4

SDF:1

SDF:2a

SDF:2b SDF:2c

SDF:3

SDF4

System Area/Power/Performance constraints

Expected Impact

ENOSYS targets the following main impact objectives:

� Significantly increased productivity of embedded system development and shorten time-to-market for SoC systems.

� Reinforced European scientific and technological leadership in the design of complex embedded systems.

� Improved competitiveness of European companies that rely on the design and integration of embedded systems in their products by reducing design costs and time to market.

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At A Glance: ERA

Embedded Reconfigurable Architectures

Project Coordinator Name: Stephan Wong Institution: Delft University of Technology Email: [email protected]

Project website: www.era-project.eu

Partners:Delft University of Technology (The Netherlands) Industrial Systems Institute (Greece) University of Siena (Italy) Chalmers University of Technology (Sweden) University of Edinburgh (United Kingdom) Evidence s.r.l. (Italy) ST Microelectronics (Italy) IBM Research Laboratory (Israel) Federal University of the Rio Grande do Sul (Brazil)

Duration: 36 months Start: 2010.01.01 Total Cost: € 4.014.513,00EC Contribution: € 2.8 M


ERAEmbedded Reconfigurable ArchitecturesERA aims at investigating and developing new methodologies in both tools and hardware designs to break through current power and memory walls for the next-generation embedded systems platforms. The proposed strategy is to utilize adaptive hardware to provide the highest possible performance for given power budgets. The envisioned ERA platform is adaptive and employs a structured design to integrate the necessary computing, networking, and memory elements. KEYWORDS: reconfigurable/adaptive computing, memory hierarchies, power models, parameterized processor designs, dynamic reconfiguration, power awareness, structured embedded systems design, application profiling and benchmarking, embedded Linux, reconfiguration-aware compilation algorithms, fault-tolerance, dynamic parallel execution, gcc compiler.

Main Objectives

In the Objective ICT-2009.3.4 "Embedded Systems Design", a strong focus is placed on the development of novel (generic) design methodologies that can be applied to several application areas. In the ERA project, we describe a platform that can adapt itself through coarse-grain reconfigurable hardware to tailor the hardware itself for changing environments and needs of the applications running on the platform, for different application markets and platform usage. We identified the following main objectives: � to define and develop a dynamically

reconfigurable integrated platform composed by the following components: a parameterized VLIW processor, a reconfigurable NoC, and a memory subsystem - taking into account power consumption as design parameter

� to provide the needed hardware monitoring and low-level OS support to efficiently control the hardware reconfiguration.

ERA will focus on the development of

an adaptive embedded system platform to handle the challenges of

current embedded processor designs

� to provide the support for flexible and fast reconfiguration of the platform by using direct hardware support as well as partial FPGA reconfiguration.


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� to benchmark and analyze a set of existing applications in the area of mobile processing to extract a set of off-line and on-line measurable parameters.

� to build a supervisor which will be able to monitor the parameters and react to online application changes to appropriately reconfigure the hardware.

The envisioned adaptive ERA platform employs a structured design approach that allows integration of varying computing elements, networking elements, and memory elements. For computing elements, we will utilize a mixture of commercially available off-the-shelf processor cores, industry-owned IP cores, and application-specific/dedicated cores, and we will dynamically adapt their composition, organization, and even instruction-set architectures to provide the best possible performance/power trade-offs. Similarly, the choice of the most-suited network elements and topology and the adaptation of the hierarchy and organization of the memory elements can be determined at design-time or at run-time. Furthermore, the envisioned adaptive platform must be supported by and/or made visible to the application(s), run-time system, operating system, and compiler exploiting the synchronicities between software and hardware. We strongly believe that having the complete freedom to flexibly tune the hardware elements will allow for a much higher level of efficiency (e.g., riding the trade-off curve between performance and power). Finally, an additional goal of the adaptive platform is to serve as a quick prototyping platform in embedded systems design.

Technical approach

In the ERA project, we identified four key areas to pursue innovations in order to achieve our objectives: � definition and characterization of application

benchmarks for embedded systems employing reconfigurable architectures.

� definition of a reconfigurable and parameterized processor architecture.

� definition of a reconfigurable memory subsystem.

� definition of the software/compiler tools and OS support for the ERA platform.

The applications exhibit behaviour that can be exploited for more efficient processing (at given power budgets) by adapting the hardware (processor and memory) to them. This paradigm shift requires new approaches in compiler algorithms and tools and advanced (embedded) OS-level support. All partners have expertise in one or several of the mentioned areas.

Key Issues

We believe that the run-time adaptive behaviour of the ERA platform is the key to develop embedded platforms for the new, heterogeneous and multi-applications embedded market. A major concern is the power utilization. This translates in several key issues that must be addressed in order to achieve a breakthrough. To cope with the reconfiguration power problem, in this project we focus on the development of accelerators using a coarse-grain reconfigurable fabric, composed of a reconfigurable VLIW processor, a flexible memory organization and an interconnection network that can provide better usage of power resources by distributing its routing resources online. A software stack consisting of a compiler and OSwill provide the means to drive both static and dynamic reconfiguration decisions according to the application characteristics and the user objectives (in terms of power and performance).

Expected Impact

The industrial partners clearly identified the benefits of the ERA project expressed in their involvement in and commitment to the project. All the solutions proposed in this project will be combined in a demonstrator platform that we expect will allow the industrial partners fast access to new products developed on top of it. The intended platform will serve several purposes: � Quick development platform for the industry: the

clear interfaces defined in this project should allow the industrial partners to take from the platform everything they need and still incorporate their own IPs. Moreover, for low volumes even the prototype can be used as a commercially viable product, since the consortium will use available FPGA technology to validate its contribution.

� Academic purposes: the ERA platform can be easily used to build different instances of embedded processing solutions and we foresee and will actively pursue the possibility of incorporating the ERA platform as a teaching tool in embedded courses or labs.

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At A Glance: GALAXY

GALS InterfAce for CompleX Digital SYstem Integration

Project Coordinator: Name: Dr. Milos Krstic Institution: IHPEmail: [email protected]

Project website: www.galaxy-project.org

Partners:IHP (Germany) The University of Manchester (UK) Ecole Polytechnique Fédérale de Lausanne (Switzerland) Alma Mater Studiorum - Università di Bologna (Italy) Silistix UK Limited (UK) Infineon Technologies AG (Germany)

Duration: 36 months Start: 2007.12.01Total Cost: € 4.079.489 EC Contribution: € 2.900.000


Main Objectives

The increased complexity, performance requirements, and the need for power and EMI reduction present almost unsolvable challenges to designers of complex embedded systems. The continued technology improvement generates additional problems for embedded system design. The combination of complex application requirements and technology imperfections exacerbate the problems of timing closure and clock tree generation requiring additional design iterations. It is imperative to deal with these issues; one very promising option is the use of a Globally Asynchronous Locally Synchronous (GALS) design methodology.

Firstly, the design-flow for GALS chip interconnect is not mature enough to guarantee reliable and comfortable chip design. Secondly, the main strengths of GALS design, such as improvement of system integration, better EMI characteristics and power reduction, were never completely exploited and proven in practice. Lastly, the targeted GALS applications were sometimes not a perfect match with the GALS techniques. In this project, we address these problems and intend to prove that the GALS methodology offers powerful solutions for modern embedded system design integration. We aim at promoting the development of GALS system design by providing an interoperability framework between the existing open or commercial CAD tools for rapid design and prototyping. We will explore and evaluate the ability of GALS to solve system integration issues as well as building on its reduced EMI and low-power properties. A promising target platform can be seen in the area of Networks on Chip (NoC). In this project we intend to investigate different approaches of implementing GALS-enabled NoC platforms, comparing them with fully synchronous implementations, and of integrating the NoC design flow into the GALS design flow.

GALAXYGALS InterfAce for CompleX Digital SYstem Integration The project evaluates the ability of the GALS approach to solve system integration issues and implement a complex GALS system on an advanced 40 nm CMOS process.KEYWORDS: GALS, Asynchronous Design, System Integration, NoC

GALAXY will focus on the GALS low EMI properties,

inherent low-power features and robustness to

process variability problems in nanoscale

geometries

When analyzing why a GALS approach has not been adopted by industry we observe that several issues have not been fully addressed until now.


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Furthermore, nanoscale technologies have their own issues such as process variability and reliability. In the framework of this project we will explore these critical issues in the context of GALS. Additionally we intend to evaluate the effectiveness of a GALS system design for a highly complex wireless communication application in a very advanced 40 nm CMOS process.

Technical approach

On the basis of the previous discussion, we are planning to analyse existing GALS solutions. During the project we will select optimal GALS architectures for the target applications and define the communication interfaces.In this project, a GALS framework providing interoperability between design tools for rapid design and prototyping will be proposed. This design flow will be based on commercial CAD tools and on the existing Balsa framework with extensions to mixed synchronous-asynchronous systems. The main idea is to integrate the Balsa language and tools in a system level design environment, where Balsa will be seen just as any other language, in order to allow mixed descriptions of synchronous and asynchronous circuits. Consequently, we will generate a system level design tool that is able to handle IP blocks referring to Balsa, Verilog, VHDL and SystemC specifications with an open plug-in interface to easily accept new languages and tool flows.

Our GALS design flow will be based on an open format for mixed synchronous-asynchronous IPs in order to consolidate asynchronous IPs dissemination and re-use. The IP format will be able to describe hardware/software entities at multiple levels of abstraction in multiple languages (SystemC, C, Verilog, VHDL, Balsa, etc.), with both synchronous and asynchronous interfaces.

We will establish a library of the important GALS components scalable to different applications. This library of GALS interface IPs should enable a plug-and-play type of approach when designing a system with a heterogeneous mixture of synchronous and asynchronous IPs.

It is planned to investigate the possibilities for lowering EMI and power with a GALS methodology. We plan to build an abstract model of the GALS circuit and generate the optimal algorithms for reducing the EMI. Additionally, the developed EMI reduction algorithms will be evaluated theoretically and in practice. We will investigate application of dynamic voltage and frequency scaling in conjunction with GALS in order to reduce power in comparison with standard synchronous low-power solutions.

The project also intends to deploy the power-aware nature of GALS technology to bring NoC architectures to maturity. GALS-based NoCs would allow the synchronous design of network nodes at their optimum clock frequency, while facilitating asynchronous communication between modules.

The project intends to consolidate GALS-NoCs as the enabling technology for widespread adoption of network-centric architectures for highly integrated MPSoC platforms in the nanometer regime.

Key Issues Practical IC implementations will be the key issue of the GALAXY project, as it will provide the best way to evaluate the developed GALS solutions and compare them against traditional circuits. We plan to have two separate ASIC implementation runs within the GALAXY project.

The first chip will be specifically designed to be a test chip containing structures to evaluate GALS components. This chip will be used to evaluate the advantages of GALS-based design in reducing power consumption, reducing EMI, and improving process variation tolerance.

Finally, we plan to build a complex target system using both a standard synchronous CMOS design flow and the GALS design flow developed in this project in a cutting edge 40 nm CMOS process. Selecting a suitable target platform for the second design is important. Since wireless communication is an application domain which is gaining more and more popularity and which poses significant technical challenges to system designers (performance- and power-wise), and since several group members have prior experience in this field, we will consider target platforms from this field. For example, one candidate will be an accelerator for an OFDM baseband processor with data rates up to 1 Gbps for communication systems in 60 GHz range which is currently under development in IHP.

Expected Impact

The realization of the ambitious goals defined by the project will result in improved design-to-market time, fewer design iterations and finally in a lower cost of the system design process. The GALAXY project has ambition to further confirm the leadership of Europe in a GALS system-on-chip design and CAD support. This leadership is already established with previous realization of complex asynchronous and GALS demonstrators and tools. The involvement of our industrial partners will guarantee the success of the project and the impact to the embedded system design methodology and practice.

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At A Glance: INTERESTED

INTER-operable Embedded Systems Toolchain for Enhanced rapid Design,

prototyping and code generation

Project Coordinator: Name: Eric Bantegnie Institution: Esterel Technologies Email: [email protected]

Project website: www.interested-ip.eu

Partners:ESTEREL Technologies SA (France) AbsInt Angewandte Informatik (Germany) TTTech Computertechnik AG (Austria) Evidence S.r.l. (Italy) Symtavision GmbH. (Germany) UNIS, spol. s r.o.(Czech republic) Artisan Software Tools Ltd (United Kingdom) Sysgo AG (Germany) Airbus SAS (France) Magneti Marelli Powertrain SpA (Italy) Commissariat à l’Energie Atomique (France) Thales SA (France) Siemens AG (Germany)

Duration: 36 months Start: 2008.01.01Total Cost: 7364057€ EC Contribution: 5388995€


Main Objectives

The INTERESTED project has been built to exactly match the goals defined within the Objective ICT-2007-3.3b (“Suites of interoperable design tools for rapid design and prototyping”), namely creating a reference and open interoperable embedded systems tool-chain, fulfilling the needs of the industry for designing and prototyping embedded systems.

high tech innovative SMEs, as well as European Major Tool Users representing several industries that are both integrating massively embedded systems and contributing to the overall competitiveness of Europe: Aerospace, Automotive, Railway and Transportation and Energy.

INTERESTEDINTER-operable Embedded Systems Toolchain for Enhanced rapid Design, prototyping and code generation INTERESTED aims at realizing the first European-wide tool reference development ever, validated by Major Tool Users thru real life industrial validators, ensuring an integrated, lower cost, highly dependable, safe and efficient development process for the benefit of critical European industries)

KEYWORDS: refrence tool suite , interoperability, integration, safety and dependability of embedded systems.

INTERESTED will focus on delivering

and integrated embedded systems

toolchain

This project regroups a consortium of leading edge European embedded systems Tools Vendors, all being


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Technical approach

The method followed in the project is to:

� Integrate the requirements of Major Tool Users of embedded systems tools to realize a reference and open interoperable embedded systems tool-chain, having in mind a broad socio-economic benefit for the European citizens, the performance of Embedded Systems generating long term societal benefits such as increased aircraft and transportation safety, reduced fuel and energy consumption and competitiveness of key European industries.

� Cover the full scope of Embedded Systems and Software engineering disciplines, spanning:

o System and Application Software Design Modelling, Verification and Code Generation

o Networking and RTOS execution platforms, Hardware-Dependent Software verification and Code Generation

o Timing analysis and code execution verification

� Validate the use of the INTERESTED tool-chain on real-life demonstrators (the “Industrial Validators”) representing key application domains for European leading industries: Aerospace, Automotive, Railway and Transportation and Energy.

From a technical standpoint, the INTERESTED reference Tool-Chain will integrate, using standards-based integration and interoperability solutions the following tools:

� Architecture definition tools (UML/SysML tools from ARTISAN Software Tools as well as demonstrated interoperability with Open Source UML, SysML and AADL Modellers such as TOPCASED and Papyrus provided as interoperability demonstration case by Airbus and CEA (a convergence process is being initiated between these 2 tools and is funded outside of INTERESTED).

� Embedded GUI design tools (SCADE Display from Esterel Technologies),

� Application Software Design, Verification and Code Generation tools (SCADE Suite from Esterel Technologies),

� Hardware-Dependent Software Design and Code Generation tools (Processor Expert from UNIS)

� Networking Infrastructure support tools (FlexRay and TTP tools from TTTech)

� RTOS execution platforms (PikeOS from SYSGO as well as demonstrated interoperability with domain specific execution platform such as the OASIS environment from CEA)

� WCET and Stack Analysis Tools (aiT from ABSINT)

� Schedulability analysis tools (SymTA/S from Symtavision and RT-Druid from Evidence), as well as numerical precision analysis tools (Fluctuat from CEA)

Key Issues

Major Tool Users (AIRBUS, THALES, MAGNETI MARELLI, SIEMENS RAIL TRANSPORTATION and CEA) will bring their requirements for the Tool-Chain content, structuring, features, interoperability architecture and characteristics, as well as real-life demonstration cases for their use of relevant parts of the tool-chain and interoperability demonstration cases with in-house or open source tools. They will ensure, thru appropriate metrics defined during the progress and evaluation of the cost reduction target that the INTERESTED reference tool-chain will enable. Tool Vendors within the INTERESTED project have established a preliminary list of Integration Technical Business Cases for the integration of their tools, will review them against the Major Tool Users requirements and will ensure that all selected Integration Technical Business Cases specifications and developments are architected in an interoperable way with 3rd party tools, such interoperability being verified within the Industrial Validators.One Major Tool User (CEA), due to its mission, enjoying strong links with academics partners, will steer an Academic Advisory Board to make sure that innovative and proper advice from academic Networks of Excellence such as ARTIST2 are clearly taken into account.

Expected Impact

In summary, INTERESTED aims at realizing the first European-wide tool reference development environment ever, validated by Major Tool Users through real-life Industrial Validators, ensuring an integrated, lower cost, highly dependable, safe and efficient development process to the benefit of critical European industries. INTERESTED will thus contribute securing Europe’s competitiveness and independencein the critical Embedded Systems field.

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At A Glance: MADES

Model-based methods and tools for Avionics and surveillance embeddeD

SystEmS

Project Coordinator: Name: Alessandra Bagnato Institution: Txt e-solutions – Corporate Research Division Email: [email protected]

Project Technical Manager: Name: Andrey Sadovykh Institution: Softeam Email: [email protected]

Project website: www.mades-project.org

Partners:TXT e-solutions (IT) Softeam (FR) University of York (UK) Politecnico di Milano (IT) The Open Group (UK) EADS Deutschland GmbH (DE)

Duration: 30 monthsStart: 2010.02.01Total Cost: € 3623931EC Contribution: € 2450000

Contract Number: INFSO-ICT-FP7-248864

Main Objectives

The project covers all the phases of the development process: from design to code generation, validation and deployment. Design activities will exploit a dedicated language developed on top of the OMG standard MARTE (Modeling and Analysis of Real-time and Embedded systems), and foster the reuse of components by annotating them with properties and constraints to ease their selection and enforce overall consistency.

Code generation will address both conventional programming languages (e.g., C) and hardware description languages (e.g., VHDL), and will adopt compile-time virtualization techniques to smooth the impact of the diverse elements of modern hardware architectures and cope with their increasing complexity. All these aspects will be fully supported by prototype tools integrated in a single framework, and will be thoroughly validated on real-life case studies in the surveillance and avionic domains. The project also aims to develop a handbook to provide detailed guidelines on how to use MADES tools in the development of embedded systems and promote their adoption.

MADESModel-based methods and tools for Avionics and surveillance embeddeD SystEmS MADES aims to develop the elements of a full-fledged model-driven approach for the design, validation, simulation, and code generation of complex embedded systems to improve the current practice in the field.

KEYWORDS: Embedded Systems Design, Advanced Model-Driven Development.

MADES will focus on a full-fledged model-driven approach for

the design, validation, simulation, and code

generation for Avionics and surveillance

embeddeD SystEmS

Validation activities will comprise the verification of key properties of designed artifacts and of the transformations used throughout the development process, and also the closed-loop simulation of the entire system.


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Technical Approach

The MADES technical approach is based on the following:� Adapt and Develop Modelling Languages

and Tools for Co-Design of Embedded Systems in the Avionics/Surveillance Domain

� Develop Advanced Methods and Tools for Verification and Simulation for the Co-Design

� Develop Advanced Methods and Tools for Code and Hardware description Co-Generation

� Integrate developed MDE tools in a single framework for the seamless modelling, validation, and code generation

� Validate with Case Studies from the Avionics/Surveillance Domains

Error! Reference source not found. depicts a preliminary overview of the components to be developed in the project. All tools are plugged into the MADES framework based on Eclipse platform and its EMF based MDD Technologies. SOFTEAM’s CASE Tool implements dedicated MARTE extensions and is integrated with other tools. The Component Repository is used to store and locate generic UML Case Tools system components used for building embedded systems. The Verification and Simulation tools are integrated with the modeller and provide the validation features. The Traceability tool keeps track of changes happening during modelling and model transformations. The Software Code and HDL description generation is insured by Transformation and Generation engine.

GenericUML Case Tool

GenericUML Case Tool

HDL Description Generation

HDL Description Generation

Verification andSimulation

Verification andSimulation

<<Embedded System Designer>>

<<Embedded SystemTester>>

MADES Integration framework –Eclipse and MDD Technologies Based on EMF

Componentsrepository

Componentsrepository

Objecteering:MARTE, UMLObjecteering:MARTE, UML

<<EmbeddVerification

Transformationand Generationwith Platform Virtualization

Transformationand Generationwith Platform Virtualization

TraceabilityTraceability

Software Code Generation

Software Code Generation

Figure 1 MADES Components Integration

Key Issues

The ideas of MADES are directly based on the needs for increased help demanded by developers and industry in embedded system design. As the systems that employ embedded software becomes more complex, they tend to contain more errors, and it becomes more relevant to provide tools to aid the developers to overcome the increased difficulties.The project will give a key help in this direction with its development efforts specifically dedicated to RTES (Real Time Embedded Systems). Major players in the Avionics and Surveillance Embedded System domain (Txt e-solutions and EADS) will provide key requirements to achieve projects objectives.

Expected Impact

MADES expects to achieve impact through:

Increasing productivity of embedded system development. The Advanced Model Driven Architecture MADES Tools and Methodologies targets a significant reduction in embedded system development time. The MADES approach is intended to significantly reduce the efforts required in all the embedded system development phases, from modelling by composition to automated verification and generation of code and HDL. The impact will be particularly proved in the MADES selected test cases where the MDA processes already in place would be very much benefiting of the proposed technology.

Supporting emergence and growth of new companies that supply design tools and associated software. The project will rely on open models and standard will be easily usable by European SMEs that are already offering innovative product and services for embedded system design. The project will produce the MADES Approach guide to help and lead in this direction.

Improving competitiveness of European companies that rely on the design and integration of embedded systems. The project will improve competitiveness of European companies that rely on the design and integration of embedded systems in their products by reducing design costs and time to market creating tools and methodologies specifically targeted to them.

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At A Glance: MADNESS

Methods for predictAble Design of heterogeneous Embedded Systems with

adaptivity and reliability Support

Project Coordinator: Name: Luigi Raffo Institution: University of Cagliari (Italy) Email: [email protected] [email protected]

Project website: http://www.madnessproject.org

Partners:Università degli Studi di Cagliari (Italy) Università della Svizzera italiana (Switzerland) Silicon Hive BV (The Netherlands) Infineon Technologies AG (Germany) Universiteit van Amsterdam (The Netherlands) Universiteit Leiden (The Netherlands) Informatik Centrum Dortmund (Germany) Lantiq Deutschland GmbH (Germany)

Duration: 36 months Start: 2010.01.01Total Cost: 2.92 M€ EC Contribution: 1.95 M€


Main Objectives

The main goal of the project is to define innovative methodologies for system-level design, able to guide designers and researchers to the optimal composition of embedded MPSoC architecture, according to the requirements and the features of a given target application field. The proposed approach will tackle the new challenges, related to both architecture and design methodologies, arising with the technology scaling, the system reliability and the ever-growing computational needs of modern applications. The proposed methodologies will extend the classic concept of design space exploration to:

� Improve design predictability, bridging the so called “implementation gap”, i.e. the gap between the results that can be predicted during the system-level design phase and those eventually obtained after the on-silicon implementation.

� Support adaptive runtime management of the architecture, considering, while tailoring the architecture, new metrics posed by novel dynamic strategies and advanced support for communication issues that will be defined.

MADNESSMethods for predictAble Design of heterogeNeous Embedded Systems with adaptivity and reliability Support The MADNESS project aims at the definition of innovative system-level design methodologies for MPSoC embedded systems, extending the classic concept of design space exploration to cope with high heterogeneity, technology scaling, system reliability and multi-application domains. KEYWORDS: system-level design, design space exploration, technology awareness, heterogeneity, fault tolerance, adaptivity.

MADNESS will focus on

improvingEmbedded

Systems design predictability,

considering new features, such as

adaptivity and fault tolerance

� Consider, in addition to traditional metrics (such as cost, performance and powerconsumption), continued availability of service, taking into account fault resilience as one of the optimization factors to be satisfied.


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Technical Approach

The project proposes an extended system-level design space exploration approach. The DSE is seen as an iterative process operating on a library of heterogeneous IP cores, exposing a large number of degrees of freedom, as typical for industrial-strength components.

In order to improve the design predictability, the project will introduce a specific layer for rapid and accurate emulation, to be exploited for architectural evaluation inside the DSE process. In detail, it will allow to take into account, during system-level decision phase, the impact of the variables related with a prospective physical implementation of the architecture (e.g. wiring capacitances and delay, 2D floorplanning). Moreover, this layer will provide the capability of performing, when needed during the optimization process, a detailed estimation of the performance and the power consumption of a candidate architecture, relying on an FPGA-based environment for on-hardware prototyping. The power consumption evaluation will be obtained annotating the FPGA emulation results with energy values estimated in a “technology-aware” manner. Novel design methodologies for fault tolerance and for adaptive runtime management will be proposed. These methodologies will act at different levels of abstraction and on different phases of the design flow. Their introduction will influence the system-level design algorithm, since it will require new metrics to be taken into account by the optimization process. Besides that, it will require the development of new dedicated hardware support and, thus, new IPs are likely to be developed.

Key Issues

Modern embedded systems usually integrate components provided by different parties, very often yielding a high level of design complexity to be handled by the designer. Different computational tasks to be executed often offer different kinds and degrees of parallelism, thus optimally fitting to a specific kind of processing elements. In order to improve the overall productivity, an effective system-level design should be handled in a novel manner, taking into account, at its early stages, a bigger number of variables as well as more complex IP cores inside the design space available to the designer. Moreover, the efficient “static approach” to the design of embedded processors needs to be extended to MPSoC design, and in certain cases needs to include dynamic behaviour. This is particularly the case when multiple applications are executed at the same time, unpredictably interfering with each other at runtime and posing the need for the assurance of a given level of Quality of Service. In addition, given the increasing complexity of the systems, a certain degree of fault tolerance must be guaranteed, but constraints presented by embedded systems design make approaches involving massive redundancy hardly adoptable. Both these issues require the support inside modern MPSoCs of a certain degree of adaptivity.

To take meaningful system-level decisions, moreover, the designer must deal with several problems related to modern technology nodes and rely on accurate estimations of the hardware costs of each candidate architectural solution.

Expected Impact

The MADNESS project will deliver advanced technology and specific tools for strengthening European excellence in the design of multi-processor heterogeneous embedded systems. Here is a brief list of the expected impacts targeted by the MADNESS project. � Significantly increased productivity of embedded

system development. � Improved competitiveness of European

companies that rely on the design and integration of embedded systems in their products by reducing design costs and time to market.

� Emergence and growth of new companies that supply design tools and associated software.

� Stimulated high-tech European companies, in particular SMEs, which offer innovative products and services for embedded systems design.

Reinforced European scientific and technological leadership in the design of complex embedded systems.

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At A Glance: MEDEIA

Model-Driven Embedded Systems Design Environment for the Industrial Automation

Sector

Project Coordinator: Name: Dr. Thomas Strasser Institution: PROFACTOR GmbH Email: [email protected]

Project website: www.medeia.eu

Partners:Vienna University of Technology (Austria) Politecnico di Milano (Italy) University of Applied Sciences South Switzerland (Switzerland) logi.cals Austria kirchner SOFT GmbH (Austria) Machining Centers Manufacturing S.p.A (Italy) SCHUNK GmbH & Co. KG (Germany) Electricité de France S.A (France) O3NEIDA Europe (Belgium)

Duration: 36 months Start: 2008.01.01Total Cost: € 2.84M EC Contribution: € 2M


Main Objectives

As the level of automation and system complexity in factories and plants increases steadily, system engineering becomes progressively more difficult and less-productive. A new approach to achieving high degrees of functionality through improved interoperability of subsystems is under way within MEDEIA.The focus of the MEDEIA project is on “automation objects” or “automation components” as the basis for developing a model-based embedded systems design environment. The MEDEIA project’s objective is a radical improvement in productivity for the development of embedded control systems within the industrial automation sector.

1. A formal framework for model-driven component-based development of embedded control

2. An easily – understandable modelling method designed for use by domain experts

3. An integrated modelling of diagnostics

4. The integrated simulation and verification of systems design

5. An automatic, embedded, and platform specific code-generation for the deployment of control software to heterogeneous automation hardware

6. A series of proof–of-concept demonstrations on real-world applications by project partners in the application domain of robotics, manufacturing, power generation and automatic packaging

The development of these elements will produce a pioneering methodology and a prototypical design and engineering framework for embedded system design, which will enable the industrial automation industry to reduce system design time and costs for the development of complex control systems.

MEDEIAModel-Driven Embedded Systems Design Environment for the Industrial Automation Sector MEDEIA will methodically target, research and develop a formal framework supporting a new multi-domain modelling method to fulfil the increasing engineering needs in the industrial automation sector.KEYWORDS: Automation components, behaviour and interface description, component based embedded systems design, model-driven architecture

MEDEIA will focus on the development of a multi-domain model-

driven embedded systems design

approach for in the industrial automation

sector

The project goal of reducing system design time by 25% will be achieved through the systematic development ofthe following elements:


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Technical Approach

The MEDEIA design methodology is based on the so-called Automation Components (ACs) which are in general a combination of embedded hard- & software. An AC contains the general model of its functionality and its interface for interacting with other components as depicted in the figure below. The starting point of each engineering flow is the definition/specification of the system requirements. The MEDEIA design flow accepts the functional and non-functional specification of a plant (e.g. for manufacturing, robotics or power generation systems) as the initial starting point. The functional structure is realized through systems or components formed, in turn, from a combination of sub-systems and sub-sub-systems. This orientation to design reflects MEDEIA’s strong compositional approach which greatly productivity in de signing and building machines and plants from the mechanical/electrical point of view significantly. In contrast to the functional structure of a plant, the state-of-the-art design process for the control system is usually not compliant with this point of view. Structures defined in embedded system disciplines like control hard- & software, as well as communication, are based rather on technical reasons as opposed to functional assignment. The MEDEIA approach will close this gap between the mechanical/electrical engineering and the embedded control engineering approaches. The first step within the design flow is the specification of a rough plant architecture and ACs. Additionally, existing ACs or already available implementations of ACs can be included. By continuous refinement, adaptation to new requirements, splitting up to sub-problems/components and composition of ACs, the MEDEIA design flow becomes highly flexible and integrative at each level of the plant architecture. Independently of the current state of the specification of an AC, the AC model enables execution of the AC within a simulation framework. Therefore, simulation of AC models together with concrete implementations enables a new kind of hardware-in-the-loop execution: at any level of the plant architecture as well as for mixed up environments of existing and simulated ACs, the execution of parts of the system or the overall system will be possible. This feature results in much reduced development cycles, early testing and improved dependability of single components as well as of the overall plant.

Key Issues

The current situation for the design of automation and control systems is characterized by a huge variety of different approaches in both, the specification and implementation of plants. When different end-users, each of whom has expressed their requirements in different forms, have to interact, there exists currently very little support in automated workflows or even in the interoperability of different software tools implementing the combined set of specifications defined in different forms. The key issue of the MEDEIA approach for bridging the gap between the different users and their special way of specifying and implementing is to put a common element, the Automation Component, in between of the specification and implementation elements of a plant automation system implementation.

Expected Impact

The MEDEIA method will support the automation industry to become more competitive by fostering new features that are seen by industry as vital for realisation and exploitation of innovative products within Europe. The proposed design method and formal framework allows a rapid design and engineering of advanced automation application solutions within a reasonable time and thus overcomes significant disadvantages of state-of-art approaches. This is crucial since pioneering high-tech products initially target premium-price sectors before reaching mass markets. Thus on a wider scope the project contributes strategically to innovations and leads to a more competitive industrial portfolio. In the 3-5 year range, the first products will appear that have been designed using the novel MEDEIA technology. First challenging fields of applications are likely to include: � Manufacturing and production plants, � Complex and advanced robotic systems, � Power generation, distribution and supply systems,

as well as � Logistic systems.

MEDEIA technology from industrial partners will be developed for application in the fields above.

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At A Glance: MNEMEE

Memory maNagEMEnt technology for adaptive and efficient design of

Embedded systems

Project Coordinator: Name: Peter Lemmens Institution: IMEC Email: [email protected]

Project Technical Manager: Name: Dr. Stelianos Mamagkakis Institution: IMEC Email: [email protected]

Project website: www.mnemee.org

Partners:Thales (France) IntraCom Telecom (Greece) Informatik Centre Dortmund (Germany) Technische Universiteit Eindhoven (NL) ICCS (Greece) IMEC (Belgium)

Duration: 36 months Start: January 1st 2008Effort: 424 Person monthsTotal Cost: 4.680.784€ EC Contribution: 2.950.000 €

Contract Number: IST-216224

Main Objectives

The “MNEMEE” project will provide a novel solution for mapping applications cost-efficiently to the memory hierarchy of any MPSoC platform without significant optimization of the initial source code. The activity is aiming at the data (statically and dynamically allocated) management between the state-of-the-art optimizations at the application functionality and the compiler design layer.

Scope

The theme of intelligent ubiquitous devices will dominate future embedded system designs and speed up the integration of multimedia and communication applications, thus creating very complex, dynamic source code. Today it is increasingly impossible for designers to map applications cost-efficiently to any platform without significant optimization of the initial source code.The MNEMEE project will address this key challenge by introducing an innovative supplementary source-to-source optimization design layer for data management between the state-of-the-art optimizations at the application functionality and the compiler design layer.

Innovation

The project proposal consists of multi-objective explorations that allow trade-offs which designers highly need to rightly position their product in the huge search space. A combination of design-time and run-time techniques to boost the cost-efficiency and performance. Automated optimizations that are applied once to reduce design effort and can handle very complex code. No existing integrated framework allows this and ongoing projects do not address it sufficiently.

MNEMEEMemory maNagEMEnt technology for adaptive and efficient design of Embedded systems Memory management technology for adaptive and efficient design of embedded systems and Variability tolerant System-on-a-chip Design in More-Moore Technologies KEYWORDS: Embeded systems design, memory optimization, design automation tool

MNEMEE's Proposed Solution

• Multi-objective exploration that enable trade-offs

• Combination of design-time and run-time

optimization methodologies• Automation tools will

support the methodologies

This FP7 funded project is the base for a collaboration between major industrial players in this field, research institutes and academic partners: Thales, IntraCom Telecom, IMEC, ICD, ICCS and Technische Universiteit Eindhoven.


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Focus

The key objective of the project lies in the efficient data access and memory storage of both dynamically and statically allocated data and their assignment on the memory hierarchy. The few existing source-to-source approaches existing today only deal with the static manifest arrays and simple code. In contrast, MNEMEE will deliver all the necessary design methodologies, heuristics and prototype tools to enable the fast exploration of the huge dynamic and static design space.

Technological challenges

� Provide a framework for source-to-source optimization methodologies, which targets both statically and dynamically allocated data.

� Introduce a novel source-to-source optimization design layer.

� Analyze the embedded software applications and highlight the source-to-source optimization opportunities.

� Develop a set of prototype tools.

� Provide data memory-hierarchy aware assignment and scheduling methodologies.

Progress beyond state-of-the-art

The below Figure shows the relation between the workpackages. The first workpackage delivers data analysis, memory hierarchy requirements, scenario identification and specifications for the embedded software applications. The second, third and fourth workpackages provide the source-to-source optimizations. The fifth workpackage provides the demonstrators for the MNEMEE optimization.

Project Approach

The above Figure shows the relation between the partners and their role in the project. Workpackage 1: Data analysis, specifications and

scenario identification for embedded software applications.

Workpackage 2: Source-to-source optimizations of dynamically allocated data mapping on MPSoC platforms.

Workpackage 3: Source-to-source optimizations of statically allocated data mapping on MPSoC platforms.

Workpackage 4: Memory hierarchy aware optimization techniques

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MOBY-D ICModel-based synthesis of digital electronic circuits for embedded control The MOBY-DIC project will research and develop a unique paradigm and supporting tool chain for the design of embedded control systems, based on modelling of the physical process and integrated design of both control algorithms and embedded circuits.KEYWORDS: Embedded control systems, circuit design, piecewise affine functions, optimal control, virtual sensors.

Main Objectives MOBY-DIC has identified the following project objectives to face the posed research challenges: O.1 Define a novel PWA (PieceWise-Affine) canonical for-malism that unifies the control and circuit views on embedded control design, and develop analysis, complexity reduction and controller and circuit design methodologies for the embedded electronics, starting from mathematical models of the embedding system.

O.2 Create a complete integrated tool chain of software modules to support the new analysis and design methodologies.

O.3 Provide a proof-of-concept of the new approach by addressing three challenging industrial case studies in the automotive domain, which require the design of embedded controllers and virtual sensors: � monitoring batteries for hybrid vehicles � design of a virtual smart full gyro sensor for

vehicle dynamics applications � Stop-&-Go Adaptive Cruise Control, a

functionality already available in some upper-class vehicles, which automatically adapts the vehicle’s speed depending on a predecessor’s behaviour, steering the throttle as well as the brake system.

The developed methodologies and tools are generic in nature with the consequence that they are usable in any application domain such as industrial and electronic automation, robotics, transportation, aerospace, health care, etc.


At A Glance: MOBY-DIC

Model-based synthesis of digital electronic circuits for embedded control

Project Coordinator: Name: Marco Storace Institution: Università di Genova Email: [email protected]

Project website: www.mobydic-project.eu

Partners:Università degli Studi di Genova – UNIGE (Italy)Technische Universiteit Eindhoven – TU/e (Netherlands) Universidad de Sevilla – USE-IMSE (Spain) Università degli Studi di Trento – UNITN (Italy) Ford Forschungszentrum Aachen GmbH – FFA (Germany) ON Semiconductor Belgium BVBA – ON-SEMI (Belgium)

Duration: 36 monthsStart: 2009.12.01Total Cost: € 3,209,203.00EC Contribution: € 2,140,000.00


MOBY-DIC will develop a unique

paradigm and supporting tool

chain for the design of embedded

control systems

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Technical Approach

The MOBY-DIC project targets a step-by-step development of the methodology and contains four scientific work packages (WP). The WP’s are organized in such a way to eliminate bottlenecks and difficulties. The main steps are: 1. Selection of the canonical PWA form suitable for

both control and circuit implementation purposes. This step is at the heart of the project, being the trait d'union. It forms the bridge between the control world and the circuit world (WP2).

2. Development of analysis and design methodologies and a software toolbox for the synthesis of circuit-oriented PWA control systems and application of them to three challenging automotive case studies (WPs 3 and 5).

3. Creation of the circuit synthesis methodologies in two phases: identification of the best circuit structures for the implementation of the controllers and observers in PWA canonical form obtained from step 2 above (phase 1) and definition of an automated circuit design procedure (phase 2) (WPs 3 and 4).

4. Validation of the proposed approach through the design of circuits implementing the control systems in three case studies. The results of the implemented circuits will be compared with those concerning standard solutions of the considered control systems (WPs 4 and 5).

There are two further work packages: WP5 concerns the validation of the whole embedded system (sensor, control, actuator) in the three case studies; WP6 will take care of dissemination and exploitation of the project results to the scientific community and industries of high importance.

Key Issues

On the theoretical level, MOBY-DIC aims at developing analysis and synthesis methods for PWA controllers and estimators that can trade-off performance properties of the overall system and the implementation complexity of the resulting digital circuits. MOBY-DIC proposes a circuit-oriented design flow based on the PWA paradigm that, starting from a model description, ends with an (even integrated) embedded system. The availability of such a design flow will actually spur the application of PWA controllers and virtual sensors for many applications and will alleviate the obstructions in their usage as caused by the decoupled designs of the (mathematical) control law and of the circuit. In other words, MOBY-DIC will provide circuit-aware embedded control design and control-aware embedded circuit design, by employing a PWA modelling paradigm, which provides a flexible formalism, efficient control design tools, and efficient implementation in electronic circuits.

Expected Impact

MOBY-DIC is expected to impact all major goals of the workprogramme, in particular: � Significantly increased productivity of embedded

system development. � Improved competitiveness of European companies

that rely on the design and integration of embedded systems in their products by reducing design costs and time to market.

� Emergence and growth of new companies that supply design tools and associated software.

� Reinforced European scientific and technological leadership in the design of complex embedded systems.

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At a Glance: MOGENTES

MOdel-based GENeration of efficient Tests for Embedded Systems

Project Coordinator: Name: Dr. Manfred Gruber Institution: Austrian Research Centers - ARC Email: [email protected]

Project Technical Manager: Name: Dr. Wolfgang Herzner Institution: Austrian Research Centers - ARC Email: [email protected]

Project website: www.MOGENTES.eu

Partners:Austrian Research Centers GmbH - ARC (AT) Budapest Univ. of Technology and Economics (HU) Ford Forschungszentrum Aachen GmbH (DE) Swiss Federal Institute of Technology Zurich (CH) Graz University of Technology (AT) Prolan Irányítástechnikai ZRT (HU) Prover Technology AB (SE) SP Technical Research Institute of Sweden (SE) Thales Rail Signalling Solutions GmbH (AT) Re:Lab S.R.L. (IT)

Duration: 36 months Start: 2008.01.01Total Cost: € 4,4 Mio EC Contribution: € 3,1Mio


MOGENTESMOdel-based GENeration of efficient Tests for Embedded Systems MOGENTES aims at significantly enhancing testing and verification of dependable embedded systems by generation of efficient test case KEYWORDS: Model-based test case generation (MBTCG), Dependable embedded systems (DES), Fault modelling, Test coverage metrics


Main Objectives

The goal of MOGENTES is to significantly enhance testing and verification of dependable embedded systems by means of automated generation of efficient test cases relying on the development of new approaches as well as innovative integration of state-of-the-art techniques. In particular, MOGENTES aims at the application of these technologies in large industrial systems of automotive, railway control, and off-highway vehicles domains to achieve a significant cost reduction.

While formal verification has been applied success-fully for systems of limited size, testing is still the primary though expensive alternative. Therefore, MOGENTES has the objectives: � To reduce testing effort by at least 20%.

� To generate efficient test cases from system and fault models, for both functional and non-functional system properties of new and existing embedded systems.

� To establish a framework for integration of involved tools, including model transformations, to prepare inputs for model checkers etc., which can be easily used by domain experts.

� To provide traceability of requirements and match them to test analysis results.

� To foster application of automated testing to satisfy functional safety standards requirements.

� In general, to increase the confidence in safety-relevant embedded systems by improving their testing and proving their conformance to safety standards.

MOGENTES will focus on

automated generation of

efficient test cases, relying on

development of new approaches as well as innovative

integration of state-of-the-art

techniques.

Today, embedded computer systems become increasingly integrated in safety-relevant systems such as vehicles, medical equipment, or industrial or public control systems. Evidently, any possible mea-sure has to be taken to ensure the dependability of such systems, from early planning and design to final installation and maintenance.

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Technical Approach

These objectives shall be achieved with the following concepts. � Define common modelling languages and

semantics (meta-models), with UML as primary candidate, such that the domain specific requirements of the demonstrators can be reflected, and the (partial) models of the demonstrators can be mapped to this language.

� Develop a test theory that defines the con-formance relation between the model and the implementation, and the notion of success and failure of a test case.

� Define fault models (for software as well as hard-ware) and extend the modelling languages to allow the integration of the representation of faults into the (application) models.

� Define new coverage criteria under consideration of minimal cut sets (i.e., combinations of faults causing a safety requirement violation), fault injec-tion, mutation testing, and safety aspects, and use existing TCG techniques to generate efficient test cases that achieve this coverage.

� Use model-based fault injection (MBFI) to extend models for automatically calculating minimal cut sets

� Validate the defined fault models (and thus the generated test cases) with physical fault injection.

� Use (bounded) model checking techniques to generate stress test scenarios.

� Provide semantics-aware transformations from system models to inputs of specific tools, e.g. to enable interaction of generated models with existing simulation environments for allowing evaluation of model coverage.

Key Issues

Following obstacles are observed which still today hamper broad application of model-based test generation in industry: � For existing systems, domain-specific formal

notations ("meta-models"), in which their models can be defined, are not always available.

� In general, formal tools are still difficult to use, they often need expert knowledge due to their own terminology and the specific semantics of the applied formalisms.

� For real embedded systems, applicability is still limited due to their complexity and size.

� Formal models used in the development focus on specification of fault-free behaviour, and the notion of faults and fault effects are rarely included in the models.

� Accordingly, means for dependability, e.g. fault tolerance, are poorly addressed by existing tools.

Expected Impact

MOGENTES will contribute to both maintaining the competitiveness of Europe's industry by helping to reduce validation and verification costs, and to strengthen the increasing test tools and services branch. In general, MOGENTES will increase knowledge and develop new techniques and tools in the area of verification and validation of dependable embedded systems which can be applied in model-based development processes also by non-experts in formal methods.

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MULTICUBE

Project Coordinator: Name: Cristina Silvano Institution: Politecnico di MilanoEmail: [email protected]

Project website: www.multicube.eu

Partners:Politecnico di Milano (Italy) Design of Systems on Silicon – DS2 (Spain) STMicroelectronics (Italy) IMEC (Belgium) ESTECO (Italy) University of Lugano - ALaRI (Switzerland) University of Cantabria (Spain) STMicroelectronics Beijing (China) Institute of Computing Technology – Chinese Academy of Sciences (China)

Duration: 30 months Start: 2008.01.01Total Cost: € 3 081 383 EC Contribution: € 2 098 338


MULTICUBEMulti-Objective Design Space Exploration Of Multi-Processor SoC Architectures For Embedded Multimedia Applications KEYWORDS: Multi-Objective Design Space Exploration, Multi-processor System-on-Chip, Architecture Optimization, Performance and Power Estimation, Platform-based Design, Embedded Systems, Multimedia Applications.


Main Objectives

Many point tools exist to optimize particular aspects of embedded systems. However, an overall design space exploration framework is needed to combine all the decisions into a global search space, and a common interface to the optimization and evaluation tools. The MULTICUBE project focuses on the definition of an automatic multi-objective Design Space Exploration (DSE) framework to be used to tune the System-on-Chip architecture for the target application evaluating a set of metrics (e.g. energy, latency, throughput, bandwidth, QoS, etc.) for the next generation of embedded multimedia platforms. This overall objective is two-fold. From one side, the MULTICUBE project will define an automatic multi-objective DSE framework to find design alternatives that best meet system constraints and cost criteria, strongly dependent on the target application, but also to restrict the search space to crucial parameters to enable an efficient exploration. In the developed DSE framework, a set of heuristic optimization algorithms must be defined to reduce the overall exploration time by computing an approximated Pareto set of configurations with respect to the selected figures of merit.

From the other side, the MULTICUBE project will define a run-time DSE framework based on the applications of the results of the static multi-objective design exploration to optimize the run-time allocation and scheduling of different application tasks. The design exploration flow results in a Pareto-optimal set of design alternatives with different speed, energy, memory and communication bandwidth parameters. This information can be used at run-time by the operation system to make an informed decision about how the resources should be distributed over different tasks running on the multi-processor system on-chip. This resource distribution cannot be performed during the design exploration itself, since it depends on which tasks are active at a particular point in time.

MULTICUBE will focus on multi-

objective design space exploration for embedded System-

on-Chiparchitectures

Once the approximated Pareto set has been built, the designer can quickly select the best system configuration satisfying the constraints.

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Technical Approach

The goal of MULTICUBE is to cover the gap between the system-level specification and the definition of the optimal application-specific architecture. MULTICUBE activities are driven by the idea to cover this gap by building a stack of tools and accurate methodologies directly targeted to specific multiprocessor SoC based on Network on Chip architectures. In the MULTICUBE design flow, the specifications of the target architectures and applications will be provided as inputs to the design flow. A SystemC-based multi-level modeling methodology for multiprocessors will be developed. Once received the target architecture as input, we will provide to the next step the system model to evaluate different architectural alternatives in terms of metrics. Then, the Design Space Exploration framework will be defined to sail over architectural solutions following several heuristic optimization algorithms. This step is implemented as an optimization loop, where the selected architecture instance generated by the DSE framework is given back to the estimation framework for the metrics evaluation. The tool integration phase in MULTICUBE will be performed to implement an automatic system optimization engine to generate, for the target MPSoC architecture, either the best architectural alternative (if the exploration is done statically) or the best tasks scheduling and allocation solution (if the exploration is done at run-time).

Key Issues

� Increased productivity of system development through a fast, reliable DSE process allowing finding an optimized solution in a short time. DSE will be performed at system-level, thus avoiding costly, low-level analysis steps (i.e. ISS simulations).

� Improved competitiveness of European companies that rely on the design and integration of embedded systems in their products by reducing costs and time to market.

� Stimulate high-tech European SMEs (such as ESTECO) that offers general-purpose innovative design solutions and tools to apply them for embedded systems design.

� Reinforced European scientific and technological leadership in the engineering of complex systems both at the industry side (STM as a large company and DS2 as a SME) and the academic and research side (IMEC, Politecnico di Milano, ALaRI, University of Cantabria and ICT).

Expected Impact

The design methodology will be implemented at system-level in a set of open-source and proprietary EDA tools to guarantee a large exploitation of the results of the MULTICUBE project in the embedded system design community. The overall goal is to support the competitiveness of European industries by optimizing embedded HW/SW systems while reducing the design time and costs. To ensure a wide applicability of the proposed DSE framework, the MULTICUBE project is strongly industry-driven. Two European industrial partners (STMicro-electronics Italy and DS2) and STMicroelectronics China will define the requirements of the design tools and validate step-by-step the results of the exploration tools to design a set of target industrial applications. The integration of design tools and the commercial exploitation of the tools will be done by an European SME, ESTECO. ALaRI will be mainly in charge of the dissemination and exploitation activities. The research and technological development will mainly be done by IMEC, Politecnico di Milano, University of Cantabria and the Institute of Computing Technology – Chinese Academy of Sciences.

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At A Glance: PREDATOR

DESIGN FOR PREDICTABILITY AND EFFICIENCY

Project Coordinator: Name: Prof. Dr. Reinhard Wilhelm Institution: Universität des Saarlandes Email: [email protected]

Project Technical Manager: Name: Prof. Dr. Reinhard Wilhelm Institution: Universität des Saarlandes Email: [email protected]

Project website: http://www.predator-project.eu/

Partners:Universität des Saarlandes (Germany) Eidgenössische Technische Hochschule Zürich (Schweiz) Universität Dortmund (Germany) Alma Mater Studiorum – Università di Bologna (Italy)Scuola Superiore di Studi Universitari è di Perfezionamento Sant’ Anna (Italy) ABSINT Angewandte Informatik GmbH (Germany) AIRBUS France SAS (France) Robert Bosch GmbH (Germany)

Duration: 36 months Start: 2008-02-01Total Cost: 3.926.305,20€ EC Contribution: 2.799.990,80€


PREDATORDesign for Predictability and Efficiency The PREDATOR project is concerned with the (worst-case) predictability and the (average-case) performance of embedded systems. The efficiency requirements comprise performance, resource utilisation, and power consumption. The considered systems typically occur in the aeronautics and automotive industries, in multimedia and industrial automation. KEYWORDS: Predictability, efficiency, average-case performance, computer system design


Main Objectives

Coordinated by the Compiler Design Lab of Universität des Saarlandes, a leading academic research group in timing analysis of hard real-time systems, and steered by Airbus France SAS and Robert Bosch GmbH, two key industrial players in safety-critical industries, PREDATOR aims at:

� improving the design and development methods for safety-critical embedded systems

� developing tools that support these development methods

� developing architectural concepts that support the derivation of timing guarantees for hard real-time systems

� providing architectural platforms that exhibit the desired predictability properties

The involved industrial partners will pose design challenges based on experience in the design of time-critical embedded systems. These challenges will be taken up by the academic consortium members. Prototype architectures, design methods and analysis tools will be developed to solve the challenges.

Each technique proposed in the project will be evaluated by measuring the reduction in the overestimation with respect to the case in which that technique is not used. Efficiency of new designs will be measured by means of simulation and profiling.

PREDATOR will develop a new methodology,

Design-for-Predictability leading to embedded systems with good

combinations of predictability and

performance.

The ultimate goal of the project is the reduction of the remaining uncertainty of real-time system behaviour and the reduction of the penalties to pay for this uncertainty.

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Technical Approach

Synergetic Development of Tools with Design

Predictability requires offline analysis of whole hardware/software systems. Thus, design and implementation methods need to be considered in terms of analysis complexity and precision. It is necessary to regard analyzability and design as a single entity. The design methodology envisaged by the PREDATOR consortium aims at improving the methods for predicting system behaviour. Two orthogonal ways to improve the predictability of embedded systems are the following: 1. Reducing uncertainty by improving analysability

and

2. Influencing design and implementation concepts to reduce penalties.

Basic questions about the relation between analysis and design will be clarified and the appropriate combination of design methods and analysis methods will be identified aiming at: � Identifying and subsequently eliminating

concepts endangering predictability, which have no significant influence on performance.

� Identifying alternative concepts to currently used ones and their implications with regard to predictability, performance, complexity and cost.

WCET Estimation and Overrun Handling

More relaxed guarantees will be considered, which increase resource efficiency, and robust scheduling algorithms as well as overload management techniques to tolerate them. Interrupt handling will be integrated into the scheduling decisions to account for both I/O and task timing requirements. Feedback-based resource reservation schemes and adaptive scheduling will be investigated to enable the system to react to unpredictable changes and cope with dynamic environments. An important point will be to identify the inter-dependencies between design choices on the different layers and in particular between the layers.

Resource-Aware Abstraction

This design concept would bound the access costs to resources on the one hand and export information about resource usage on the other hand. Component models are needed that expose resource demand and guarantees instead of abstracting them away. As a result, there is no distinction between functional and non-functional properties anymore as both system aspects need to be considered likewise. This new approach can be considered as a paradigm shift in component-based design. Pivotal questions related to this topic are whether

� the current layering is suited for time-predictability and efficiency,

� there are new organisational principles between layers that help to find suitable trade-offs at run-time or compile-time, and

� resource demand and guarantees can be integrated into a new component-based approach to embedded system design.

Key Issues

The consortium will develop methods for heterogeneous embedded-system design with improved predictability properties. Adaptivity will be offered on the basis of reliably determined performance bounds. The predictability of extra-functional properties, such as timing and energy performance, plays a key role. Tool chains for designing embedded systems as offered by the participating partners will be integrated to respond to the needs of the industry.

The PREDATOR methods will enable embedded systems to be designed in a resource-aware way. This will eliminate unnecessary feedback loops, considerably reduce costs, and shorten the time to market.

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At A Glance: PROARTIS

Probabilistically Analyzable Real-Time Systems

Project Coordinator: Name: Gina Alioto Institution: Barcelona Supercomputing Center - Centro Nacional de Supercomputación Email: [email protected]

Project Technical Manager: Name: Francisco J. Cazorla Institution: Barcelona Supercomputing Center - Centro Nacional de Supercomputación Email: [email protected]

Project website: www.proartis-project.eu

Partners:Barcelona Supercomputing Center - Centro Nacional de Supercomputación (Spain) Rapita Systems Ltd. (U.K.) Università di Padova (Italy) Institut National de Recherche en Informatique et Automatique (France) Airbus Operations SAS (France)

Duration: 36 monthsStart: 2010.02.01Total Cost: € 2,425,654EC Contribution: €1,800,000


PROARTISProbabilistically Analyzable Real-Time Systems PROARTIS will define novel hardware and software architectures for critical real-time embedded systems that, thanks to randomized timing behaviour, will ensure negligible probability of pathologically long execution times. This will enable a truly probabilistic worst-case execution time analysis that can be used in certification arguments.KEYWORDS: real-time systems, embedded systems, probabilistic timing analysis, worst-case execution time analysis (WCET)


Main Objectives

The overarching objective of the PROARTIS project is to facilitate a probabilistic approach to timing analysis. The proposed approach will concentrate on proving that pathological timing cases can only arise with negligible probability, instead of struggling to eradicate them, which is arguably not possible and could severely degrade performance. This will be a major turn from previous approaches that seek analyzability by trying to predict with cycle accuracy the state of hardware and software through analysis.

To summarize:

This paradigm shift will permit probabilistic analysis techniques to be used effectively in arguments of system verification and certification, by demonstrating that the probability of pathological execution times is negligible.

The techniques developed in PROARTIS will enable probabilistic guarantees of timing correctness to be derived. For example, if the reliability requirements placed on a sub-system indicate that the probability of a timing failure (a

WCET violation) must be less than 10-9 per hour of operation, then the analysis techniques developed in PROARTIS shall translate this requirement into a probabilistic worst-case execution time guarantee for the sub-system. Probabilistic analysis effectively provides a continuum of worst-case execution times (WCET) for different confidence levels.

PROARTISfocuses on the

probabilistictiming analysis of critical real-time

embedded systems

The central hypothesis of PROARTIS is that new advanced hardware/software features enabling truly randomized timing behaviour can be defined for use in critical real-time embedded (CRTE) systems.

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Thus a sub-system may have a probability of 10-8

per hour of exceeding an execution time of 1.5 ms,

and probabilities of 10-9

, and 10-10

per hour of exceeding 1.55 ms and 1.59 ms, respectively. The main idea of PROARTIS is that for future CRTE systems, such probabilistic guarantees offer significant advantages over deterministic approaches which attempt to make absolute guarantees, thereby severely limiting the opportunity of use of advanced hardware features and inevitably attaining lesser performance.

Technical Approach

The technical approach of the project is to develop new hardware and software architectures that are amenable to probabilistic analysis, and to propose novel and effective probabilistic timing analysis methods. The project will work along three main axes:

1. Architectural Design Principles. Definition of hardware and software design guidelines that will allow CRTE system designers to benefit from randomisation properties. These properties permit to take benefit from high performance hardware features as well as more complex software systems.

2. Probabilistic Timing Analysis. Definition of a new analysis paradigm that exploits the randomisation properties of the proposed architecture. The new probabilistic approach will enable the timing analysis of the new high performance hardware features as well as more complex software systems. As a result of this new analysis paradigm, the project will develop a new probabilistic WCET analysis method and tool.

3. Verification and Certification. Based on the outcomes of (1) and (2), development of probabilistic arguments that can be used effectively in the verification and certification of CRTE systems.

Key Issues

The main challenge of the PROARTIS project is to foster a paradigm shift from deterministic to randomised timing behaviour in CRTE systems. In the past, strong arguments that could be used in certification have been based on understanding the behaviour of the whole system at the level of processor cycle. This approach is becoming increasingly untenable in practicality, error proneness and cost against new-generation hardware technologies, including of course the pervasive multi core systems.

The PROARTIS project moves away from timing-deterministic systems towards timing-randomised systems that exhibit truly independent timing behaviour and therefore enable the application of the law of large numbers to (probabilistically) predict the behaviour of extreme (i.e., long) execution times. The benefits of this novel approach are potentially very large. Strong emphasis is put in the project on the issues that may arise with regard to system validation and on the quantification of the benefits that the approach developed may bring.

Expected Impact

The PROARTIS project will facilitate the production of analysable CRTE systems on advanced hardware platforms with features such as memory hierarchies and multi core processors. PROARTIS has the following overall strategic industrial goals:

1. Increased performance, reliability and reduced costs by enabling CRTE systems to take full advantage of advanced hardware like deep memory hierarchies and multi core processors. The use of these features will allow designers to schedule more tasks while reducing the weight, power consumption and the size of the whole system and maintaining the desired predictability. It will also reduce the risk of temporal budget overruns. Application-level tasks will have an execution behaviour free (with sufficient low probability) from pathological temporal overruns.

2. Increased productivity by enabling software engineers to develop more complex real-time software systems through timing-aware systems that reveal crucial timing details while dramatically simplifying analysis. For example, memory latencies will be predicted with less effort, requiring knowledge only of the total number of memory accesses, rather than the exact memory addresses and memory access patterns.

3. Reduced time-to-market by enabling trustworthy WCET and other analyses for large-scale real-time systems that will dramatically reduce testing time.

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At A Glance: ProSE

Promoting Standardisation for Embedded systems

Project Coordinator: Name:Laila Gide Institution: THALES Email: [email protected]

Project Technical Manager: Name: Erwin Schoitsch Institution: Austrian Research Centers Email: [email protected]

Project website: www.prose-project.org

Partners:Fraunhofer-IGD ESI –Tecnalia (Spain) Austrian Research Centers (Austria) AVL List (Austria) STMicorelectronics (Belgium) CEA (France) Acciona Infraestructuras (Spain) Ericsson AB (Sweden)

Duration: 24 months Start: 2008.05.01Total Cost: € 720 000 EC Contribution: € 720 000


ProSEPromoting Standardisation for Embedded systems Standards are of strategic importance for market creation and development. ProSE envisages providing recommendations for purposeful and efficient standardisation in Embedded Systems, facilitating the evolution of synergies across business domains.

KEYWORDS: Support Action, Embedded Systems, ARTEMIS, Strategic Agenda, Standards, Standardisation, Design by composition, cross-domain (holistic) system view.

Main Objectives

The ProSE project aims at providing the “Embedded Systems” community, particularly ARTEMIS Technology Platform and ARTEMISIA with adequate support for the implementation of their objectives in the “Standardisation” arena by setting-up a methodology for prioritisation and building links with the standardisation bodies in order to foster the emergence of standards in line with the high level objectives of the ARTEMIS ETP. The prime objective of ProSE will be approached by actively assisting ARTEMISIA in elaborating, maintaining, and monitoring a Strategic Agenda in the area of the standards, throughout the 24 months duration of the project, by supporting the specific ARTEMIS Working Group on Standards adopted by ARTEMISIA. More specifically, ProSE aims at enabling the emergence of high value standards by starting with the dissemination of knowledge about relevant deployed and emerging standards in the field of embedded systems within the related R&D communities in Europe, going over to the identification and prioritisation of new areas for standardisation activities and coming up with a practised methodology for supporting their development and acceptance.

ProSE links to European national and international standardisation bodies and pre-standardisation organisations to collaboratively (e.g. in workshops) classify different standardisation needs, and to elaborate common issues across research areas and projects. This will be complemented by setting up an open forum on standardisation issues in Embedded Systems. ProSE also contributes to the action plan for ICT, defined by the European Commission in March 2006, by providing a concrete solution for improvement in the adoption of standards in the rapidly growing embedded systems domains, and by improving the inclusion of different stakeholders in the standardisation process.

ProSE will make a survey of the state of the art and perform a gap analysis through the adoption of a methodology for the identification of appropriate standardisation candidates.

ProSE will focus on providing recommendations

on Embedded Systems Standards to foster cross domains synergies and to

accelerate development and evolution of standards in order to respond to the

needs of the fast evolving markets.


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This is accompanied by awareness building and by communication and dissemination to the stakeholders and to the public at large.

Key Issues

There are, at present, many promising R&D activities dealing with diverse issues of embedded technology, and there are many standardisation bodies that are potentially interested in the results of those R&D activities. However, due to the fragmentation between application domains and between their communities, and also due to the lack of a systematic and selective promotion of standardisation candidates to support the above-mentioned targets in the field of embedded systems, the emergence and evolution of desired standards does not keep pace with the increasingly rapid technology development. The key issue for ProSE is to fill this gap by: - structuring and disseminating knowledge about existing standards within the various embedded systems domains, - providing a set of criteria for identifying and prioritising good candidates for standardisation in a very systematic and selective manner, - proposing a practicable methodology for their maturation towards their eventual acceptance so as to enable or facilitate cross-domain compatibility and a higher degree of reusability.

Expected Impact

The ProSE project will directly address the complexity challenge by promoting and facilitating new approaches to embedded system design. It will also contribute to the changeover from “design by decomposition” to “design by composition” as a major trend for embedded systems, by supporting existing and emerging standards that will enable this changeover. It will help to better meet increasing demand for innovation activities in the Embedded Systems domains by shortening the process of selection of candidate standards, and facilitating the emergence of high quality standards and of new services, cross-domain products and solutions, thus seizing new market opportunities.

Technical Approach

ProSE envisages providing recommendations for purposeful and efficient standardisation in Embedded Systems and facilitating the evolution of synergies across business domains: � by addressing specific cross domain issues such

as the reusability, reliability, verification and certification of embedded software and systems; and

� addressing adaptation of existing standards, influencing evolving or promoting potential new standards in areas not properly addressed until now;

� by investigating the existing specific domains (Aeronautics, Automotive, Rail, Energy, Telecom, Consumer, Medical...) standards in order to identify cross-domain potential synergies and promoting the ProSE vision towards standardisation bodies;

� by establishing links between the ES industry (facilitating the engagement of SMEs), EU standardisation bodies (ETSI, CEN, CENELEC, AUTOSAR …) and worldwide standardisation bodies (ARINC, ITU, IEC, ISO,…), and the research community (particularly Networks of Excellence, ERCIM, EWICS TC7, ENCRESS, “Clubs” and the like;

� by delivering a Strategic Agenda for standardisation. This Strategic Agenda aims at serving as an input to the future EU and national work programmes.

The goal of ProSE is the promotion and initiation of standards and standards adaptation. For this purpose, the project will develop a framework for the analysis of the present standardisation position and a method to determine standardisation priorities for Embedded Systems.

The project will also identify major relevant standardisation organisations and develop criteria for evaluating candidate standards, a work model and procedures for promoting these candidates to reach the status of a standard in the long term. To achieve a long-lasting impact, ProSE therefore intends to establish a self-sustaining process – an approach and a way of working – that will live well beyond the end of the proposed project itself, as long as it is effective in coping with the challenges of finding cross-domain solutions and improving reusability in the field of embedded systems.

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At a Glance: Quasimodo

Quantitative System Properties in Model-Driven-Design of Embedded Systems

Project Coordinator Name: Professor Kim Guldstrand Larsen Institution: Aalborg University, Denmark Email: [email protected]

Project Co-Coordinator Name: Associate Prof. Brian Nielsen Institution: Aalborg University, Denmark Email: [email protected]

Project website: www.quasimodo.aau.dk

Partners:Aalborg University (DK) Embedded Systems Institute (NL) RWTH Aachen University (D) Universität des Saarlandes (D) Université Libre de Bruxelles (B) ENS-Cachan/CNRS (F) Terma A/S (DK) Hydac Gmbh (D) Chess Beheer B.V (NL)

Duration: 36 months Start: 2008.01.01Total Cost: 2.696.000 € EC Contribution: 1.995.000€


QuasimodoQuantitative System Properties in Model-Driven-Design of Embedded Systems

Quasimodo will develop theory, techniques and tool components for handling quantitative (e.g. real-time, hybrid and stochastic) constraints in model-driven development of real-time embedded systems. KEYWORDS: Quantities, non-func-tional properties, modelling, analysis, testing, code-generation, algorithms.


Main Objectives

Characteristic for embedded systems is that they have to meet a multitude of quantitative constraints. These constraints involve the resources that a system may use (computation resources, power consumption, memory usage, communication bandwidth, costs, etc.), assumptions about the environment in which it operates (arrival rates, hybrid behaviour), and requirements on the services that the system has to provide (timing constraints, QoS, availability, fault tolerance, etc.). Existing Model-Driven Development (MDD) tools are rather limited in their handling of quantitative constraints.

The objective of the Quasimodo project is to develop theory, techniques and tool components for handling quantitative (e.g. real-time, hybrid and stochastic) constraints in model-driven development of real-time embedded systems. More specifically, the project aims at:� Improving the modelling of diverse quantitative

aspects of embedded systems.

� Providing a wide range of powerful techniques for analysing models with quantitative information and for establishing abstraction relations between them.

� Generating predictable code from quantitative models.

� Improving the overall quality of testing by using suitable quantitative models as the basis for generating sound and correct test cases.

� Applying the techniques to real-life case-studies and disseminating the results to industry.

Quasimodo will focus on developing new

techniques and tools for model-driven design, analysis, testing and code-generation for advanced embedded

systems with complex quantitative constraints.

Existing Model-Driven Development (MDD) tools are rather limited in their handling of quantitative constraints. Hence MDD will not realise its full potential in the embedded systems area unless the ability to handle quantitative properties is drastically improved.

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Current industrial testing practise is often manual without effective automation and is consequently rather error prone and costly: it is estimated that 30-70% of the total development cost is related to testing. Model-based testing is a novel approach to testing with high potential of improving cost and efficiency. We intend to extend the model-based testing technology to the setting of quantitative models allowing generation,selection, execution and provision of coverage-measures to be made. In order to demonstrate the usefulness of our techniques, we will apply them to several complex industrial case studies, and provide a collection of unique tool components to be use as plug-ins in industrial tools or tool chains.

Key Issues

One key issue is modelling of quantitative information in models with sound semantic basis. Typically these models are automata extended with notations for real-time, continuous, stochastic, and resource consumption. Another central problem is the development of efficient symbolic techniques, algorithms and data-structures for the (automated) analysis of quantitative models, and that can be implemented in tools for analysis, test and controller/code-generation.

Expected Impact

By enabling early and automated analysis, design, and test of embedded systems with quantitative constraints, the results of Quasimodo will increase the competitiveness of European embedded systems industry and will help establish Europe as a leader in design of complex embedded systems. This objective will be reached by both advancing the state-of-the-art of models, tools and methods for quantitative design, together with knowledge transfer to European industries.

Technical Approach

To achieve its aims, Quasimodo will - as illustrated in the figure below - cover all of the logical phases of a typical development trajectory including Modelling and Specification, Analysis, Implementation and Testing. The Quasimodo project will start on the basis of previous theoretical and practical experience of the consortium members, in the areas of verification (real-time, cost-decorated, stochastic and hybrid systems), scheduling and controller synthesis (finite-state, real-time and cost-decorated systems), implementability (finite-state and real-time systems) and testing (finite-state, data-intense and realtime systems). The principle aim of the project is to provide a coherent and scalable metho-dology with a supporting collec-tions of tool components that can be used to design reliable embedded systems that meet their requirements in a controlled and resource-efficient way using a model- driven approach. This means that design decision, analysis, code-generation, testing, etc. are always based upon design models that reflect the relevant aspects of the systems. To focus on aspects such as performance, timeliness, and efficient resource-usage, which are central to embedded systems, the models must provide quantitative information such as information about timing, cost, data, stochastics and hybrid phenomena. Algorithmic methods will be developed for analysis of functional correctness and performance issues. The analysis methods include data-structures for symbolic exploration of the behaviour of models, abstraction and compositionality principles for relating design models and help to control the size and complexity of the models, exploitation of approximate analysis techniques for partial analysis of very complex models and, orthogonally, optimal utilisation of the given computing platform on which the algorithms are implemented. In the implementation step, executable code running on given physical devices has to be provided. The theoretical framework of the quantitative models assumes infinitely fast hardware, infinitely precise clocks, unbounded memory etc. In contrast real CPUs are subject to hard limitations in terms of frequency and memory-size. Thus, how to guarantee that properties established by a given model are also valid of its implementation is a major challenge.

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At A Glance: SATURN

SysML bAsed modelling, archteTUre exploRation, simulation and syNthesis

for complex systems

Project Coordinator / Project Technical Manager: Name: Paul Whiston Institution: Artisan Software Tools Ltd Email: [email protected]

Project website: www.saturnsysml.eu

Partners:Artisan Software Tools (UK) Intracom S.A. Telecom Solutions (GR) Thales Security Systems S.A.S. (F) Extessy AG (D) Paderborn University (D) University of Cantabria (E)

Duration: 36 months Start: 2008.01.01Total Cost: € 3 747 208EC Contribution: € 2 450 000


SATURNSysML bAsed modelling, archteTUre exploRation, simulation and syNthesis for complex systems

KEYWORDS: SysML, UML, MARTE, SystemC, VHDL


Main Objectives

SATURN’s goal is to bridge the current gap between modelling and verification/synthesis in UML based designs of Embedded Systems that are equally composed of HW and SW.To do this, the UML profile for MARTE is evaluated for its complementary application with SysML, and significantly improved adding formal semantics of different Models of Computation for integrated modelling and verification environments. By bridging this gap, SATURN expects to demonstrate a significant reduction in time-to-market. This will be delivered through: � the augmentation of SysML with MARTE,

� the use of MARTE as a platform to integrate SysML with a run-time environment for cross-domain verification,

� the automatic generation of implementable descriptions for both hardware (SystemC/VHDL) and embedded software (C/C++) components of the targeted system, and

� the integration of different abstraction layers allowing seamless integration at functional and target architecture level.

Results are validated by two complex industrial proof-of-concept case studies covering a smart camera system and an outdoor broadband wireless telecom system.

The consortium also includes two major European Universities: Paderborn University & University of Cantabria. SATURN enables Artisan to build on its leading position in engineering based UML tools (extending SysML based on Artisan Studio) while Extessy will benefit from the project by increasing their respective market in verification infrastructures. Taking advantage of the open platform of Extessy AG, the SATURN process will be extremely flexible, and integrate with different third party verification tools and implementations. Through contributions to MARTE standardisation, project results will be exploited both during the project and will persist long after the project has completed.

SATURN will focus on SysML with MARTE, auto-generaration of

SystemC/VHDL and the verification and

simulation of systems

SATURN combines two SME tool vendors (Artisan and Extessy AG) with leading system houses (Intracom S.A. Telecom Solutions & Thales Security Systems S.A.S).

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At A Glance: TERESA

Trusted computing Engineering for Resource constrained Embedded

Systems Applications

Project Coordinator: Name: Antonio Kung Institution: TRIALOG Email: [email protected]

Project Technical Manager: Name: Cyril Grepet Institution: TRIALOG Email: [email protected]

Project website: www.teresa-project.org

Partners:TRIALOG (France) IRIT (France) Fraunhofer SIT (Germany) escrypt (Germany) Universität Siegen (Germany) Ikerlan-IK4 (Spain)

Duration: 36 months Start: 2009.11.01Total Cost: € 3.79 millionEC Contribution: € 2.9 million


TERESATrusted computing Engineering for Resource constrained Embedded Systems Applications

The goal of TERESA is to define, demonstrate and validate an engineering discipline for trust that is adapted to resource constrained embedded systems KEYWORDS: Trust, Security, Dependability, Patterns, Resource Constrained Embedded Systems, Model Driven Engineering.


Main Objectives

The goal of TERESA is to define, demonstrate and validate an engineering discipline for trust that is adapted to resource constrained embedded systems. We define trust as the degree with which security and dependability requirements are met.

� They are used by different application sectors.

� Computing resources are mostly statically determined and allocated through a process consisting of a configuration phase and a building phase.

� They are generally high integrity systems with strong assurance requirements. They therefore use advanced engineering disciplines.

TERESA has the following objectives: � Provide guidelines for the specification of sector

specific RCES trusted computing engineering. Software process engineers in a given sector can then use the guidelines to define a trusted computing engineering process that is integrated with the software engineering process used in their RCES sector.

� Define a trusted computing engineering approach that is suited to the following sectors:

- Automotive

- Home control

- Industry control

- Metering

TERESA will focus on trust, security and

dependability in resource constrained embedded systems.

Resource Constrained Embedded systems (RCES) are characterised as follows:

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Expected Impact

TERESA contributes to the security and reliability of Information and Communication Technology (ICT) through the increased productivity of embedded system development. The engineering process promotes the separation of engineering concerns. It provides application designers with the following benefits:� The reuse of state-of-the-art S&D solutions.

� The advantage of MDE and pattern based approaches. The MDE approach allows the reuse of S&D artefacts at an earlier stage of design.

� The repository access tool allows application designers to have the advantage of MDE even though they do not use MDE for application design and are not experts in modelling.

TERESA's engineering process takes into account domain specific processes. This allows for the support of specific standards, as well as the assurance of the approach. TERESA's open repository facilitates the emergence of new tools for repository access. This will in turn encourage the emergence and growth of new companies. TERESA contributes to European leadership in embedded system design and competitiveness in the area of trusted computing engineering of resource constrained embedded systems. In the future, new systems used for the Internet, for alternative paths to ICT components and systems, and for ICT sustainable development will be resource constrained embedded systems. By focusing on the trusted computing engineering aspects of such systems, TERESA will contribute to the advent of such breakthroughs.

Technical Approach

Patterns Patterns are widely used today to specify architecture and design aspects. They refer to templates which describe solutions for commonly occurring problems. A key advantage is that security and dependability experts can provide patterns which might not be available in companies involved in the development of RCES. The TERESA vision is that Security and Dependability (S&D) patterns that are derived from and associated with domain specific models will help application developers to integrate application building blocks with S&D building blocks.

ModelsModel Driven Engineering (MDE) is a technique for software development. Models are transformed into another one up to the generation of the application. MDE engineering is widely used in embedded systems where assurance requirements are crucial. TERESA advocates the use of a model-based approach for defining patterns and developing applications.

Repository Trust is adapted to resource constrained embedded systems and must take into account the requirements of all sectors, since not all RCES have the same needs. The TERESA approach uses a repository of S&D patterns.

Process Validation in Different Sectors The engineering process for resource constrained embedded systems will be validated in the systems of four application sectors: automotive, home control, industry control, and metering.

Key Issues

TERESA follows a model-based approach which uses S&D patterns: � Application sector trust models are defined as

profiles (e.g. UML, SysML profiles), based on a common trust meta-model.

� S&D platform independent patterns are identified and defined for each application sector, while some patterns can be used by several application sectors.

� The S&D repository saves all patterns. The TERESA process will provide guidelines to define when and how to apply these patterns through the repository.

� Formal properties of S&D are defined and validated for patterns belonging to application sectors requiring a certain level of assurance.

� Platform-dependent implementation of the patterns is guided by precise requirements.

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HOW TO OBTAIN EU PUBLICATIONS

Free publications:

• via EU Bookshop (http://bookshop.europa.eu);

• at the European Union’s representations or delegations. You can obtain their contact details on the Internet (http://ec.europa.eu) or by sending a fax to +352 2929-42758.

Priced publications:

• via EU Bookshop (http://bookshop.europa.eu).

Priced subscriptions (e.g. annual series of the Offi cial Journal of the European Union and reports of cases before the Court of Justice of the European Union):

• via one of the sales agents of the Publications Offi ce of the European Union (http://publications.europa.eu/others/agents/index_en.htm).

European Commission

Embedded Systems Design

Luxembourg: Publications Offi ce of the European Union

2010 – 64 pp. – 21 x 29.7 cm

ISBN 978-92-79-16409-5doi:10.2759/35125

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ISBN 978-92-79-16409-5


KK-32-10-379-EN-C

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