embedded systems: hardware computer processor basics isa (instruction set architecture)

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Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture) RTL (Register Transfer Language) Main reference: Peckol, Chapter 1 Fig. 01-00

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Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture) RTL (Register Transfer Language) Main reference: Peckol, Chapter 1. Fig. 01-00. fig_01_01. Basic components. Common bus structure: address, data, control. fig_01_01. fig_01_03. fig_01_05. - PowerPoint PPT Presentation

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Page 1: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

Embedded Systems: Hardware

Computer Processor Basics

ISA (Instruction Set Architecture)

RTL (Register Transfer Language)

Main reference: Peckol, Chapter 1

Fig. 01-00

Page 2: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_01

Basic components

Common bus structure:address, data, control

fig_01_03

Page 3: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_05

Some processor options(note firmware)

DSP (A/D, D/A; high speed—video, audio, images

2. Microcontroller-based system Fig. 1-05 components integrated into one unit)

1. Microprocessor-based system

fig_01_06

fig_01_07

Page 4: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_08

DATA: DATA TYPES

NUMERIC--Unsigned integer

--Signed integer (2’s complement, sign-magnitude, fixed point, etc.)

--Floating point:3 components:

signexponentmantissa

NONNUMERIC--address

--character

Page 5: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

Numeric data

1. Range is always limited. Number of digits of resolution is size of fractional part.

Example: in 4 numeric bits:

Number of bits in fraction range

0 (integer) 0-15

1: xxx.x 0-7.5(fractions 0, ½)

2: xx.xx 0-3.75(fractions, 0, ¼, ½, ¾)

3: x.xxx 0-1.875(fractions, 0, 1/8, ¼, 3/8, ½, 5/8, ¾, 7/8)

Page 6: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_09

Most base 10 fractions cannot be represented exactly in binary:

Example: how to represent 2.x in 4 bits, with 2 bits of resolution?

Choices: 2.0, 2.25, 2.5, 2.75, 3.0

2.1 2.0 or 2.25

2.2 2.0 or 2.25

2.3 2.0 or 2.25 or 2.5

truncationroundingdown

roundingup

r

rounding truncation

Error range for n bits of resolution:

Truncation: -2-n < Etruncation < 0

Rounding: - ½ 2-n < Erounding < ½ 2-n

Computation: which is easier to compute?

Page 7: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

Error propagation in arithmetic:

Examples:Consider two numbers whose true values are N1 and N2

and whose values in the computing system are N1E and N2E

Addition: errors add: N1E = N1 + E1

N2E = N2 + E2

N1E + N2E = (N1 + E1) + (N2 + E2)

= N1 + N2 + E1 + E2

Multiplication: error :

N1E * N2E = (N1 + E1) * (N1 + E2)

= (N1N2) + (N2 * E1 + N1 * E2) + (E1 * E2)

term 1 term 2

Note that if term 2 is neglected then error depends on size of N1 and N2

Page 8: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_10

Another example (pp. 11-12 of text): measuring power dissipated in resistor R in the following circuit:

Suppose E = 100 VDC +/- 1%, I = 10A +/- 1%, R = 10 ohms +/- 1%.

3 methods of caluculatin power dissipated, neglecting lower order error terms:

a. E1 = (100V +/- 1%) * (10A +/- 1%) = 998.9 1001.1

b. I2R = (10A +/- 1%) * (10A +/- 1%) * (10 ohms +/- 1%) = 997 1003

c. E3 = (100 V +/- 1%)*(100 V +/- 1%) / (10 ohms +/- 1%) = 908.9 1111.3

Which should we use?“optimistic”: a“middle-of-the-road”: average of a,b,c“safest”: c

Page 9: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

Instructions—ISA level

Instruction coding:

HLL (high level language, C, C++ , e.g.)

assembly language (ISA)

machine language

(can work at any level; high level allows faster but less efficient coding)

IEEE Standard 694-1985—IEEE standard for microprocessor assembly language—used for examples in text

Page 10: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

Instruction coding:

Fields: operator, operands (type of addressing)

Example: 32 bits

3 bits: opcode

2 bits: address mode (e.g. direct, indirect, indexed, immediate)

27 bits: for addressing operand (s)

Expanding opcode (example):

000-110xxxx…xxx: 2 operands

1110xxx…xxx: 1 operand

1111xxx…xxx: no operand (e.g., HALT)

operator addr mode operand(s)

Page 11: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_13fig_01_14

fig_01_15

Example instruction formats

Page 12: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

Instructions

Instruction types:

arithmetic / logical

data movement

control

Arithmetic / logical instructions:

operator; number of operands; arity (unary, binary, three-operand, …)

Examples:

x = -x negation, assignment

x = y assignment

x = x + y addition, assignment

z = x + y addition, assignment

Page 13: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_42

Typical ALU and

registers

Page 14: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_43

Common ALU functions

Cannot be affected by interrupt

Page 15: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_44

Common ALU functions (continued)

Page 16: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_45

Common ALU functions (continued)

Question: what is a minimal set of ALU instructions?

Page 17: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_16

Data movement instructions: source / destination

Page 18: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_17

Common data movement instructions

Question: how can you implement XCH without using a temporary variable?

Page 19: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_12

Addressing modes:

Immediate: MOVE A, #BH;

Direct: MOVE OPR1, OPR2;

Indirect: MOVE OPR1, *myVarPtr;

MOVE *OPR1, *OPR1;

MOVE *OPR1, **yPtr;

Register direct: MOVE Reg1, Reg2;

Register indirect: MOVE Reg1, *Reg2;

Indexed (loops): MOVE Reg1, OPR2[REG2];

PC relative (loops,e.g.; offset can be negative):

ADD PC, [Reg1];

Example: what is the difference between Y, *Y, **Y

Indirect addressing—myVarPtr holds address or myVar

Page 20: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_21

Addressing examples:

Page 21: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_22

Page 22: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_23

Page 23: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_24

Page 24: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

Control instructions

Control can be:

sequential (default)

loop (pre or posttest)

branch:

go to

conditional (if, if-else,, case, branch on condition)

procedure or function calll

Page 25: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_29

Branch instructions

Typical condition codes

Typical branch instructions:

fig_01_30

Page 26: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_31

Example of conditional statements: C / assembly language:

fig_01_32

Page 27: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_34

Looping: example

fig_01_35

Page 28: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_36

fig_01_37

Function or procedure call:

Must store return address, pass information back and forth

What are standard parameter passing methods?

Page 29: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_39

Stack: common way to handle procedure / function calls

Q: what are two alternative methods for handling function / procedure calls? Which methods facilitate recursion?

Page 30: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_40

Function call: example:

fig_01_41

Page 31: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

Question: can you design a “general-purpose computer” with a 3-bit opcode?

Page 32: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_46

Different viewpoint:

RTL: register-transfer language level

Page 33: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_49

Register behavior: Read / Write; Serial / Parallel

fig_01_50fig_01_51

Page 34: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_52

RTL VIEW

fig_01_53

Page 35: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_54

fig_01_55Instruction execution cycle

Q: Where is this step implemented?

Page 36: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_57

Multiple levels--examples

Page 37: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_58

Page 38: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

fig_01_59

Page 39: Embedded Systems: Hardware Computer Processor Basics ISA (Instruction Set Architecture)

table_01_03