emc2 xilinx sdsoc presentation

How EMC2 benefits from Xilinx SDSoC

Xilinx SDSoC for Acceleration of Real-time Video Processing on COTS ZYNQ Modules. HiPEAC EMC2 Workshop 2016-01-20

Ji Kadlec, Zdenk Pohl, Luk Kohout (UTIA AV R v.v.i. - Prague, Czech Republic)

Flemming Christensen, Mark Honman, (Sundance - Chesham, United Kingdom)

[emc2] UTIA/Sundance Presentation for HiPEAC 20.01.2016 in Prague2016-20-01Page #

Introduction and ContentIntroduction to the Xilinx SDSoC Environment

UTIA SDSoC 2015.4 HW Platform for EMC2-DPHDMI-in HDMI-out DemosVITA Video Sensor-in HDMI-out Demos, Data movers and HLS blocks

Sundances EMC2 Development Platform


EMC2 - System on Module40mm x 50mm Xilinx SoC or FPGAsZynq, Artix-7 or Kintex-7


EMC2 - System on Module


EMC2 - Devlopment PlatformPC/104 Stackable Board


EMC2 - Development PlatformPC/104 Stackable Board - IO Module


EMC2 - Development PlatformPC/104 Multiprocessing Stack


EMC2 - Development PlatformPC/104 Multiprocessing Stack


EMC2 - Development PlatformPC/104 I/O FMC Expansion Module


EMC2 - Development PlatformPC/104 I/O FMC Expansion Module

[emc2] UTIA/Sundance Presentation for HiPEAC 20.01.2016 in Prague2016-20-01Page #EMC2 Video Processing DemoXilinx SDSoC Environment

[emc2] UTIA/Sundance Presentation for HiPEAC 20.01.2016 in Prague2016-20-01Page #EMC2 Video Processing DemoXilinx SDSoC Environment

[emc2] UTIA/Sundance Presentation for HiPEAC 20.01.2016 in Prague2016-20-01Page #All Programmable SoCs Development Flow

APP(){ funcA(); funcB(); funcC();}HW-SW partition? funcAfuncB, funcCPSPLHW-SW Connectivity?funcAPSfuncB, funcCPLDatamoverPS-PL interfacesSW drivers

Explore optimal architecture

[emc2] UTIA/Sundance Presentation for HiPEAC 20.01.2016 in Prague2016-20-01Page #Without SDSoC: HW-SW Partition Exploration

PL

PS

ApplicationSDKC/C++

DriverSDK, OS ToolsC

IP IntegratorIPI project

DatamoverPS-PL interfaceIPVivadoHLSVerilog, VHDL

HW-SW partition specMet Req ?

[emc2] UTIA/Sundance Presentation for HiPEAC 20.01.2016 in Prague2016-20-01Page #With SDSoC: Automatic System Generation

C/C++Select functions for PL

PL

PS

IP

ApplicationDriverSDSoC

DatamoverPS-PL interfaceMet Req ?func1_sw();func2_hw();func3_hw();

[emc2] UTIA/Sundance Presentation for HiPEAC 20.01.2016 in Prague2016-20-01Page #Base HW Platform for SDSoC

ApplicationDriverInterface IPsInterface IPsApplicationDriverAMBA Bus

PlatformProcessing Systems (PS) Programmable Logic (PL)Custom platform = Vivado project + Bootable software imageAvailable for commonly used development kit and SoMs

[emc2] UTIA/Sundance Presentation for HiPEAC 20.01.2016 in Prague2016-20-01Page #Complete SDSoC flow

ApplicationDriverInterface IPsInterface IPsApplicationDriverAMBA Bus

C/C++ Application

ApplicationDriverIPIPIPIPConnectivity

Generated

[emc2] UTIA/Sundance Presentation for HiPEAC 20.01.2016 in Prague2016-20-01Page #SDSoC Example: Matrix Multiply +Add

main(){ malloc(A,B,C); mmult(A,B,D); madd(C,D,E); printf(E); } madd(inA,inB,out){

}HDL IPC-callable IP mmult(inA,inB,out){

}HLS C/C++A,Bdatamovers

AMBA Bus

Platform

ApplicationDrivermmultmadd

GeneratedDABCE

[emc2] UTIA/Sundance Presentation for HiPEAC 20.01.2016 in Prague2016-20-01Page #EMC2 DP w. HDMI In/Out FMC Module runnung SDSoC 2015.4 environment

666 MHz ARM A9SW synchronization of VFBsSpace for SW version of algorithms

[emc2] UTIA/Sundance Presentation for HiPEAC 20.01.2016 in Prague2016-20-01Page #Sobel Filter Full HD Pf: HDMI In/Out SW and HW flow in Xilinx SDSoC 2015.4Carrier: EMC2-DP

120 MHz HW path/DMA150 MHz VDMA666 MHz ARM A9148,5 MHz HDMI In148,5 MHz HDMI Out

[emc2] UTIA/Sundance Presentation for HiPEAC 20.01.2016 in Prague2016-20-01Page #Sobel Filter Full HD Pf: HDMI In/Out Process only upper 50% of framesSingle computing data path in HW

150,0 MHz VDMA666 MHz ARM A9150 MHz HW path/DMA148,5 MHz HDMI In148,5 MHz HDMI Out

[emc2] UTIA/Sundance Presentation for HiPEAC 20.01.2016 in Prague2016-20-01Page #Sobel filter in Full HD Pf: HDMI In/Out Process upper and lower part of framesTwo parallel computing data paths in HW

Two 120 MHz HW data paths/DMA148,5 MHz148,5 MHz HDMI Out150,0 MHz VDMA666 MHz ARM A9

[emc2] UTIA/Sundance Presentation for HiPEAC 20.01.2016 in Prague2016-20-01Page #Sobel filter in Full HD Pf: HDMI In/Out

[emc2] UTIA/Sundance Presentation for HiPEAC 20.01.2016 in Prague2016-20-01Page #Motion Detection in Full HD Pf: HDMI In/Out Process complete frameSingle computing data path in HW

148,5 MHz HDMI In148,5 MHz HDMI Out120 MHz HW data path/DMA

[emc2] UTIA/Sundance Presentation for HiPEAC 20.01.2016 in Prague2016-20-01Page #Motion Detection Full HD Pf: HDMI In/Out SW and HW flow in Xilinx SDSoC 2015.4Carrier: EMC2-DP

148,5 MHz HDMI In148,5 MHz HDMI Out120 MHz HW data path/DMA

[emc2] UTIA/Sundance Presentation for HiPEAC 20.01.2016 in Prague2016-20-01Page #EMC2-DP with Vita Camera In/HDMI Out using SDSoC 2015.4 environment

666 MHz ARM A9SW synchronization of VFBsSpace for SW version of algorithms

148,5 MHz HDMI Out


120 MHz HW data path/DMA148,5 MHz HDMI OutSobel filter in Full HD Pf: vita-hdmioProcess upper and lower part of framesTwo parallel computing data paths in HW


Sobel filter in Full HD Pf: Vita In/HDMI OutProcess upper and lower part of framesTwo parallel computing data paths in HW

[emc2] UTIA/Sundance Presentation for HiPEAC 20.01.2016 in Prague2016-20-01Page #ConclusionsCompile times in SDSoC (average laptop figures):SW: 1 minHW (Vivado IP Integrator System): 3 minHW (to bitstream and SD card BOOT.BIN): 60 minSDK (final SW project with HW accelerator): 1 min

Licensing:Xilinx is selling license of SDSoC(it is for all ZYNQ devices with Vivado and HLS)SDK (final SW project with HW accelerator): free

Acknowledgement: UTIA and Sundance are partially supported by the Artemis EMC2 project.


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emc2 xilinx sdsoc presentation

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