IW1B.1.pdf Advanced Photonics Congress 2016 (IPR, NOMA, Sensors,Networks, SPPCom, SOF) © OSA 2016

Emerging Photonic Hardware Platforms

Bhavin J. Shastri, Alexander N. Tait, Mitchell A. Nahmias, Thomas Ferreira de Lima,and Paul R. Prucnal

Department of Electrical Engineering, Princeton University, Princeton NJ, 08544 USAshastri@ieee.org

Abstract: Photonic integrated circuit technology could revolutionize optical informationprocessing, beyond conventional binary-logic approaches, granting the capacity of ultrafast-categorization and decision-making. We will discuss the progress and requirements of scalableand reconfigurable emerging photonic hardware platforms.© 2016 Optical Society of America

OCIS codes: (200.0200) Optics in computing; (200.3050) Information processing; (200.4650) Optical interconnects;(250.0250) Optoelectronics; (250.5300) Photonic integrated circuits; (250.5960) Semiconductor lasers.

Photonics has revolutionized information communication, while electronics, in parallel, has dominated informationprocessing. Recently, there has been a determined exploration of the unifying boundaries between photonics and elec-tronics on the same substrate, driven in part as Moore’s Law approaches its long-anticipated end [1, 2]. For example,the computational efficiency (multiply-accumulate (MAC) operations per joule) for digital processing has leveled-offaround 100 pJ per MAC [2]. As a result, there has been a widening gap between computational efficiency and the nextgeneration needs, such as Big Data applications which require advanced pattern matching and analysis on increasinglydense, voluminous data in real-time. This in turn, has led to expeditious advances in: (1) emerging devices that arecalled beyond-CMOS or More-than-Moore, (2) novel processing or unconventional computing architectures calledbeyond-von Neumann, that are bio-inspired i.e. neuromorphic, and (3) CMOS-compatible photonic interconnect tech-nologies. Collectively, these research endeavors have opened opportunities for emerging photonic hardware platformsthat are reconfigurable i.e. programmable optical integrated circuits (POIC) such as photonic spike processors [3–8].Such chips in the near future could combine ultrafast operation, moderate complexity, and full programmability, ex-tending the bounds of computing for applications such as navigation control on hypersonic aircrafts, and real-timesensing and analysis of the radio frequency (RF) spectrum. We will discuss the current progress and requirements ofsuch a platform.

In a photonic spike processor, information is encoded as events in the temporal and spatial domain of spikes (oroptical pulses). This hybrid coding scheme is digital in amplitude but analog in time and benefits from the bandwidthefficiency of analog processing and the robustness to noise of digital communication. Optical pulses are received,processed, and generated by certain class of semiconductor devices that exhibit excitability—a nonlinear dynamicalmechanism underlying all-or-none responses to small perturbations [9]. Optoelectronic devices operating in the ex-citable regime are dynamically analogous with the spiking dynamics observed in neuron biophysics but roughly eightorders of magnitude faster. Example of excitable photonic devices include two-section gain and saturable absorber(SA) lasers [3, 6, 10], semiconductor ring [11–13] and microdisk lasers [14, 15], two-dimensional photonic crystalnanocavities [16, 17], resonant tunneling diode photodetector and laser diode [7], semiconductor lasers based on opti-cal injection [18–20] and optical feedback [21–24], and polarization switching in VCSELs [8].

Using a gain and SA excitable laser, we recently demonstrated [3] the first unified, experimental demonstration oflow-level spike processing functions in an optical platform. Excitatory input pulses to this laser increase the carrierconcentration within the gain region by an amount proportional to its energy through gain enhancement. Beyond someexcitation energy, the absorber is saturated, resulting in the release of a pulse. This is followed by a relative refractoryperiod during which the arrival of a second excitatory pulse is unable to cause the laser to fire as the gain recovers. Weshowed that this platform can simultaneously exhibit logic-level restoration, cascadability and input-output isolation—fundamental challenges in optical information processing [25–27]. We also implemented the classic spike processingtasks of temporal pattern detection and stable recurrent memory—while simple, these fundamental behaviors underlyhigher level processing. We will review the recent surge of interest in the information processing abilities of suchexcitable optoelectronic devices.

The field is now reaching a critical juncture where there is shift from studying single excitable (spiking) devicesto studying an interconnected network of such devices to build a photonic spike processor. We recently proposed [4]

IW1B.1.pdf Advanced Photonics Congress 2016 (IPR, NOMA, Sensors,Networks, SPPCom, SOF) © OSA 2016

Microring Resonators (MRR) Bank

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Hierarchical Broadcast Architecture Broadcast-and-Weight Network Processing Network Node (PNN)

PNN in a Hybrid III-V and Silicon Photonics Platform

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F. Selmi et al. Phy. Rev. Lett. 112 (2014)

Review Article Advances in Optics and Photonics 11

Fig. 12. (a) Cutaway architecture (showing a terraced view of the center) of the hybrid InGaAsP-silicon evanescent laser neurondesign with graphene layers sandwiched in between the Si and III-V layers. This platform includes III-V materials that are bondedto underlying passive silicon photonic interconnection networks. In a typical device, optical modes are hybridized between thesilicon and III-V layers simultaneously [111]. Nanostructures necessary for waveguides, resonators, and gratings are fabricatedstrictly in silicon, while the III-V layers provide optical gain [112, 113]. The use of a DFB cavity guarantees a single longitudinallasing mode, defined through the lithographic definition of lasing wavelength via SOI grating pitch. From [31]. (b) Sketch andscanning electron microscope (SEM) image of the micropillar laser with SA (see text). A vertical micropillar laser in a III-V materialstack is surrounded by a SiN oxide. Pump light (red arrow) is incoming from the top and is partially reflected from the remainingpart of the lower Bragg mirror. From [37].

the semiconductor gain and absorber sections are isolated electrically with a proton implantation region [115], and a separate implantprovides a smaller lifetime in the absorber section.

Shastri et al. theoretically [85] and experimentally [31] demonstrated a fiber-based graphene excitable laser and also proposedan integrated device that contains electrically pumped quantum wells (gain section), two sheets of graphene (SA section), and adistributed feedback-grating (section). Since its emergence as a new type of SA, graphene has been rigorously studied in the context ofpassive mode locking and Q-switching [116–119] and has been preferred over the widely used semiconductor saturable absorbers [120]due to its high saturable absorption to volume ratio [121]. Graphene possesses a number of other important advantages that areparticularly useful in the context of processing, including a very fast response time, wideband frequency tunability (useful for WDMnetworks), and a tunable modulation depth. Furthermore, graphene also has a high thermal conductivity and damage thresholdcompared to semiconductor absorbers.

Fig. 12 shows the integrated excitable laser in a hybrid InGaAsP-graphene-silicon platform. It comprises a III-V epitaxial structurewith multiple quantum well (MQW) region bonded to a low-loss silicon rib waveguide that rests on a silicon-on-insulator (SOI)substrate. Sandwiched in between is a heterostructure of two monolayer graphene sheets and an hexagonal boron nitride (hBN) spacer.The cavity and waveguide are formed by the presence of a half-wavelength grating in the silicon. Silicon gratings provide feedback forthe lasing cavity. The full cavity structure includes III-V layers bonded to silicon, and a quarter-shifted wavelength grating (quartershift not shown). The silicon waveguide has height, width, and rib etch of 1.5 µm, 500 nm, and 300 nm respectively. The length ofcavity is 120 µm. The laser emits light along the waveguide structure into a passive silicon network. The hybrid III-V platform ishighly scalable and amenable to both passive and active photonic integration [112].

Shastri et al. [31] compare the simulated (predicted) performance of the integrated device with those obtained experimentallywith an analogous fiber-based prototype. The former is capable of exhibiting the same behaviors, but on a much faster time scaleand with lower pulse energies. Some key behaviors associated with excitability are shown in Fig. 13. Fig. 13(a) shows the outputpulse width as a function of an input pulse for both the integrated and fiber lasers. Although the pulse profile stays the same, itsamplitude may change depending on the value of the perturbation. The integrated device exhibits the same behavior on a much fastertime scale, recovering in nanoseconds with pulse widths in picoseconds, a factor of about ⇠ 103 and ⇠ 106, respectively than thefiber prototype. The width of the pulses—which puts a lower bound on the temporal resolution of the information encoded betweenspikes—is bounded by both the SA recovery time and the round trip cavity time. Although graphene’s incredibly fast response time(⇠ 2 ps) makes it effectively instantaneous in the fiber lasers, simulations suggest that graphene can shorten the pulse widths in anintegrated device. The relative refractory period on the other hand is bounded by the speed of either the gain or the SA, although thegain recovery times tends to be larger.

Temporal pulse correlation is an important processing function that emerges from excitability. A integrating excitable system isable to sum together multiple inputs if they are close enough to one another in time. This allows for the detection of pulse clusters,or potentially, coincidence detection of pulses across channels through the use of incoherent optical summing [28]. Coincidencedetection underlies a number of processing tasks, including associative memory [122] and STDP [107, 108], a form of temporal learning.Temporal pulse correlation in the fiber laser experiment and simulation, and integrated laser simulation are shown in Fig. 13(b).Reducing the time interval between input pulses (i.e. simultaneous arrival) results in an output pulse. Although the fiber laser canfunction at kHz speeds, the internal dynamics of the integrated device allow it to function much faster, putting it in the GHz regime.

Figure 14(a)–(c) illustrate the typical transient excitable dynamics of a gain-SA laser. In this system, an excitatory pulse increases the

Gain-SA Laser

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Fig. 1. Concepts, devices, and networks to build a photonic spike processor including gain-SA ex-citable lasers, MRR weight banks, PNNs, broadcast-and-weight networks. Also shown is a three-dimensional sketch of a PNN in a hybrid III-V and silicon platform.

an on-chip networking architecture called broadcast-and-weight (Fig. 1) that could support massively parallel (all-to-all) interconnection between excitable lasers. It has similarities with the fiber networking technique broadcast-and-select, which channelizes usable bandwidth using wavelength division multiplexing (WDM); however, the protocolflattens the traditional layered hierarchy of optical networks, accomplishing physical, logical, and processing tasksin a compact computational primitive. Although the processing circuits are unconventional, the required device set iscompatible with mainstream PIC platforms in silicon, which make heavy use of WDM techniques.

Within this network, an interface called processing network node (PNN) (Fig. 1), gives the ability for one laserto communicate with others. A PNN handles inputs from multiple sources by weighting and spatially summing (i.e.weighted addition), before sending the resulting signal to an excitable laser. The front-end of the PNN consists oftwo spectral filter banks of continuously tunable microring resonator (MRR) weight banks that partially drop WDMchannels that are present without demultiplexing. The use of MRRs as continuous-valued weights has recently beenshown [28,29]. One filter bank represents the weights of excitatory (positive) input connections while the other controlsinhibitory (negative) inputs. These weight profiles could be stored in local co-integrated or off-chip CMOS memory.Balanced photodetectors output a current that represents total optical power, thus computing the weighted sum ofWDM inputs in the process of transducing them to an electronic signal, which is capable of modulating an excitablelaser. In this way, each such PNN is connected with every other PNN in a broadcast loop using a broadcast-and-weight network. That is, the broadcast loop is fully multiplexed and capable of supporting N2 interconnects in justone transparent link (waveguide) with N WDM channels; an electronic interconnect would require, at best, N(N −1)/2 links to achieve the same non-blocking behavior. Recent channel density studies [30] quantified analysis formultiwavelength analog networks, and derived a limit of 108 PNNs per broadcast loop, of which many can co-existon a single chip.

An integrated hardware platform has been proposed [10] to be built on a hybrid III-V and silicon photonics platform(Fig. 1). III-V compound semiconductor technology, such as indium phosphide (InP) and gallium arsenide (GaAs), is atthe forefront of providing active elements like lasers, amplifiers and detectors. Silicon, in parallel, brings compatibilitywith CMOS fabrication processes and low-loss passive components like waveguides and resonators. Scalable andfully reconfigurable networks of excitable lasers can be implemented in the silicon photonic layer of modern hybrid

IW1B.1.pdf Advanced Photonics Congress 2016 (IPR, NOMA, Sensors,Networks, SPPCom, SOF) © OSA 2016

integration platforms, in which spiking lasers in a bonded InP layer are densely interconnected through a silicon layer.Such a photonic spike processor will potentially be able to support several thousand interconnected photonic spikeprimitives (PNNs). It is predicted [31] that such a chip would have a computational efficiency of 260 fJ per MAC,which surpasses the energy efficiency wall by two orders of magnitude while operating at very high speeds (i.e. signalbandwidths 10 GHz).

The emerging field of photonic spike processors has received tremendous interest and continues to receive fur-ther developments as PICs increase in performance and scale. As novel applications requiring real-time, ultrafastprocessing—such as the exploitation of the RF spectrum—become more critical, we expect that these systems willfind use in a variety of high performance, time-critical environments.

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