emu peripheral crate specificationmadorsky/backplane/peripheral... · web viewtable 9: ccb...

EMU Peripheral Crate Specification

UCLA High Energy PhysicsVersion 3.2

January 30, 2001

AbstractThis document describes the CMS EMU VME Peripheral Crate Backplane design requirements. Signals to and from the VME modules that comprise the system are specified in detail, including all data bits and connector pins (eventually). Information is included for the Clock and Control Board (CCB), DAQ Motherboard (DMB), Muon Port Card (MPC), and combined Cathode LCT / Trigger Motherboard (TMB).

Figure 1: Peripheral Crate Front View

VME

TMB

DMB

TMB

DMB

TMB

DMB

TMB

DMB

TMB

DMB

CCB

MPC

TMB

DMB

TMB

DMB

TMB

DMB

TMB

DMB

Clock B

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

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J1 VME64x A24D16

TMB MPC

TMB MPC MPC TMB

MPC TMBTMB MPC

MPC TMBTMB MPC

TMB MPC

<> <> <> <> <> <> <> <> <>

Clock BusFast Control Bus

TMB Reload BusDMB Reload Bus

MPC Reload

Revisions

Changes For Version 3.0, January 25, 2001

Backplane1) Connectors changed back to AMP Z-pack, with sockets the backplane.2) Added 1.5V voltage regulators on plug-in boards for GTLP termination.

CCB1) New signal list: removes Calibration bus, modifies Fast Control bus for encoded TTC data2) There are now 3 instead of 2 dmb_cfeb_calibrate[2..0] bits coming from the front panel and

VME.3) CCB can now "hold" a TTC level 1 accept until it is "released" by a dmb_l1a_release or

tmb_release signal. This is a new function requested by OSU for CFEB calibration.4) Fast Control Bus now has 24 bits. Previously, Fast Control + Calibration Bus totaled 15 bits.

Now 24-15=9 new backplane signals are needed.

TMB1) New signal list from CCB2) Signals to/from DMB are now LVTTL instead of GTLP3) Transition module now passes 63 RPC bits and 50 ALCT through backplane to TMB card4) 2 50-pin SCSI cables connect ALCT to TMB5) TMB sends tmb_l1a_release to CCB for CFEB calibration mode.6) TMB now receives alct_hard_reset from the backplane and forwards it to ALCT

DMB1) New signal list from CCB2) Signals to/from TMB are now LVTTL instead of GTLP3) Signals dmb_cfeb_calibrate[] have been increased by 1, using a formerly reserved bit.4) DMB sends dmb_l1a_release to CCB for CFEB calibration mode.

MPC1) MPC now receives TTC signals from CCB for bunch crossing and event-counter verification

Changes For Version 2, December 11,2000

Backplane1) Connectors changed from Z-pack to 160-pin VME64x DIN to avoid having signal pins on

the backplane. The recent reduction in the data width from TMB to MPC leaves only 306 signals going to MPC, which can fit in two 160-pin connectors. (This still allows 7 grounds per connector).

2) Moved CCB, TMB, and DMB connectors to the J3 position to reduce module insertion torque.

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CCB1) Several bussed bits changed (see CCB summary table)2) CCB now has a programmable level 1 accept timer for external triggers and calibration

triggers.3) CCB receives a bussed signal "request_L1A" from TMBs to request a local L1A from the

CCB. This will be useful for the FAST sites as a way to generate and distribute L1A within the crate.

TMB1) CLCT/TMB has been renamed "TMB".2) The number of bits from TMB to MPC has been reduced from 74 to 64.3) TMB now receives 2 "winner" bits (1 per muon) back from the MPC at 80MHz4) TMB has the option of sending 15 or 30 bits to the DMB FIFO5) There are now a few signals reserved for future-use DMB-to-TMB data6) TMB now sends "request_L1A" (bussed, i.e. 1 pin) to the CCB in response to an external

trigger or pattern trigger for the FAST sites.

DMB1) TMB FIFO data can now be stored in either a 15-bit or 30-bit format2) There are now a few signals reserved for future-use DMB-to-TMB data

MPC1) The number of bits from the TMBs has been reduced to 9x64/2 = 2882) MPC now sends 2 "winner" bits back to each TMB using one pin at 80MHz (9 pins total)

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Table of ContentsABSTRACT...................................................................................................................................................................1

REVISIONS...................................................................................................................................................................2

VME CRATE................................................................................................................................................................6

OVERVIEW..................................................................................................................................................................6CONNECTORS..............................................................................................................................................................7VME CONTROLLER....................................................................................................................................................8OPTION 1: DYNATEM D360 3U MODULE.................................................................................................................8OPTION 2: BIT3 6U MODULE....................................................................................................................................8VME ADDRESS SPACE...............................................................................................................................................9VME SLOT ASSIGNMENTS.........................................................................................................................................9VME64X J1/P1 CONNECTOR....................................................................................................................................10

CCB SLOT..................................................................................................................................................................11

CCB SIGNALS...........................................................................................................................................................11CCB SIGNAL DESCRIPTIONS....................................................................................................................................13

Clock Bus:...........................................................................................................................................................13Fast Control Bus:...............................................................................................................................................13TMB Reload Bus:...............................................................................................................................................14MPC Reload Bus:...............................................................................................................................................15DMB Reload Bus:..............................................................................................................................................15DAQ Special Purpose Bus [DMB and TMB]:..................................................................................................15Trigger Special Purpose Bus [TMB Only]:.......................................................................................................16

CCB-FROM-TTC......................................................................................................................................................17CCB SIGNAL COUNT................................................................................................................................................17CCB CONNECTORS...................................................................................................................................................17

TMB SLOTS................................................................................................................................................................18

CCB-TO/FROM-TMB...............................................................................................................................................18CFEB TO TMB........................................................................................................................................................18ALCT-TO/FROM-TMB.............................................................................................................................................18RPC-TO-TMB..........................................................................................................................................................18TMB-TO-DMB.........................................................................................................................................................19TMB TRANSITION MODULE.....................................................................................................................................19TMB-TO-MPC.........................................................................................................................................................20MPC-TO-TMB.........................................................................................................................................................20TMB SIGNAL COUNT...............................................................................................................................................21TMB CONNECTORS..................................................................................................................................................21

DMB SLOTS...............................................................................................................................................................22

CCB-TO/FROM-DMB...............................................................................................................................................22TMB-TO-DMB.........................................................................................................................................................22DMB-TO-DDU........................................................................................................................................................22DMB SIGNAL COUNT...............................................................................................................................................22DMB CONNECTORS..................................................................................................................................................22

MPC SLOT..................................................................................................................................................................23

CCB-TO/FROM-MPC...............................................................................................................................................23TMB-TO-MPC.........................................................................................................................................................23MPC-TO- TMB........................................................................................................................................................23MPC-TO-SR............................................................................................................................................................23MPC SIGNAL COUNT................................................................................................................................................23MPC CONNECTORS..................................................................................................................................................24

MECHANICAL..........................................................................................................................................................25

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POWER DISTRIBUTION.........................................................................................................................................25

FAQ AND OPEN QUESTIONS................................................................................................................................26

CRATE.......................................................................................................................................................................26BACKPLANE..............................................................................................................................................................26CCB..........................................................................................................................................................................26TMB (FORMERLY CLCT/TMB)...............................................................................................................................27DMB.........................................................................................................................................................................28MPC.........................................................................................................................................................................28

REVISION HISTORY...............................................................................................................................................29

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VME CrateOverview

Figure 2: Signal Distribution

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TMB1 of 9

DMB1 of 9

CCB

MPC45

cfd

VMECTRL

3x4 prCLINK from RPC

Cables from ALCT

Differential LVDS

Single Ended GTLP @ 40 MHzLVDS Channel Link

Single Ended 3.3V LVTTL

A24D16 VME 5V TTL

VME64x P1/J1 Bus 160 pinsTo/From All Slots

64 bits = 32 SE GTLP @ 80MHz

TMBData

616 bits319 pins

Rea

r Tra

nsiti

on M

odul

e

Clock Bus 20 LVDS

cfd

cfd

clk

clk

clk









Single Ended GTLP @ 80MHz

Bits

Fro

m 9

TM

B M

odul

es:

2x M

ultip

lexe

d at

80M

Hz

MPC Result for DMB readout

FastCtrl Bus: 24 GTLPTMB Reload: 22 GTLPDMB Reload: 13 GTLP

DAQ Special: 12 GTLPTrigger Special 32 GTLP

MPC Reload: 5 GTLP

3

Single Ended 5V TTL

2x25 pr

Connectors

Figure 3: Crate Connectors

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J1VME

5x32

160pins

ControllerTMB

229 I/O pinsDMB

124 I/O PinsCCB

139 I/O Pins

J1VME

5x32

160pins

J1VME

5x32

160pins

J1VME

5x32

160pins

MPC306 I/O Pins

J1VME

5x32

160pins

J2VME

5x32

160pins

J3CCB

+TMB

J3CCB

+DMB

J2TMB

I/.O

5x32

J3CCB

J3TMBI/O

CCB BusCCB Bus

TMB/DMB Bus

VME BusA24D16

VME BusA24D16

VME BusA24D16

VME BusA24D16

TMB-MPC

CCB Clock

TMB-MPC

J2RPCPassThru+

DMB

VME Controller

Option 1: Dynatem D360 3U module

Processor: Dynatem D360Software: NUCLEUS package from Accelerated Technologies.Mechanical: 3U VMEFeatures: 25/33 MHz 68EN360 Communications Controller with Built-in CPU32+

Processing Core, I/O, and Memory Interface.Ethernet via 10BaseT or AUI.Two 2-wire RS232 Ports and One Sync/Async RS232 Port with Handshaking.Two Sync/Async Serial ports of RS232 or RS422/485.Flexible DMA.4 MB of 32 bit Wide DRAM.2 or 4 MB Flash PROM.256 KB or 1 MB of Dual Ported NV SRAM.Background Debugger Port.Battery Backed Real Time Clock.VMEbus Slot 1 Capability 360 68360 Based 3U VMEbus Communications Controller Card

Option 2: Bit3 6U module

Backplane will have P1/J1 and P2/J2 connectors in slot 1 to accommodate a 6U VME controller.

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http://www.atinucleus.com/intro.htm

http://www.dynatem.com/d360.html

VME Address SpaceAddress/Data: A24/D16Address Space: [23..19] 5 bit Geographic Address [equals crate slot number]

[18..0] 19 bits available to individual board designers

All VME modules will use geographic addressing to partition the available 24-bit address space.This leaves 24-5 = 19 bits of addresses for use within each module.

VME Slot AssignmentsFigure 4: VME Slot Assignments and Bus Connections

Slot Unit VMEBus

J1 J2

ClockBus

FastControl

Bus

TMBReload

Bus

MPCReload

Bus

DMBReload

Bus

DAQSpecial

Bus

TriggerSpecial

Bus

TMBDMBDirect

TMBMPCDirect

RPCALCT

Transition

1 VME 2 TMB 3 DMB 4 TMB 5 DMB 6 TMB 7 DMB 8 TMB 9 DMB 10 TMB 11 DMB 12 CCB 13 MPC 14 TMB 15 DMB 16 TMB 17 DMB 18 TMB 19 DMB 20 TMB 21 DMB

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VME64x J1/P1 ConnectorA VME64x 160-pin, 5-row connector is required in all 21 slots for all J1/P1 because +3.3V power pins and geographic addressing bits are not available on the standard 3-row VME connector.Address bits: 24Data bits: 16Geographic Address bits: 5

Backplane Connector: Harting 02-01-160-2201 Female [What is 02-02-160-2301?]PCB Connector: Harting 02-02-160-2101 Male Right-Angle

Table 5: VME64x J1/P1 pin assignmentsPin Row z Row a Row b Row c Row d1 MPR D00 BBSY* D08 VPC2 GND D01 BCLR* D09 GND3 MCLK D02 ACFAIL* D10 +V14 GND D03 BG0IN* D11 +V25 MSD D04 BG0OUT* D12 RsvU6 GND D05 BG1IN* D13 -V17 MMD D06 BG1OUT* D14 -V28 GND D07 BG2IN* D15 RsvU9 MCTL GND BG2OUT* GND GAP*10 GND SYSCLK BG3IN* SYSFAIL* GA0*11 RESP* GND BG3OUT* BERR* GA1*12 GND DS1* BR0* SYSRESET* +3.3V13 RsvBus1 DS0* BR1* LWORD* GA2*14 GND WRITE* BR2* AM5 +3.3V15 RsvBus2 GND BR3* A23 GA3*16 GND DTACK* AM0 A22 +3.3V17 RsvBus3 GND AM1 A21 GA4*18 GND AS* AM2 A20 +3.3V19 RsvBus4 GND AM3 A19 RsvBus1120 GND IACK* GND A18 +3.3V21 RsvBus5 IACKIN* SERCLK A17 RsvBus1222 GND IACKOUT* SERDAT A16 +3.3V23 RsvBus6 AM4 GND A15 RsvBus1324 GND A07 IRQ7* A14 +3.3V25 RsvBus7 A06 IRQ6* A13 RsvBus1426 GND A05 IRQ5* A12 +3.3V27 RsvBus8 A04 IRQ4* A11 LI/I*28 GND A03 IRQ3* A10 +3.3V29 RsvBus9 A02 IRQ2* A09 LI/O*30 GND A01 IRQ1* A08 +3.3V31 RsvBus10 -12V +5VSTDBY +12V GND32 GND +5V +5V +5V VPC

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CCB SlotThe Clock and Control Board distributes the system clock and other signals common to all modules. Because CCB transmits FPGA reload signals, the CCB itself must have low susceptibility to radiation upset.

CCB SignalsTable 6: CCB Signal Summary

Signal Bits Source Destination Type Logic Duration

Clock Bus: Clock Distribution & Bunch Crossingccb_clock401 19 TTCrx2, FP3,Xtal All 19 Slots Point-to-point LVDS 40MHzccb_clock40_enable 1 VME4, FP All 19 Slots Bussed LVDS Pulse, n counts

Total 20

Fast Control Busccb_cmd[5..0] 6 TTCrx, VME All 19 Slots Bussed GTLP Levelccb_evcntres 1 TTCrx, VME All 19 Slots Bussed GTLP 25nsccb_bcntres 1 TTCrx, VME All 19 Slots Bussed GTLP 25nsccb_cmd_strobe 1 TTCrx, VME All 19 Slots Bussed GTLP 25nsccb_bx0 1 dTTCrx5, VME All 19 Slots Bussed GTLP 25nsccb_l1accept 1 TTCrx, VME, FP All 19 Slots Bussed GTLP 25ns+ECL FPccb_data[7..0] 8 TTCrx, VME All 19 Slots Bussed GTLP Levelccb_data_strobe 1 TTCrx, VME All 19 Slots Bussed GTLP 25nsccb_reserved[3..0] 4 VME Al l 19 Slots Bussed GTLP 25ns

Total 24

TMB Reload Bus: ALCT+CLCT+TMB FPGA Reloadtmb_hard_reset6 1 dTTCrx, VME 9 TMB Bussed GTLP 300nstmb_cfg_done[8..0] 9 9 TMB VME Point-to-Point GTLP Levelalct_hard_reset 1 dTTCrx, VME 9 TMB Bussed GTLP 300nsalct_cfg_done[8..0] 9 9 TMB (from ALCT) VME Point-to-Point GTLP Leveltmb_reserved[1..0] 2 VME 9 TMB Bussed GTLP 25ns

Total 22

MPC Reload Bus: MPC FPGA Reloadmpc_hard_reset 1 dTTCrx, VME MPC Point-to-Point GTLP 300nsmpc_cfg_done 1 MPC CCB Point-to-Point GTLP Levelmpc_reserved[2..0] 3 VME MPC Point-to-Point GTLP 25ns

Total 5

1 Clock: CCB distributes Clock40Des1 from the TTCrx or a crystal or FP, de-skewed separately for each slot.2 TTCrx: Signals derived unaltered by the CCB from the TTCrx chip3 FP: Signals input or output via CCB Front Panel (ECL levels)4 VME: Signals read or written via the CCB VME interface5 dTTCrx: Signals decoded by CCB from TTCrx Brcst[7..2], see Table 7: CCB_CMD[5..0] Command Codes on page 136 hard_reset: CCB decodes separate TTC commands for tmb_hard_reset, alct_hard_reset, dmb_hard_reset, and mpc_hard_reset. The TTC command "hard_reset" pulses all hard resets simultaneously.

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DMB Reload Bus: DMB FPGA Reload dmb_hard_reset 1 dTTCrx, VME 9 DMB Bussed GTLP 300nsdmb_cfg_done[8..0] 9 9 DMB CCB Point-to-Point GTLP Leveldmb_reserved[2..0] 3 VME 9 DMB Bussed GTLP 25ns

Total 13

DAQ Special Purpose Bus [Used by DMB and TMB]dmb_cfeb_calibrate[2..0] 3 VME, FP 9 DMB 9TMB Bussed GTLP 25ns ECL FPdmb_l1a_release 1 9 DMB 9 TMB CCBL1ALogic Bussed GTLP 25nsdmb_reserved_out[4..0] 5 VME 9 DMB 9TMB Bussed GTLP -dmb_reserved_in[2..0] 3 9 DMB 9 TMB VME Bussed GTLP -

Total 12

Trigger Special Purpose Bus [Used by TMB only]alct_adb_pulse_sync 1 VME, FP 9 TMB Bussed GTLP 25ns ECL FPalct_adb_pulse_async 1 VME, FP 9 TMB Bussed GTLP 25ns ECL FPclct_external_trigger 1 VME, FP 9 TMB Bussed GTLP 25ns ECL FPalct_external_trigger 1 VME, FP 9 TMB Bussed GTLP 25ns ECL FPclct_status[8..0] 9 9 TMB VME, FP Bussed GTLP 25ns ECL FPalct_status[8..0] 9 9 TMB VME, FP Bussed GTLP 25ns ECL FPtmb_l1a_request7 1 9 TMB, FP CCBL1ALogic Bussed GTLP 25ns ECL FPtmb_l1a_release8 1 9 TMB CCBL1ALogic Bussed GTLP 25nstmb_reserved_in[4..0] 5 9 TMB VME Bussed GTLP -tmb_reserved_out[2..0] 3 VME 9 TMB Bussed GTLP -

Total 32

7 CCB asserts ccb_l1accept backplane signal 3.2us (VME programmable) after receiving tmb_l1a_request.8 CCB releases ccb_l1accept immediately after receiving tmb_l1a_release

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CCB Signal Descriptions

Clock Bus:ccb_clock40

System 40MHz clock. Derived from TTCrx signal Clock40Des1, and delayed independently for each slot in the crate for isochronous clocking. The clock source can be either Clock40Des1 or an on-board crystal (80MHz divided by 2 for symmetry) or an ECL front panel input.

ccb_clock40_enableEnables 40MHz clock. Enables ccb_clock40 in TMB, ALCT, DMB, and MPC to single-step synchronous logic for debugging.

Fast Control Bus:ccb_cmd[5..0]

TTC Broadcast commands. Sent simultaneously to all peripheral crates in the system. Commands are binary encoded according to the following table:

Table 7: CCB_CMD[5..0] Command Codes 0-3F9

Signal Code(Hex) Description

BX0 00 Bunch Crossing ZeroL1 Reset 01hard_reset 02 Reload all FPGAs from PROMtmb_hard_reset 03 Reload TMB FPGAs from PROMalct_hard_reset 04 Reload ALCT FPGAs from PROMdmb_hard_reset 05 Reload DMB FPGAs from PROMmpc_hard_reset 06 Reload MPC FPGAs from PROMStart Trigger 07Stop Trigger 08Test Enable 09Private Gap 0APrivate Orbit 0Bdmb_cfeb_calibrate0 0C CFEB Calibrate Pre-Amp Gaindmb_cfeb_calibrate1 0D CFEB Trigger Pattern Setupdmb_cfeb_calibrate2 0E CFEB Pedestal Calibrationdmb_cfeb_initiate 0F Initiates CFEB calibration,CCB holds next L1A until dmb_l1a_release|tmb_l1a_releasealct_adb_pulse_sync 10 Pulse Anode Discriminators, synchronous wrt 40MHz clockalct_adb_pulse_async 11 Pulse Anode Discriminators, asynchronousclct_external_trigger_all 12 External Trigger All CLCTsalct_external_trigger_all 13 External Trigger All ALCTs

9 Command code numbers are subject to change. This table is just an example of what the actual commands might be implemented.

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ccb_evcntresEvent Counter Reset. TTC broadcast command, pre-defined to be Brcst[1]. Event Counter Reset clears the Event Counters contained in each VME module that increment on Level 1 Accept.

ccb_bcntresBunch Counter Reset. TTC broadcast command, pre-defined to be Brcst[0]. Bunch Counter Reset clears the Bunch Counters contained in each VME module that increment on ccb_clock40

ccb_cmd_strobeIndicates ccb_cmd[5..0], ccb_evcntres, ccb_bcntres, ccb_bx0, ccb_l1accept, and are valid on the rising edge of ccb_clock40

ccb_bx0Bunch Crossing Zero. Decoded by CCB from Brcst[7..2], resets Bunch Counters to their initial offset values.

ccb_l1acceptLevel 1 Accept. Derived from TTCrx signal L1Accept. This signal is also generated by CCB in response to tmb_l1a_request (for FAST site use). There is also a special CFEB calibration mode, where CCB receives a dmb_cfeb_initiate command from the TTC system or VME. In this mode, CCB "holds" the next L1Accept signal (by preventing it from being broadcast on the backplane). Then CCB "releases" it (by asserting L1Accept on the backplane) when a dmb_l1a_release or tmb_l1a_release signals is received from a DMB or TMB.

ccb_data[7..0]Individually addressed command. Extracted by CCB from Dout[7..0]

ccb_data_strobeIndicates ccb_data[7..0] are valid on the rising edge of ccb_clock40.

ccb_reservedBussed signals from CCB to all modules. Reserved for future use.

TMB Reload Bus:tmb_hard_reset

Reloads TMB FPGA logic from PROM.

tmb_cfg_doneFPGA "Configuration Done" success signal from 9 TMBs. Can be read via CCB VME interface

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alct_hard_resetReloads ALCT FPGA logic from PROM.

alct_cfg_doneFPGA "Configuration Done" success signal from 9 ALCTs. (forwarded by 9TMB to the backplane). Can be read via CCB VME interface

tmb_reservedBussed signals from 9 TMB to CCB. Reserved for future use.

MPC Reload Bus:mpc_hard_reset

Reloads MPC FPGA logic from PROM.

mpc_cfg_doneFPGA "Configuration Done" success signal from MPC. Can be read via CCB VME interface

mpc_reservedSignals from MPC to CCB. Reserved for future use.

DMB Reload Bus:dmb_hard_reset

Reloads DMB FPGA logic from PROM.

dmb_cfg_doneFPGA "Configuration Done" success signals from 9 DMBs. Can be read via CCB VME interface

dmb_reservedBussed signals from 9 DMB to CCB. Reserved for future use.

DAQ Special Purpose Bus [DMB and TMB]:dmb_cfeb_calibrate

CFEB calibration commands. CCB creates these signals from VME or Front Panel inputs.

dmb_l1a_releaseRequests CCB to release L1Accept pending from previous calibration command.

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dmb_reserved_outBussed signals from CCB to 9 DMBs reserved for future use.

dmb_reserved_inBussed signals from 9 DMBs to CCB reserved for future use.

Trigger Special Purpose Bus [TMB Only]:alct_adb_pulse_sync

Triggers the ALCT Anode-Test-Pulse generator, synchronized to the 40MHz clock. CCB creates this signal from VME or front panel inputs.

alct_adb_pulse_asyncTriggers the ALCT Anode-Test-Pulse generator, not synchronized to the 40MHz clock. CCB creates this signal from VME or front panel inputs.

clct_external_triggerExternal trigger for CLCT logic. CCB creates this signal from VME or front panel inputs.

alct_external_triggerExternal trigger for ALCT logic. CCB creates this signal from VME or front panel inputs. TMB forwards this signal to ALCT.

clct_statusCLCT status bit from 9 TMB. They can be read via CCB VME, and are output to the CCB front panel as ECL signals.

alct_statusALCT status bit from 9 TMB. They can be read via CCB VME, and are output to the CCB front panel as ECL signals.

tmb_l1a_requestTMB L1Accept Request. Bussed input from 9 TMB, requests CCB to generate an L1Accept backplane signal.

tmb_l1a_releaseRequests CCB to release L1Accept pending from previous calibration command.

tmb_reserved_inBussed signals from 9 TMBs to CCB reserved for future use.

tmb_reserved_outBussed signals from CCB to 9 TMBs reserved for future use.

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CCB-From-TTCThe TTC system sends data over an optical fiber to the CCB. The optical fiber enters the CCB front panel and does not affect the backplane.

CCB Signal CountTable 8: CCB Signal Count

Bits Pins Source Destination Description

20 40 CCB LVDS 9 TMB 9 DMB 1 MPC Clock Bus24 24 CCB GTLP 9 TMB 9 DMB 1 MPC Fast Control Bus4 4 CCB 9 TMB TMB Reload Bus From CCB18 18 9 TMB CCB TMB Reload Bus To CCB4 4 CCB MPC MPC Reload Bus From CCB1 1 MPC CCB MPC Reload Bus To CCB4 4 CCB 9 DMB DMB Reload Bus From CCB9 9 9 DMB CCB DMB Reload Bus To CCB8 8 CCB 9 DMB 9 TMB DAQ Special Purpose Bus4 4 9 DMB CCB DAQ Special Purpose Bus8 8 CCB 9 TMB Trigger Special Purpose Bus24 24 9 TMB CCB Trigger Special Purpose Bus

128 148 Total

CCB Connectors

Table 9: CCB Backplane Connectors

ID Function Connector

J1 VME64x P1 Harting 02-02-160-2101 Male Right-AngleJ2 - NoneJ3 CCB signals

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TMB Slots

CCB-To/From-TMBTMB modules receive all CCB Fast Control signals, and connect to the DAQ Special Purpose Bus, the Trigger Special Purpose Bus and the TMB Reload bus. FPGA configuration-done status bits after a reload is sent to the CCB. These signals were described previously in the CCB section.

CFEB To TMBTMB connects to Cathode Front End Boards via 5 25-pair cables that connect to the front panel. From each CFEB, TMB receives 48 Comparator bits multiplexed 2:1 at 80MHz. TMB also sends a 40MHz clock to each CFEB over the same cable. Signal levels are LVDS.

ALCT-To/From-TMBTMB communicates with ALCT via 2 25-pair cables that connect to a rear-crate transition module. Data from the ALCT (50 bits) pass from the transition module through the custom backplane to the TMB. There are no connections to the backplane by the ALCT signals, but space is required for the pass-through pins. TMB supplies power and ground to the transition module for ALCT LVDS receivers and drivers.

RPC-To-TMBData from the RPCs (63 bits) pass from the rear-crate transition module through the custom backplane to the TMB. There are no connections to the backplane by the RPC signals, but space is required for the pass-through pins. Channel-link receivers reside on the transition module, so only de-multiplexed 40MHz bits connect directly to a TMB. TMB supplies clock, power, and ground to the transition module for LVDS Channel Link Receivers.

Table 10: RPC-To-TMB

Signal Bits Connector Description

rpc0_vpf 1 C-Link 0 Valid Patternrpc0_seg[11..0] 12 C-Link 0 RPC Segment[11..0]rpc0_bxn[7..0] 8 C-Link 0 Bunch Crossing Number [7..0]

0


0


Total data bits 63 3x4=12 Channel Link pairs

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TMB-To-DMB

TMB boards have a wide point-to-point data path to the adjacent DMB slot.Data from ALCT, CLCT, and TMB for DAQ readout are assembled into a stream for storage in the DMB 36-bit FIFO. The data format is programmable in DMB to accept either 15-bit or 30-bit TMB data words (the 16th bit is reserved as DDU special word flag).

Table 11: TMB-To/From-DMB

Signal Bits Dir Logic Description

tmb_data[14..0] 15 Out LVTTL TMB data[14..0] to 16-bit DMB FIFOtmb_data[29..15] 15 Out LVTTL TMB data [29..15] to 36-bit DMB FIFO optionddu_special 1 Out LVTTL DDU Special Word Flaglast_frame 1 Out LVTTL Last FIFO framefirst_frame 1 Out LVTTL First FIFO frame/write_enable 1 Out LVTTL FIFO /write_enableactive_feb_flag 1 Out LVTTL Active Front-End-Board Flagactive_feb[4...0] 5 Out LVTTL Active FEB indicators[4..0]fifo_clock 1 Out LVTTL 40MHz FIFO storage clock [= tmb_clock]dmb_request_lct 1 In LCTTL DMB requests active_feb_flag from TMBreserved_to_dmb[2..0] 3 Out LVTTL Future signals from TMB to DMBreserved_from_dmb[2..0] 3 In LVTTL Future signals from DMB to TMB

Total Bits 48

TMB Transition ModuleOne cable from the RPCs and two cables from an ALCT connect to a 9U transition module mounted behind each TMB slot. The transition module has no connections to the backplane, but connector space is required for the pass-through pins. Power and ground for transition module circuitry is provided by the TMB.

Table 12: TMB Transition Module Through-Pins

Signal Bits Logic Description

rpc_data 63 LVTTL 40MHz decoded by C-Links on transition boardrpc_clock 1 LVTTL 40MHz clock from TMB for C-linksalct_data 50 LVTTL ALCT data+3.3V 4 Power Vcc for 3 C-Link Receivers, 13 LVDS drivers+3.3V Ground 4 Powerspare 3 - Spare through pins

Total Pins 125

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TMB-To-MPC

Because of the large number of signals sent from the 9 TMBs to the MPC,the data bits are multiplexed 2-to-1 at 80MHz in the TMB output stage.

Table 13: TMB-To-MPC

Signal Bits Logic Descriptionlct0_vpf 1 80MHz GTLP Pt-Pt LCT 0 Valid Pattern Flaglct0_quality[8..0] 9 80MHz GTLP Pt-Pt LCT 0 ALCT+CLCT +bend quality [8..0]lct0_hs[7..0] 8 80MHz GTLP Pt-Pt LCT 0 Cathode ½-Strip ID [7..0]lct0_wg[6..0] 7 80MHz GTLP Pt-Pt LCT 0 Anode Wire-Group ID [6..0]lct0_accmu 1 80MHz GTLP Pt-Pt LCT 0 Accelerator Muonlct0_bxn[1..0] 2 80MHz GTLP Pt-Pt LCT 0 Bunch Crossing Numberlct0_reserved[3..0] 4 80MHz GTLP Pt-Pt LCT 0 Reserved for future use

0

lct1_vpf 1 80MHz GTLP Pt-Pt LCT 1 Valid Pattern Flaglct1_quality[8..0] 9 80MHz GTLP Pt-Pt LCT 1 ALCT+CLCT +bend quality [8..0]lct1_hs[7..0] 8 80MHz GTLP Pt-Pt LCT 1 Cathode ½-Strip ID [7..0]lct1_wg[6..0] 7 80MHz GTLP Pt-Pt LCT 1 Anode Wire-Group ID [6..0]lct1_accmu 1 80MHz GTLP Pt-Pt LCT 1 Accelerator Muonlct1_bxn[1..0] 2 80MHz GTLP Pt-Pt LCT 1 Bunch Crossing Numberlct1_reserved[3..0] 4 80MHz GTLP Pt-Pt LCT 1 Reserved for future use

Total 64 32 Pins

MPC-To-TMB

The MPC chooses the best 3 of 18 muons it receives every 25ns clock cycle. If a muon is accepted by the MPC, a "winner" bit is sent from MPC to TMB. The TMB will insert the bit into ones of its DMB data stream header frames.

Table 14: MPC-To-TMB

Signal Bits Logic Descriptionlct0_winner 1 80MHz GTLP Pt-Pt LCT 0 Accepted by MPC best 3 of 18 sortlct1_winner 1 80MHz GTLP Pt-Pt LCT 1 Accepted by MPC best 3 of 18 sort

Total 2 1 Pin per TMB

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TMB Signal Count

Table 15: TMB Signal Count


2 4 CCB LVDS 9 TMB 9 DMB 1 MPC Clock Bus24 24 CCB GTLP 9 TMB 9 DMB 1 MPC Fast Control Bus4 4 CCB 9 TMB TMB Reload Bus From CCB2 2 9 TMB CCB TMB Reload Bus To CCB8 8 CCB 9 DMB + 9 TMB DAQ Special Purpose Bus4 4 9 DMB CCB + 9 TMB DAQ Special Purpose Bus8 8 CCB 9 TMB + 9 DMB Trigger Special Purpose Bus24 24 9 TMB + 9 DMB CCB + 9 DMB Trigger Special Purpose Bus63 63 RPC TMB RPC Inputs48 48 TMB Adjacent DMB DMB Point-to-point64 32 TMB 80MHz MPC MPC Point-to-point2 1 MPC 80MHz TMB MPC winner

253 222 Total

TMB Connectors

Table 16: TMB Backplane Connectors


J1 VME64x P1 Harting 02-02-160-2101 Male Right-AngleJ2 RPC/ALCT Transition Module

Pass-through + MPC I/OAMP 2mm Z-Pack socket

J3 CCB + DMB I/O AMP 2mm Z-Pack socket

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DMB Slots

CCB-To/From-DMBDMB modules receive all CCB Fast Control signals, and connect to the DAQ Special Purpose Bus, the Trigger Special Purpose Bus and the DMB Reload bus. FPGA configuration-done status bits after a reload is sent to the CCB. These signals were described previously in the CCB section.

TMB-To-DMBDMB boards have a wide point-to-point data path from the adjacent TMB slot. These signals were described previously in the TMB section

DMB-To-DDUDMB boards have an optical link to the DDU card. Optical fibers exit the front of the DMB card.

DMB Signal CountTable 17: DMB Signal Count


2 4 CCB 9 TMB 9 DMB 1 MPC Clock Bus24 24 CCB 9 TMB 9 DMB 1 MPC Fast Control Bus4 4 CCB 9 DMB DMB Reload Bus From CCB1 1 DMB CCB DMB Reload Bus To CCB8 8 CCB 9 DMB + 9 TMB DAQ Special Purpose Bus4 4 9 DMB CCB DAQ Special Purpose Bus8 8 CCB 9 TMB + 9 DMB Trigger Special Purpose Bus24 24 9 TMB + 9 DMB CCB Trigger Special Purpose Bus48 48 TMB Adjacent DMB DMB Point-to-point

123 125 Total

DMB ConnectorsTable 18: DMB Backplane Connectors


J1 VME64x P1 Harting 02-02-160-2101 Male Right-AngleJ2 - NoneJ2 CCB + TMB I/O

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MPC Slot

CCB-To/From-MPCMPC modules receive all CCB Fast Control signals, and connect to the DAQ Special Purpose Bus, the Trigger Special Purpose Bus and the TMB Reload bus. FPGA configuration-done status bits after a reload is sent to the CCB. These signals were described previously in the CCB section.

TMB-To-MPCBecause of the large number of signals received from the 9 TMBs to the MPC,the incoming data bits are multiplexed 2-to-1 at 80MHz in the TMB output stage.

MPC-To- TMBThe MPC chooses the best 3 of 18 muons it receives every 25ns clock cycle. If a muon is accepted by the MPC, a "winner" bit is sent from MPC to TMB. The TMB will insert the bit into ones of its DMB data stream header frames.

MPC-TO-SRThe MPC sends trigger data over optical fibers to a Sector Receiver. Optical fibers exit the MPC front panel and do not affect the backplane.

MPC Signal Count

Table 19: MPC Signal Count


2 4 CCB LVDS 9 TMB 9 DMB 1 MPC Clock Bus24 24 CCB 9 TMB 9 DMB 1 MPC Fast Control Bus4 4 CCB MPC MPC Reload Bus From CCB1 1 MPC CCB MPC Reload Bit To CCB

64 32 TMB 0 MPC TMB 0 data64 32 TMB 1 MPC TMB 1 data64 32 TMB 2 MPC TMB 2 data64 32 TMB 3 MPC TMB 3 data64 32 TMB 4 MPC TMB 4 data64 32 TMB 5 MPC TMB 5 data64 32 TMB 6 MPC TMB 6 data64 32 TMB 7 MPC TMB 7 data64 32 TMB 8 MPC TMB 8 data18 9 MPC TMB MPC "Winner" Results

625 330 Total

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MPC ConnectorsTable 20: MPC Backplane Connectors


J1 VME64x P1 Harting 02-02-160-2101 Male Right-AngleJ2 TMB I/OJ3: TMB I/O

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Mechanical

VME Crate: Type: Modified VIPA VME64xSlot 1: 3U or 6U for VME controllerSlots 2-21: 9U, 400mm

Keying Slots 2-21 must have key-pins or backplane bars to prevent plugging in thewrong type of module.

Module Front Panels:9U4HP type IV, single width with inject-ejector levers.

Rittal 3684.427 Panel Kit [we want the metal-ejector version, which has a different part number]

Power Distribution

It is anticipated that the standard P1/J1 power supply connections are sufficient for all modules.Modules requiring voltages other than +3.3V and +5V are expected to use their own on-board regulators, except for 1.5Vtt, which will be supplied from backplane-mounted regulators. The 1.5Vtt regulators are mounted on plug-in boards for easy replacement.

Table 21: Power Supply Current Per Module P1/J1 [Estimated]

Module +1.5Vtt +1.8V +2.5V +3.3V +5.0V

CCBTMBDMB 1 A 4 A 4 AMPCBackplane

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FAQ and Open QuestionsBold Type = Still unresolved

Crate1) Should TMB be on the left or the right side of DMB?

Answer: TMB left of DMB.

2) Should the order of TMB-DMB pairs reflect about CCB and become DMB-TMB pairs?Answer: No.

3) How are slots keyed? Use VME64x keys or connector offset or Wesley bars?Proposal: put blocking bar on existing backplane supports, matching notches on VME module PCBs.Partial Answer: Current design has offset connectors.

Backplane1) Should the J2,J3 backplane connectors be AMP 2mm Z-Pack or VME64x (160) or ?

Answer: AMP Z-Pack sockets.

2) Should the connectors or backplane have guide pins to prevent bending the connector pins?Answer: Yes

3) How will the power supply cables connect to the backplane without blocking the transition modules?Answer: Power cables are to be routed between transition module slots.

4) GTLP power consumption is lower when the backplane drivers are in the "high" state.Should all FPGAs invert their data on both the transmitting and the receiving end? Answer: Yes

5) Are inverting GTLP driver/receiver ICs available?Answer: No

CCB1) Should CCB 40MHz clock distribution be LVDS or GTLP?

Answer: Differential LVDS. It probably has better timing than single-ended GTLP

2) Should CCB use LVDS, LVTTL, ABT, GTLP for bussed signals?Answer: GTLP.

3) Should TMB configuration-done signals go to CCB or just VME?Answer: Both. Routing CFG signals to the CCB allows localized and fast error reporting.

4) Does DMB need more than just 1 reload command signal? of 29

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Answer: Yes, hard reset and soft reset.

5) Should MPC and DMB send configuration-done to CCB?Answer: Yes, but it depends on OSU and Rice designers to agree.

6) Should non-critical CCB signals be on multi-drop LVDS channel link instead of discrete?Answer: No. Avoid channel links.

7) What is clock_enable used for?Answer: It allows single-stepping the FPGA logic without losing sync in PLLs

8) Should all the TTC signals in Varela's list be connected to the backplane for possible future use? (ready, busy, warning overflow, out of sync, error)Answer: No. These signals will be created at the DDUs or higher in the readout system.

9) Does TTCrx optical cable come out the front or rear of the CCB module?Answer: Front panel, the same as for the DMB.

TMB (formerly CLCT/TMB)1) Do we want discrete LVDS or Bus-TTL for MPC signals instead of channel links?

Answer: No. Use 80MHz 2x multiplexed GTLP.

2) Should RPC signals be on LVDS channel link or 40MHz uncompressed or 80MHz compressed? Depends on RPC latency wrt LCT. Current design assumes LVDS channel links from the RPC link boards.Answer: It doesn't affect the peripheral crate design.

3) How do the RPC signals connect to the TMB module?Answer: Via rear-cage transition modules.

4) Do RPC Channel Link receivers reside on the transition module or on the TMB?[This determines whether the TMB receives 3x4=12 or 3x21=63 bits]Answer: Channel link receivers should be on the transition module.

5) Should RPC send 8 or 5 BXN bits (TMB only uses 2, but FIFO dump uses 12)?Answer: It doesn't affect the peripheral crate design.

6) How do ALCT signals enter the TMB module? The ALCT connector are too large to fit on the TMB front panel. Options are to enter from a rear-panel transition module or to mount connector inside the VME module.Answer: The backplane will have 50 through-pins to allow the transition module solution.

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DMB1) What FPGA radiation reload signals are needed?

Answer: 300ns reload minimum pulse width.

2) Does DMB want to see TMB reload signals?Answer: No.

3) How will DMB get L1A after a CFEB calibration pulse?Answer 1: TMB could generate an external trigger cycle from cfeb_calibrate0

Needs to be coordinated with Global TriggerAnswer 2: CCB asserts L1A when requested to by any TMB

4) Will the DDU optical fibers come out the back or the front of the DMB board?(i.e. does the backplane need a hole for the fibers?).Answer: Front

5) Does the DMB communicate with the Fast Monitoring System?Answer: No. Fast Monitoring signals are generated at the DDU or higher in the readout system

6) Does the DMB want to see the Trigger Special Purpose bus? TMB snoops DAQ Special Purpose Bus, perhaps DMB would snoop the Trigger Special Purpose Bus.Answer: No.

7) What are the source and pulse-width for signals dmb_cfeb_calibrate0 and dmb_cfeb_calibrate1 ?Answer: Source is CCB front panel, CCB VME, and a TTCrx command, which is decoded by the DMB.

MPC1) Should MPC muon selection results be sent to TMB for inclusion in the DAQ readout? If so,

which DMB?Answer: Yes. MPC sends a "winner" bit back to the originating TMB. TMB includes this bit in the ALCT+CLCT data header sent to DMB for inclusion in the DDU data stream.

2) Can MPC use TMB reload signals or does it require separate reload?Answer: Separate hard reset

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Revision History

11/01/00 V1 JK Added 80MHz option for CLCT-MPC signals11/20/00 V1 JK Replaced LVTTL with GTLP everywhere, removed connector pins12/05/00 V2 JK Revisions from December EMU meeting12/11/00 V2 JK Move to VME64x 160-pin DIN connectors01/22/01 V3 JK Back to AMP Z-Pack w/backplane sockets, revised TTC, moved ALCT01/25/01 V3.1 JK More TTC revisions01/29/01 V3.2 JK Changed ccb_cmd and ccb_data to be levels, fixed table 11 to 48 bits

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