ENCRYPTION INFRASTRUCTURE ON-KEY

Written by: Elkin Aleksey

Savi Esacov

Advisor: Idan Shmuel

Winter 2013/14

Final Presentation

BACKGROUND Now there are a lot of data encryption systems based on

hardware These systems encryption mechanism and control system

loose, so there is a dependence and lack of flexibility in the system

Separation of encryption mechanism and the control system will increase the system flexibility Allow to change the encryption mechanism according to the needs Allow to make verification separate for each component Allow to work on control system and encryption mechanism in same time

Now the lab are realizing the encryption and decryption mechanism, which is implanted into the shell we must build

PROJECT PURPOSES

Design universal infrastructure for encryption/decryption system using FPGACreation GUIDesign control system for tracking data from PC to a SD

card and back through encrypts / decrypts Learning and experience in a variety of areas :

RealTime controlling systemFPGAProgramming

MILESTONE GOALS

Planning and creating an interface between the DE2 Board and SD card

Planning and creating an interface between the DE2 Board and PC

Planning and creating GUI Integration between parts of the system

INSTRUMENTS Hardware

DE2 BoardNIOS II coreDLPSD card

SoftwareQuartus II 13.0QsysEclipse – Software control systemActive-HDL – Hardware simulationMatlab - GUI

Hardware synthesis

ARCHITECTURE – HIGH LEVEL

PC

DLP SD card

GUISending data

to encrypt Or decryption

request

NIOS IIsoftware controller

AVALON BUS

Controllerhardware

EncryptionDecryption

(optional)

GUI FOR CONVERTING FILES

Converting text file from regular form in .dat file and back

GUI FOR SENDING/RECEIVING DATA

DLP-USB245M

BLOCK DIAGRAM

FIFO IN8 bits (char)×

8192

Nios II/e

USB protocol(1 MB/s)

STOP and WAIT protocol(40 kB/s)

STOP and WAIT protocol(40 kB/s)

SD CardCTRL NIOS-SD CARD

SOFTWARE

FIFO OUT8 bits (char)×

8192

CTRL FIFO-NIOSHARDWARE

CTRL FIFO-NIOSHARDWARE

DLP

PC

DE BOARD

CTRL PC(DLB)-FIFOHARDWARE

Nios II/e Core – enough for our needs

Using Level 1 debugger is essential for Eclipse

NIOS II CORE

TOP LEVEL

DLP-FIFO controller

FIFO IN

FIFO-NIOS controller

NIOS-SD CARD

FIFO OUT

TOP LEVEL COMPILATION RESULT

When Total memory bits exceed 85% Quartus unable to do Place & Route procedure

RESULTS Maximum possible data file size : 8kb (dictated by the FIFO size) System speed: 40 kb/s (dictated by the NIOS-SD card interface)

SOFTWARE VERIFICATION Software controller (NIOS-SD card) verification done by using

Eclipse console and inspection

HARDWARE VERIFICATION Hardware controller (DLP-FIFO and FIFO-NIOS) verification by

simulation using Active-HDL 9.1

BUGS AND NOTES NIOS II software tools – Eclipse require simple example to

begin to wok Require Altera package for NIOS-SD card interface Using custom data transmitter from FPGA to NIOS-SD card

for calculation maximum system speed

SUMMARY AND CONCLUSIONS The most of the goals were achieved project Using software make system work slowly

NIOS-SD card interface via software decrease system speed Our project allow to compare hardware and software

development and implementation Hardware harder to develop but it faster and easier for debugging

FUTURE DEVELOPMENT RECOMMENDATION

Advancing GUIBetter interface for the novice userReal Time file systemUsing RS422 instead DLP

Speed improvementExchange software controller to hardware

controller

THANK YOU FOR LISTENING