engr 298 successive approximation analog to digital...

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ENGR 298

Successive Approximation Analog to Digital Converter

Presented to

Ali M. Zargar

On April 30, 2010

By Team Number 7

Nila Barot

Committee Members

Faculty Reader Prof. Morris Jones, Retired from Intel Corp.

Industrial Sponsor

Srenik Mehta, Atheros Comm.

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©2010

Nila Barot

ALL RIGHT RESEREVED

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APPROVED FOR THE GENERAL ENGINEERING DEPARTMENT

Morris Jones

Srenik Mehta

__________________________________________

Ali M. Zargar

APPROVED FOR THE UNIVERSITY

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ABSTRACT

This master project report contains implementation of design and economic justification of SAR

ADC. The main motivation is to implement design of capacitor array DAC and achieve high

speed with medium resolution using 45nm technology. The current SAR architecture has in built

sample and hold circuit, so there is significant saving in chip area. The other advantage is

matching of capacitor can be achieved better then resistor. The market and cost analysis says

current SAR ADC has better future.

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ACKNOWLEGEMENT

Writing and implementing this master project was a very rewarding for me. I would like to say

thanks to my project guides Prof. Morris Jones and Srenik Mehta for their guidance and support

for design the SAR ADC using capacitor array DAC. I would like to say thanks to Prof. Ali

Zargar for his direction to planning and writing this master project report. Finally, thanks to the

readers of this project report for their suggestions and comments.

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Contents 1. Introduction ............................................................................................................................................... 8

1.1 Selection of the right ADC architecture .............................................................................................. 8

1.2.1 SAR ADC Architecture ................................................................................................................... 8

1.2.2. Advantages and limitations ............................................................................................................. 9

1.3 VNB company ................................................................................................................................. 10

2. Objective ................................................................................................................................................. 10

2.2 Summary of phenomena ................................................................................................................... 10

2.3 Description of Internal Major Blocks ............................................................................................... 12

2.3.1 Design of Capacitor array DAC ................................................................................................. 12

2.3.2 Operation for binary weighted capacitor array DAC ................................................................. 13

2.3.3 SAR Logic ................................................................................................................................. 17

2.3.4 Design of Comparator ................................................................................................................ 18

2.4.1 Experimental Procedures ............................................................................................................... 23

2.4.1.1 Static parameters .................................................................................................................... 24

2.4.1.2 Dynamic parameters ............................................................................................................... 24

2.4.2 Resources Utilized ......................................................................................................................... 25

2.4.3 Project Schedule ............................................................................................................................. 25

3. Literature Survey .................................................................................................................................... 26

4. Economic Justification ............................................................................................................................ 28

4.1 Executive Summary .......................................................................................................................... 28

4.2. Market Survey .................................................................................................................................. 28

4.3. Current SAR ADC ........................................................................................................................... 33

4.4 Cost Survey ....................................................................................................................................... 34

5. Applications of Data Converters ............................................................................................................. 35

6. Cost Analysis .......................................................................................................................................... 36

6.1 Human Resources ............................................................................................................................. 36

6.2 Product Cost ...................................................................................................................................... 37

6.3. Product Revenue .............................................................................................................................. 38

6.4 Breakeven Analysis .......................................................................................................................... 39

6.5 Profit & Loss Analysis ...................................................................................................................... 42

6.6 SWOT Assessment ........................................................................................................................... 44

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7. Relevance of core courses ....................................................................................................................... 45

8. Conclusion .............................................................................................................................................. 46

9. Future Work ............................................................................................................................................ 46

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1. Introduction

1.1 Selection of the right ADC architecture The selection of the right architecture is a very crucial decision. The following figure 1 shows

the common ADC (Analog to Digital Converter) architectures, their applications, resolutions and

sampling rates. Sigma Delta ADC architectures are very useful for lower sampling rate and

higher resolution (approximately 12-24 bits). The common applications for Sigma-delta ADC

architecture are found in voice band, audio and industrial measurements. The Successive

Approximation (SAR) architecture is very suitable for data acquisition; it has resolutions ranging

from 8bits to 18 bits and sampling rates ranging from 50 KHz to 50 MHz. The most effective

way to create a Giga rate application with 8 to 16 bit resolution is the pipeline ADC architecture.

(Kester, W. 2005, June)

Figure 1 ADC architecture, applications, resolution, and sampling rates. (Kester, W. 2005, June)

1.2.1 SAR ADC Architecture The SAR architecture mainly uses the binary search algorithm. The SAR ADC consists of fewer

blocks such as one comparator, one DAC (Digital to Analog Converter) and one control logic.

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The algorithm is very similar to like searching a number from telephone book. For example, to

search a telephone number from telephone book, first, the book is opened and the number may

be located either in first half or in the second half of the book. Further, relevant section is divided

into half. This procedure can be followed until finding relevant number. (Moscovici, A. 2001)

Figure 2 Block diagram of SAR ADC which has a capacitive DAC, a comparator and a digital

logic ( BP Ginsburg, A. C. 2007).

1.2.2. Advantages and limitations The main advantage of SAR ADC is good ratio of speed to power. The SAR ADC has compact

design compare to flash ADC, which makes SAR ADC inexpensive. The physical limitation of

SAR ADC is, it has one comparator throughout the entire conversation process. If there is any

offset error in the comparator, it will reflect on the all conversion bits. The other source is gain

error in DAC. However, the static parameter errors do not affect dynamic behavior of SAR

ADC. Furthermore, higher the speed, it is difficult to obtain the dynamic behavior of ADC. One

solution is to use time-interleaved converters. (Moscovici, A. 2001)

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1.3 VNB company Currently, VNB Company has one student engineer named Nila Barot and two expert guides Prof. Morris

Jones (Ex. VP of Intel) and Srenik Mehta (Director of Analog Design at Atheros). Data convertor is

major product of company. Company has started business during year 2009, and currently company has

implemented the SAR ADC design. Furthermore, performance testing of SAR ADC is under progress.

2. Objective The Data Converters are widely used in wireless communication, digital audio and video

applications. There are many kind of ADC such as flash ADC, Integrating ADC, pipeline ADC

and SAR ADC. The SAR ADC can be build using resistor string DAC or Capacitor array DAC.

The current SAR ADC design uses capacitor array DAC using 45nm CMOS (Complementary

Metal oxide Semiconductor) technology. (BP Ginsburg, A. C. 2007)

2.2 Summary of phenomena The main goal of this project is to design a successive approximation (SAR) ADC using binary

weighted split capacitor array DAC. The basic algorithm of binary search is to convert analog

signal into digital signal/quantized form. The conversion process starts after discharging the

capacitors. During sampling mode capacitor array is charged by vIN (input voltage). During

charge redistribution mode, MSB (Most Significant Bit) set to one and remaining bits set to zero.

The MSB capacitor is charge to Vref (Reference Voltage). If Comparator output is high, bottom

plate of MSB capacitor remains connected to Vref. On the other hand, if comparator output is

low, the MSB capacitor connects to the ground. The conversion process continue for the next

largest MSB same way, and the second largest capacitor charges to Vref while the remaining

LSB (Least Significant Bit) capacitor array connect to the ground. If the comparator output is

high, the second largest MSB capacitor connects to Vref otherwise it connects to the ground.

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This process continues until the last conversion. The figure 3 shows the logic over view of SAR

ADC, where Vx is voltage at top plate of capacitor

Figure 3. Logic over view of SAR ADC

Discharge

Sample

Hold

Vx>VCM ?

Bi =0

Bit cycle Start

Y

N

Bi =1

Bit remain Unchanged

Bit changed to Zero

Vx=Vx+Vref/

2^(i+1)

Vx=Vx‐Vref/

2^(i+1)

>N

Stop

I=i+1, Bi=1

Y

N

Vx=VCM

Vx=VCM

Vx=‐Vin+VCM

Vx=‐Vin+VCM+Vref/2

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2.3 Description of Internal Major Blocks As mentioned in summary of phenomena, the SAR ADC consists of three major blocks such as a

comparator, a successive approximation register (SAR), and a DAC. The current SAR ADC

builds using following blocks:

• Capacitor array DAC

• Comparator

• Control logic.

2.3.1 Design of Capacitor array DAC The conventional binary weighted capacitor array has limitation for higher resolution due the

larger capacitor ratio from MSB capacitor to LSB capacitor. To eliminate this problem, one

technique can be applied known as split capacitor technique. (BP Ginsburg, A. C. 2007). For

example, to achieve the 8bits resolution, the capacitor array can be splited as shown in following

figure 4. The attenuation capacitor divides the LSB capacitor array and MSB capacitor array.

Here, the ratio between LSB to MSB capacitor (C to 8Cc) reduces drastically compare to the

conventional binary weighted capacitor array (C to 128C). (Baker, J. R., Li, H. W., & Boyce, D.

E.1998)

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Figure 4. Split capacitor array DAC for 8 bits resolution (Baker, J. R., Li, H. W., & Boyce, D. E.,

1998)

2.3.2 Operation for binary weighted capacitor array DAC The capacitor array works in four different phases such as

• Discharge

• Sample

• Charge transfer (Hold)

• Charge redistribution

The following paragraphs describe all the phases in detail.

2.3.2.1 Discharge phase During discharge phase, comparator act as unity gain buffer as shown in figure 5, and the reset

switch is on. All bottom plates of capacitor array are connected to VCM. (In this case 0.5V),

C C 2C8C C2C 8C4C

16/15 C Attenuation Capacitor

VCM

Vin

Vrefn

Vrefp

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hence voltage across capacitor plate are zero. As shown in figure 5, Vx is voltage at top plate of

capacitor array, and VCM is common mode voltage.

Figure 5. Discharge phase

2.3.2.2 Sampling phase During sampling phase bottom plates of capacitor array are connected to Vin as shown in figure

6. The reset switch still on hence the top plate is on VCM; and voltage across capacitor array is

Vin-VCM.

Figure 6. Sampling Phase

2ⁿ C

Vin VCM

2ⁿ C

VCM VCM

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2.3.2.3 Charge transfer/ Hold phase During Charge transfer phase, bottom plates of capacitor array are switched to VCM and top

plates are floating as shown figure 7. In this phase, reset switch is off. Hence, Voltage at top

plate Vx, which is as follows:

Vx= VCM - (Vin-VCM) = -Vin.

For example: Vin = 0.7V

Vx=0.5- (0.7-0.5)

=0.5-0.2=0.3V

Figure 7. Charge transfer Phase

2.3.3.4 Charge redistribution phase During the Charge redistribution phase, first the MSB is set to high, and the bottom plate of

MSB capacitor is connected to Vrefp (Reference voltage Positive) (In this case 1V) as shown in

figure 8. The other remaining bits are set to zero, hence bottom plates of these capacitors are

connected to Vrefn (Reference voltage Negative) (In this case GND). If the comparator output is

high, the MSB reset to high and bottom plate of MSB capacitor remains connected to Vrefp. If

2ⁿ C

VCM VCM

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Comparator output is low, the bottom plate of MSB is then connected back to the GND. The

voltage at top of the capacitor array Vx is:

Vx = -Vin + Vos + D N-1 * (Vrefp/2)

= 0.3 + Vos+ 1*(1/2)* 1(for time being Vos=0)

=0.8 V

Figure 8. Charge redistribution phase (MSB set to High)

Then, the next largest capacitor is tested in the same manner clearly shown in figure 9. The

conversion process continues until the last bit. (Baker, J. R., Li, H. W., & Boyce, D. E. 1998)

2ⁿ⁻ ¹ C

Vrefp

VCM

Vrefn

2ⁿ⁻ ¹ C

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Figure 9. Testing second largest bit during charge redistribution phase

2.3.3 SAR Logic SAR logic is purely a digital circuit, and it consists of three major blocks;

• Counter

• Bit register

• Data register

The counter provides timing control and switch control. For 8 bits conversion, seven DFFs (D

flip-flops) are used. The following table 1 explains which bit set to high during different phases

of SAR operation.

Phase q0 q1 q2 q3 q4 q5 q6

Discharge/Reset 0 0 0 0 0 0 0

Sample/ Reset 1 0 0 0 0 0 0

Vrefp

VCM

Vrefn

2ⁿ⁻ ¹ C

Vrefn

2ⁿ⁻ ² C

2ⁿ⁻ ² C

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Hold (charge Transfer) 1 1 0 0 0 0 0

Test7 [D7] 1 1 1 0 0 0 0

Test6 [D6] 1 1 1 1 0 0 0

Test5 [D5] 1 1 1 1 1 0 0

Test4 [D4] 1 1 1 1 1 1 0

Test3 [D3] 1 1 1 1 1 1 1

Test2 [D2] 0 1 1 1 1 1 1

Test1 [D1] 0 0 1 1 1 1 1

Test0 [D0] 0 0 0 1 1 1 1

Unused 0 0 0 0 1 1 1

EOC (end of conversion) 0 0 0 0 0 1 1

Table 1. Control of switches during different four phases

2.3.4 Design of Comparator

2.3.4.1 Characterization of a comparator A comparator is a circuit, which has a binary output and its value is based on a comparison of

two analog inputs. The output of the comparator is high (VOH) when the difference between the

non inverting and the inverting inputs is positive. The output is low (VOL) when the difference

is negative, which clearly shown in figure 10. This is an ideal behavior of comparator, which is

impossible in a real time.

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Figure 10. Ideal Transfer curve of comparator (Anonymous)

Ideally, output of comparator is defined as follows:

Practically, comparator cannot achieve infinite gain; hence, the output is defined as follows:

(Anonymous)

Figure 11. Transfer curve of comparator with finite gain (Anonymous)

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Another important characteristic of comparator is slew rate. If the input voltage is larger which

will results into a smaller delay time. However, it has upper limit. (Philips E. Allen 2002)

Another non- ideal characteristic of comparator is input offset. The output of comparator does

not change until the input difference reached the input offset Vos. The figure 12 shows the

transfer characteristic of comparator with input offset. The output is defined as follows:

(Philips E. Allen 2002) and (Anonymous)

Figure 12. Transfer curve of a comparator including input offset voltage (Anonymous)

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Figure 13. Ideal Comparator with gain 1000, Vm (0 10 1V), Vp(0.3V)

Input voltage Vm varies from 0 to 1V while another input Vp is set nearly 500mV. The result of

simulation is shown in figure 14.

Figure 14. Simulation data of ideal comparator with gain 1000

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Furthermore, often a comparator is placed in noisy environment; hence, the output of comparator

is noisy. By adding hysteresis into the comparator, better results can be achieved. The hysteresis

can be added by adding positive feedback externally or internally. For current SAR ADC internal

positive feedback is used. (Philips E. Allen 2002)

2.3.4.2 Regenerative comparator There are many types of comparator such as two stage open loop comparator, discrete time

comparator and folded cascade comparator. For current SAR ADC design, discrete time

comparator is used. The discrete time comparator works on some portion of time, and it is clock

driven.

The block diagram of comparator is as shown in figure 15. The first stage is pre amplification

stage to amplify the input signal. The second stage is decision circuit or sense amplifier with

latch. The current regenerative comparator uses positive feedback for comparison of two signals.

The latch works on two phases, one disable the positive feedback and other phase enables the

latch. The latch keeps the voltage high or low relative to its value. The last part of comparator is

an output buffer. (Baker, J. R., Li, H. W., & Boyce, D. E. 1998), and (Philips E. Allen 2002)

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Figure 15 Three stage Comparator block diagram (Baker, J. R., Li, H. W., & Boyce, D. E., 1998)

2.4.1 Experimental Procedures Referred the different internal blocks circuits from literatures, books and online materials, and

applied the concepts to the circuits. The next phase is mathematical calculation which were done

using Microsoft Excel and manually.

The schematic capture is done using the Cadence Composer Tool. The next task was to simulate

the design at circuit level, and to integrate all the circuits to check the functionality. Another

major task was to measure the performance evaluation. The performance parameters are the

essential part of any kind of design to satisfy the design specification. There is two kinds of

parameter of ADC; one is static and other is dynamic. The static parameters are offset error, gain

error, Integral Non linearity (INL), and Differential Non linearity (DNL). While the dynamic

Pre amplification

Sense Amplifier

/Decision Circuit Post amplification

From capacitor

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parameters are, signal to noise ratio (SNR), ENOB (Effective Number of Bits), and Total

harmonic distortion.

2.4.1.1 Static parameters Offset error is defined as the difference between the actual value and theoretical value of input

voltage required to obtain the transition from first code 00…000 to next code 00…001.

(Moscovici, A. 2001)

Gain error is defined as ratio of difference between actual maximum input voltage and actual

minimum input voltage to difference between theoretical maximum input voltage and theoretical

minimum input voltage. (Moscovici, A. 2001)

Integral Non-linearity (INL) is defined as the difference between the data converter code

transition points and straight line with all other error set to zero. (Baker, J. R., Li, H. W., &

Boyce, D. E. 1998)

Differential Non-linearity (DNL) is defined as difference between the actual code width of a

non-ideal converter and ideal case. (Baker, J. R., Li, H. W., & Boyce, D. E. 1998)

2.4.1.2 Dynamic parameters Signal to Noise Ratio (SNR) is ratio of the value of the highest RMS (Root Mean Square) input

signal to the RMS value of the noise. (Baker, J. R., Li, H. W., & Boyce, D. E. 1998)

Effective numbers of bits (ENOB) specifies the dynamic performance of an ADC at a specific

input frequency and sampling rate. (Maxim Integrated Product 2010)

Total harmonic distortion (THD) is defined as the ratio of the RMS sum of the selected

harmonics of the input signal to the fundamental itself. (Maxim Integrated Product 2010)

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2.4.2 Resources Utilized For the design and simulation, Microsoft Excel and Cadence tools are used. For the

implementation of the design, Cadence Composer tool is used. In the next step is simulated the

design using the Cadence Circuit Simulator and the performance parameters are checked

2.4.3 Project Schedule This Project contains two phases; Phase I and Phase II. Both the phases involve the eight major

tasks. Each task has approximately eleven to sixteen days duration. The Table 1 and Gnatt Chart

present the activities of phase II as shown in following.

Task

No

Task Nos. of

Days

Start Time Finish

Time

Status

1 Design of Capacitor array DAC 16 1/22/10 2/12/10 Completed

2 Design of control Logic 11 2/12/10 2/26/10 Completed

3 Design of Comparator 15 2/26/10 3/18/10 Completed

4 Integration of all blocks 4 3/18/10 3/23/10 Completed

5 Simulation of Data Convertor 18 3/23/10 4/16/10 Completed

6 Performance Evaluation 11 4/16/10 4/30/10 Under Progress

7 Final Report 6 4/09/10 4/16/10 Completed

8 Final Report Presentation 6 4/23/10 4/30/10 Under Progress

Table 2 Project Schedule for Project Phase II

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Figure 16. Gnatt Chart for Project Phase II

3. Literature Survey Several IEEE documents, company’s websites and on line newsletters are analyzed. The table 3

shows the summary of performance of a SAR ADC for 65nm CMOS technology.

Table 3. Summary of Performance (BP Ginsburg, A. C. 2007)

Technology 65 nm CMOS 1P6M

Supply Voltage 1.2v

Sampling Rate 500 MS/s

Resolution 5 bits

Input Range 800m Vpp Differential

SNDR(fin=3.3 MHz) 27.8 dB

SNDR(fin=239 MHz) 26.1dB

SFDR(fin=239 MHz) -41.5dB

DNL 0.26 LSB

INL 0.16 LSB

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Texas Instruments have announced the 16, 14, 12 bits six channel simultaneously sampling

analog to digital converter. The maximum data rate per channel is around 500kSPS [3]. The

following data shows the detail features about six channel SAR ADCs. (Incorporated, T. I. 2009,

August).

Features of six channel SAR ADCs

• Family of 16, 14, 12 bits, Pin and software Compatible ADC

• Six SAR ADCs Grouped in three Pairs

• Maximum Data Rate Per Channel with Internal Conversion Clock and Reference:

ADS8556: 630kSPS (PAR) or 450kSPS (SER)



• Maximum Data Rate with External Conversion

Clock and Reference:

800kSPS (PAR) or 530kSPS

• Pin Selectable or Programmable Input Voltage

Ranges: Up to ±12V

• Excellent Signal to Noise Performance:

91.5dB (ADC8556)

85 dB (ADS8557)

73.9 dB (ADS8558)

• Programmable and Buffered Internal

Reference: 0.5V to 2.5V and 0.5V to 3.0V

• Operating Temperature Range:

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-40� C to +125� C

• LQFP -64 Package (Incorporated, T. I. 2009, August)

4. Economic Justification

4.1 Executive Summary Currently, VNB Company has one full time student engineer from San Jose State University

under the guidance of Professor Morris Jones (Ex. VP of Marketing at Intel Corporation) and

Srenik Mehta (Director of Analog Design at Atheros). The present job of the VNB Company is

to implement the design of SAR ADC using 45nm technology.

To achieve this mission VNB Company, currently uses resources from SJSU Electrical

Department Lab. Additionally, for research VNB company explores the library database, books

and online materials. These equipments and materials are easily accessible and economical.

The Company’s progress seems to be satisfactory, and profit of approximately $1.5 million is

expected to be achieved within first five to six years. To accomplish a target the Company is

putting hour’s of hard work, and it also needs initial funding of approximately $250,000.

The wireless communication and battery powered equipment companies are target user of VNB

products.

4.2. Market Survey There are many IC companies, which make different kinds of data convertors. The following is

list of some companies, which make data converters:

• Analog Devices

• National Semiconductors

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• Texas Instruments

• Maxim

• Cirrus Logic

• Universal Semiconductor, Inc

• Accord Solutions, Inc

• Aimtron Technology

• Analog Microelectronics

• Arizona Microtek, Inc

• CE Infosys GmbH

• Empire Technology Group

• Euram Electronics Source, Inc

• Foresight Technologies, Inc

• Quickfilter Technologies Inc.

• Royal Philips Electronics

• Shanghi Belling Co. Ltd

• Smith Semiconductor, Inc

• Swindon Silicon Systems

• T.D Stringer

• THine Electronics, Inc

• Yeeuntech Co. Ltd (Global Spec, 1999-2000)

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Analog Devices announced a few new releases, which have SAR ADC architectures ranging

from 6-bit, 8-bit, and 12-bit up to 28-bits. The newly released data converters are applicable for

low power and high-speed application. (Analog Devices I., 1995-2009)

The table 4 shows important features for currently released AD7985/AD7980, and similar

products.

Table 4. Products and its features (Analog Devices, 2009) and (Analog Devices I., 1995-2009)

Product ID Resolution

bits

Speed

MSPS

Power

Consumption(mw)

AD7985 16 2.5 15.5

AD7980 16 1.0 7.0

AD7450A 12 1 9

AD7450 12 1 9

AD7451 12 1 9.25

AD7440 10 1 9

AD7441 10 1 9.3

AD7983 16 1.33 12

AD7623 16 1.33 55

AD7622 16 2 85

AD7621 16 3 86

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National Semiconductor has a large variety of ADCs, which have sampling rate ranging from

kSPS (Kilo Samples Per Second) to GSPS (Giga Samples Per Second). Here, in table 5, few

products are listed which use SAR ADC architecture. The resolution range is from 8 to 12 bits.

In addition the Graph 1 shows comparison between Analog Devices and National

Semiconductor. (Anonymous, 2009, June)

Product ID Resolu

tion

(bits)

Speed

(kSPS)

Power

Consumption(mw)

3V

Power

Consumption(mw)

5v

Supply

Voltage

ADC081C021 8 5.5 to 189 0.26 0.78 2.7 to 5.5

ADC101C021 10 5.5 to 189 0.26 0.78 2.7 to 5.5

ADC121C021 12 5.56 to189 0.26 0.78 2.7 to 5.5

ADC081C027 8 5.5 to 189 0.26 0.78 2.7 to 5.5

ADC101C027 10 5.5 to 189 0.26 0.78 2.7 to 5.5

ADC121C027 12 5.56 to189 0.26 0.78 2.7 to 5.5

Table 5 National Semiconductor products, resolution, speed, power and supply voltage

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Graph 1 Comparison between Analog Devices and National Semiconductor

National Semiconductor has similar products for ultra high speed and medium resolution;

however, those products use pipeline architecture. The table 6 contains product ID and its

resolution with corresponding speed.

Product ID Resolution bits Speed (GSPS)

ADC081000 8 1

ADC08D1000 8 1

ADC08D1020 8 1

ADC081500 8 1.5

ADC08D1500 8 1.5

0

0.5

1

1.5

2

2.5

3

3.5

8 8 10 10 12 12 12 16 16 16 16

Speed in M

SPS

Resolution in bits

Speed Vs Resolution

Speed MSPS (National Semiconductor)

Speed MSPS (Analog Device)

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ADC08D1520 8 1.5

ADC083000 8 3

ADC08B3000 8 3

Table 6 National Semiconductor’s ultra high speed and medium speed products (Anonymous,

2009, June)

4.3. Current SAR ADC From the market survey, the SAR ADC has resolution from 8 to 16 bits with sampling rate few

kSPS to few MSPS. The current SAR ADC has resolution of 8 bits and sampling rate more than

50 MSPS. The current SAR ADC will be useful for high speed with medium resolution

application. The following graph 2 shows a clear picture for the current SAR ADC’s comparison

with Analog Device and National Semiconductor SAR ADC’s in terms of sampling rates and

resolutions.

Graph 2 Analog Devices, National Semiconductor and current SAR ADC

6

8

10

12

14

16

18

1.00E+02 1.00E+04 1.00E+06 1.00E+08

Resolution

Sampling Rate

Analog Devices

National Semi

Current

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The design specification mentioned under following table no. 7 is for the current SAR ADC.

Table 7. Targeted and Achieved Design specification for 8 bit SAR ADC

4.4 Cost Survey The sampling rate of Analog Device products is higher compared to some of National

Semiconductor ADC products, which make Analog Device Products costlier than National

Semiconductor products for same resolution.

Analog Device National

Semiconductor

AD7985BCPZ $30.99 ADC081S021CIMF $0.67

Targeted Achieved

Technology 45 nm 1P6M 45 nm

Supply Voltage ~1v 1v

Sampling Rate >50MSPS >50MSPS

Resolution 8 bits 8 bits

Integral Nonlinearity +/- 0.5 LSB Under progress

Differential Nonlinearity +/- 0.5 LSB Under progress

Power Consumption Future work Future work

Signal to Noise Ratio Future work Future work

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AD7980ARMZ $13.38 ADC12C105CISQ $24.00

AD7980BRMZ $17.85 ADC12C105CISQE $24.00

AD7626BCPZ $34.95 ADC12C105CISQ $24.00

AD7626BCPZ-RL7 $34.95 ADC12C170CISQ $33.00

Table 8. Pricing for Analog device products and National Semiconductor (Analog Device, I.,

2009), and (Anonymous. (2009, Oct))

However, for comparable resolution and speed both companies have more or less same prices.

5. Applications of Data Converters The applications of Data Converters are listed below:

• Battery powered equipment

• Wireless Communication

• Data acquisition systems

• Medical instruments

• Test and measurement

• Industrial imaging (Analog Device I., 2009), and (Analog Device I., 1995-2009)

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Figure 17. Data converters applications (Anonymous, 2009, June)

6. Cost Analysis

6.1 Human Resources

Currently VNB Company has a single employee under the technical guidance from Prof. Morris

Jones (San Jose State University) and Srenik Mehta (Director of Analog design at Atheros

Comm.). VNB Company has already completed the preliminary phase of research. In the

research phase, the company has done literature survey, market survey, and cost survey. The

implementation part of this project has already completed successfully and the testing part is

done partially. Currently, the performance testing part is in progress. The table 9 shows past and

estimated growth from year 2009 to year 2013 of the VNB Company.

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Department 2009 2010 2011 2012 2013

Engineering 1 1 2 3 6

Marketing 1 1 1 2 5

Human

Resources

0 0 Consultant Consultant Consultant

Table 9. Past and Estimated growth of VNB Company

6.2 Product Cost

From the literature survey, the SAR ADC design seems to be challenging, and from the market

survey and cost analysis, it seems marketable and profitable. Currently at the starting point, the

VNB Company has limited resources such as PC, communication tools, and University

resources. As the company expands, it will have more resources such as office space,

workstations, and marketing facilities. For design purpose, company will provide tools like

Cadence, Mentor Graphics, Synopsis Powermill, and Smart Spice etc. The Company will bear

the license cost of the mentioned tools. The table 10 and Graph 3 explain the past and estimated

company product development cost. (Inc., M. , 2006-09), and (Inc., Y. 2009)

Category 2009 2010 2011 2012 2013

Employee Salary 80 90 300 550 740

Marketing 10 10 30 40 600

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Table 10. Past and Estimated VNB company product development cost (in thousand $)

Graph 3. Graphical presentation of development cost of VNB Company

6.3. Product Revenue

From the cost survey and design cost, the price of VNB Company’s product is estimated around

$30.00. As the company will expand, there will be similar group of products. The breakeven

point reaches in the year 2011 when the company will start making profit. (Inc., M. 2006-09),

and (Inc., Y. 2009. The table 11 shows the past and estimation of product revenue.

0

500

1000

1500

2000

2500

3000

3500

4000

4500

5000

2009 2010 2011 2012 2013

Dollors in

thou

sand

Year

Devlopment Cost

Others

Manufacturing

Marketing

Engineering

Manufacturing 0 20 100 150 3000

Other 0 10 40 50 100

Total 90 140 470 790 3700

39

2009 2010 2011 2012 2013

Nos. of Units 0 2500 18,000 32,000 1,206,000

Revenue 0 75 540 960 4,020

Cost 90 140 470 790 3,700

Profit -90 -65 70 150 320

Table 11. Past and Estimation of Product Revenue in thousand dollars

6.4 Breakeven Analysis

Breakeven analysis can be represented graphically or mathematically. Breakeven analysis relates

fix cost and variable cost with number of units produced or number of operation hours.

Breakeven point says when company starts making profit. Breakeven analysis is very important

technique for firms’ economic evaluation. (Blanchard, B. S., & Fabrycky, W. J. (2006))

It is estimated that VNB Company will sell 2500 units in year 2010 and then next coming years

sale will increase.

The fix cost which must be paid regardless of production. The selling price is estimated $30.00.

Hence, the total revenue is calculated from number of sold units and selling price.

Total revenue = #of units sold * selling price

= 2500 * $30

= $75000

It is assumed that variable cost is around $9 per unit.

40

Hence, total variable cost = # of unit sold * variable cost/unit

= 2500 * $9

=$22,500 (for year 2010)

Breakeven =FC / SP –VC

Where FC is fix cost, SP is selling price and VC is variable cost.

Breakeven = $63000 / ($30 - $9)

= 3000

Similar way breakeven calculation can be done for following years. The graph 4 shows

breakeven analysis for VNB Company. (S., Patel, K., & Byron, Spring 2009)

Graph 4. Breakeven Analysis

$0

$500

$1,000

$1,500

$2,000

$2,500

$3,000

$3,500

$4,000

$4,500

2009 2010 2011 2012 2013

$ in th

ousand

s

Year

Breakeven Analysis

Cost

Revenvebreakeven

41

Initial Years VNB Company’s profit is negative; however, after year 2011 VNB Company will

first make profit. The total investment is $ 250,000. The return of investment is calculated below.

Return on Investment = Net profit – total investment / total investment x 100

= ($385,000 -$250,000) / $ 250,000 x100

= .54 x 100

=54%

The Graph 5 explains the Norden Rayleigh Estimation for each year before VNB Company

makes its first net profit. VNB Company expects approximately $250,000 funding for initial

years.

Graph 5. Norden Rayleigh Estimation for funding

‐20

0

20

40

60

80

100

120

140

160

180

0 1 2 3 4 5 6 7

Dollors in

thou

sand

s

Year

Norden Rayleigh Estimation

Dollors in thousands

42

6.5 Profit & Loss Analysis Profit and Loss analysis is estimated for year 2009 to 2011.The table 12 to 14 shows profit and

loss with income and expense in tabular form.

Quarter Income Expense Profit/Loss

Qtr 3 '09 0 60 -60

Qtr 4 '09 0 30 -30

Table 12 Past and Estimated Profit and Loss for Qtr 3 ’09 to Qtr 4 ’09 ($ in thousands)

The graph 6 shows VNB Company did not make any money in year 2009, however loss is

reduce in following years.

Graph 6 Past and Estimated Profit and Loss for Qtr 3 ’09 to Qtr 4 ’09

‐80

‐60

‐40

‐20

0

20

40

60

80

Qtr 3 '09 Qtr 4 '09

$ in th

ousand

s

Quarter & Year

P & L Qtr3 '09 to Qtr4 '09

Income

Expense

Profit/Loss

Quarter

Qtr 1 '10

Qtr 2 '10

Qtr 3 '10

Qtr 4 '10

Table 13

Graph 7 E

As shown

Quarter

Qtr 1 '11

‐

‐

$ in th

ousand

s

I

1

3

3

4

Estimated P

Estimated P

n in table 14

Incom

60

20

10

0

10

20

30

40

50

Qtr 1

Income Ex

10 -20

30 -20

35 50

40 50

Profit and Lo

rofit and Lo

4 and graph 8

me Exp

75

1 '10

P &

xpense Pr

0 -20

0 -20

-1

-10

oss for Qtr 1

ss for Qtr 1

8, VNB Com

pense Pro

-15

Qtr 2 '10

Quarte

&L Qtr

43

rofit/Loss

0

0

5

0

’10 to Qtr 4

’10 to Qtr 4

mpany expec

ofit/Loss

5

Qtr 3 '10

r & Year

1 '10 to

4’10 ($ in tho

’10

cted first pro

Income

60

0 Qtr

Qtr 4 '1

ousands)

ofit in year 20

4 '10

10

011.

Income

Expens

Profit/

e

se

Loss

Qtr 2 '11

Qtr 3 '11

Qtr 4 '11

Table 14

Graph 8 E

6.6 SWOThe SWObriefly su

‐

10

1

20

2

$ in th

ousand

s

60

190

230

Estimated P

Estimated P

OT AssessmOT analysis ummarized.

50

0

50

00

50

00

50

Qtr 1

75

160

160

Profit and Lo

rofit and Lo

ent performed u

'11 Qtr

P & L

-15

0 30

0 70

oss for Qtr 1

ss for Qtr 3

using market

r 2 '11 Q

Quarter & Y

Qtr 1 '1

44

5

’11 to Qtr 4

’11 to Qtr 2

t survey. In f

Qtr 3 '11

Year

1 to Qtr

60

190

230

4 ’11 ($ in th

’12

following tab

Qtr 4 '11

r 4 '11

housands)

ble 15 SWO

Inc

Exp

Pro

OT assessmen

ome

pense

ofit/Loss

nt is

45

Strengths Weaknesses

1. Current SAR ADC has 8 bits resolution and speed >50 MSPSs using 45nm technology. 2. Capacitor array DAC is better compare to resistor string DAC. Matching of Capacitor can be achieved better compare to resistor matching.

1. VNB is small company, so it is difficult to grow in recession time.

Opportunities Threats

1. From market and cost analysis, VNB Company’s product seems marketable and cost effective. 2. In built sample and hold circuit, so there can be significant saving in chip area.

1. Analog Device and National have released similar kind of ADCs. They may come up with better design.

Table 15. SWOT Assessment

7. Relevance of core courses The break-even analysis, which was covered in ENGR 202, is useful for this project. Breakeven

analysis is a technique used to find out or analyze when company will make profit. The subject

matter of ENGR 202 is useful to find return of investment and mainly to understand overall

project life cycle. The ENGR 203’s contain is helpful for project planning and scheduling using

techniques like Gnatt Chart and CPM (critical path method). The topics covered in ENGR 201

are the Fourier series, time and frequency domain, and transfer function, which are useful to

understand the ADC signal flow. ENGR 200W covered the formatting, how to write the report

and how to present the power point.

46

8. Conclusion As discuss in the introduction, a SAR ADC is suitable for medium resolution with higher speed

ranging from kSPSs to MSPSs. From the literature survey, and current market and cost survey,

the future of SAR ADC using capacitor array DAC is marketable and cost-effective. As

mentioned in the two analog product companies (Analog Devices and National Semiconductor)

are making similar kind of ADC. Furthermore, the SAR ADC has many applications such as

wireless communication, and medical Instruments.

9. Future Work Future work is to increase the resolution up to 12, 16 and 18 bits with reasonable speed. Current

SAR ADC is designed using split capacitor array DAC. For future design SS capacitor array

(Series Split Capacitor array) can be used. VNB Company will make products using other

architectures such flash ADC or pipeline ADC.

47

Bibliography

[1] Analog Devices, I. (1995 - 2009 ). Retrieved from http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad7985/products/product.html.

[2] 16-Bit, 2.5 MSPS, PulSAR 15.5 mW ADC in LFCSP. (2009). Retrieved from www.analog.com.

[3]Device, A. (1995-2009). AD7980: 16-Bit, 1 MSPS PulSAR® ADC in MSOP/QFN . Retrieved from http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad7980/products/product.html.

[4]Kester, W. ( 2005, June). Which ADC Architecture Is Right for Your Application? Retrieved from http://www.analog.com/library/analogDialogue/archives/39-06/architecture.pdf.

[5] Anonymous. (2009, June). Analog Products selection Guide. Retrieved from www.national.com.

[6] Anonymous. (2009, Oct). Price & Availability. Retrieved from http://www.national.com/pf/master_DC.html.

[7] S., Patel, K., & Byron. (Spring 2009). Multicore Microprocessor Interfacing (Propeller). San Jose State University.

[8] Inc., M. (2006-09). How to calculate Cost of Goods. Retrieved from http://www.marketingmo.com/how-to-articles/marketing-metrics/how-to-calculate-cost-of-goods/.

[9] Inc., M. (2006-09). How to Calculate ROI – Return on Investment. Retrieved from http://www.marketingmo.com/4-support-tools/how-to-calculate-roi-return-on-investment/.

[10] Inc., Y. (2009). What is revenue? how do i calculate it? and how do businesses generate it? Retrieved from http://answers.yahoo.com/question/index?qid=20080513102735AAKMSuH.

[11] Baker, J. R., Li, H. W., & Boyce, D. E. (1998). CMOS CIRCUIT DESIGN, LAYOUT, AND SIMULATION. New York: The Institute of Electrical and Eletronics Engineers, Inc

[12] BP Ginsburg, A. C. (2007). 500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC. IEEE Journal of Solid State Circuits .

[13] Incorporated, T. I. (2009, AUGUST ). 16-, 14-, 12-Bit, Six-Channel, Simultaneous Sampling. Retrieved from http://focus.ti.com/lit/ds/symlink/ads8558.pdf.

48

[14 ] Moscovici, A. (2001). High Speed A/D Converters. Kluwer Academic Publishers.

[15] Maxim Integrated Product. (2009). Retrieved from http://para.maxim-ic.com/en/search.mvp?fam=fast_adc&hs=1.

[16] GlobalSpec. (1999-2009 ). Specialty Data Acquisition and Convertor Chips. Retrieved from http://semiconductors.globalspec.com/SpecSearch/Suppliers/Semiconductors/Analog_Mixed_Signals/Data_Acquisition_Chips/Specialty_Data_Acquisition_Converter_Chips.

[17] Blanchard, B. S., & Fabrycky, W. J. (2006). Systems engineering and Analysis. New Jersey: Prentice Hall.

49

Appendix A

CMOS Switch Ron

To estimate the Ron resistance of CMOS switch following circuit as shown in figure3 is used. The Dc

operating condition is simulated and results are tabulated in table 1.

Figure1. CMOS Switch Ron Schematic

Current

1uA

Vin V NMOS Ron PMOS Ron CMOS Ron

0.00E+00 3.4150E+03 1.6910E+11 3.4150E+03

1.00E‐01 3.6280E+03 4.9170E+09 3.6280E+03

2.00E‐01 3.9870E+03 1.5030E+08 3.9869E+03

3.00E‐01 4.7050E+03 5.3350E+06 4.7009E+03

4.00E‐01 6.6680E+03 2.9910E+05 6.5226E+03

5.00E‐01 1.5610E+04 4.1520E+04 1.1345E+04

6.00E‐01 1.0230E+05 1.5260E+04 1.3279E+04

50

7.00E‐01 1.8580E+06 9.4920E+03 9.4438E+03

8.00E‐01 5.1810E+07 7.3410E+03 7.3400E+03

9.00E‐01 1.6300E+09 6.2470E+03 6.2470E+03

1.00E+00 5.3440E+10 5.5860E+03 5.5860E+03

Table 1 Ron Resistance of CMOS switch

MOS characteristics

NMOS Characteristics

The figure2 is schematic for circuit simulation, and the output characteristics of NMOSs are plotted in

figure 3. The drains to source currents are almost constant when transistors are in saturation region (for

currents lower than 30uA). For higher currents, the length modulation effect is significant.

Figure 2. Circuit for simulating output characteristics

51

Figure 3. Output characteristics of NMOS transistor

PMOS Characteristics

The figure 4 is schematic for circuit simulation, and the output characteristics of PMOSs are plotted in

figure 5.

Figure 4. Schematic to measure output characteristics of PMOS

52

Figure 5. Output Characteristics of PMOS transistor

Transconductance parameter

Kn (transconductance parameter for NMOS) and Kp (transconductance parameter for Pmos) are

calculated from performing circuit simulation as shown in following figure 4. The graphical

presentation is shown in graph 1 and graph2. The Kn is approximately 148 uA/V2 and Kp is

approximately 78 uA/V2 for 45 CMOS technology.

Figure 6. Schematic to find Kn and Kp for NMOS and PMOS respectively

53

Graph 1. Kn vs L (length in nm) for different value of W (width in nm) for NMOS

Graph 2 Kp vs L (length in nm) for different value of W(width in nm) for PMOS

0

50

100

150

200

250

300

45 90 135 180

Kn

L nm

Kn vs L

Kn(w=67.5nm)

Kn(w=135nm)

Kn(w=202.5nm)

Kn(w=270nm)

0

20

40

60

80

100

120

45 90 135 180

Kp

L nm

Kp vs L

Kp (W=67.5nm)

Kp(w=135nm)

Kp(w=202.5nm)

Kp(w=270nm)

54

Appendix B

engr 298 successive approximation analog to digital...

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