eGaN® FET DATASHEET EPC2016C

EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 1

EPC2016C eGaN® FETs are supplied only in passivated die form with solder bars.Die size: 2.1 x 1.6 mm

Applications• High Speed DC-DC conversion• Class-D Audio• High Frequency Hard-Switching and Soft-Switching Circuits

Benefits• Ultra High Efficiency• Ultra Low RDS(on)

• Ultra Low QG

• Ultra Small Footprint

EFFICIENT POWER CONVERSION

HAL

EPC2016C – Enhancement Mode Power Transistor

VDS , 100 VRDS(on) , 16 mΩID , 18 A

G

D

S

Maximum Ratings

PARAMETER VALUE UNIT

VDS

Drain-to-Source Voltage (Continuous) 100 V

Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 120 V

ID

Continuous (TA = 25°C, RθJA = 13.4°C/W) 18A

Pulsed (25°C, TPULSE = 300 µs) 75

VGSGate-to-Source Voltage 6

VGate-to-Source Voltage -4

TJ Operating Temperature –40 to 150°C

TSTG Storage Temperature –40 to 150

Thermal Characteristics

PARAMETER TYP UNIT

RθJC Thermal Resistance, Junction-to-Case 2

°C/W RθJB Thermal Resistance, Junction-to-Board 4

RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 69Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.

All measurements were done with substrate connected to source.

Static Characteristics (TJ = 25°C unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITBVDSS Drain-to-Source Voltage VGS = 0 V, ID = 300 μA 100 V

IDSS Drain-Source Leakage VGS = 0 V, VDS = 80 V 25 150 µA

IGSSGate-to-Source Forward Leakage VGS = 5 V 0.5 3 mA

Gate-to-Source Reverse Leakage VGS = -4 V 0.15 0.25 mA

VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 3 mA 0.8 1.4 2.5 V

RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 11 A 12 16 mΩ

VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.8 V

Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate.

eGaN® FET DATASHEET EPC2016C

EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 2

I D –

Drai

n Cu

rrent

(A)

VDS – Drain-to-Source Voltage (V)

75

60

45

30

15

0 1.0 1.5 2.0 2.5 3.0

VGS

GS

GS

GS

= 5 VV = 4 VV = 3 VV = 2 V

I D –

Drai

n Cu

rrent

(A)

VGS – Gate-to-Source Voltage (V)

75

60

45

30

15

00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

R DS(

on) –

Dra

in-to

-Sou

rce R

esist

ance

(mΩ)

R DS(

on) –

Dra

in-to

-Sou

rce R

esist

ance

(mΩ)

VGS – Gate-to-Source Voltage (V)

40

50

30

20

10

02.5 2.0 3.0 3.5 4.0 4.5 5.0 2.5 2.0 3.0 3.5 4.0 4.5 5.0

VGS – Gate-to-Source Voltage (V)

50

30

40

20

10

0

ID = 11 A

25˚C125˚C

VDS = 3 V

25˚C125˚C

Figure 1: Typical Output Characteristics at 25°C Figure 2: Transfer Characteristics

Figure 3: RDS(on) vs. VGS for Various Drain Currents Figure 4: RDS(on) vs. VGS for Various Temperatures

0 0.5

ID = 8 AID = 12 AID = 20 AID = 40 A

Dynamic Characteristics (TJ = 25°C unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITCISS Input Capacitance

VGS = 0 V, VDS = 50 V

360 420

pFCOSS Output Capacitance 210 310

CRSS Reverse Transfer Capacitance 3.2 4.8

RG Gate Resistance 0.4 Ω

QG Total Gate Charge

VDS = 50 V, ID = 11 A

3.4 4.5

nC

QGS Gate-to-Source Charge 1.1

QGD Gate-to-Drain Charge 0.55 1

QG(TH) Gate Charge at Threshold 0.7

QOSS Output Charge VGS = 0 V, VDS = 50 V 16 24

QRR Source-Drain Recovery Charge 0All measurements were done with substrate connected to source.Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.

eGaN® FET DATASHEET EPC2016C

EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 3

Norm

alize

d On-

Stat

e Res

istan

ce –

RDS

(on)

TJ – Junction Temperature ( ˚C )

1.7

1.8

1.5

1.6

1.4

1.3

1.2

1.1

1

0.9

0.80 25 50 75 100 125 150

ID = 11 AVGS = 5 V

Figure 8: Normalized On-State Resistance vs. Temperature

Norm

alize

d Th

resh

old V

olta

ge

0.7

0.8

0.9

1

1.1

1.2

1.3

1.4

0.60 25 50 75 100 125 150

ID = 3 mA

Figure 9: Normalized Threshold Voltage vs. Temperature

TJ – Junction Temperature ( ˚C )

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

I SD –

Sour

ce to

Dra

in Cu

rrent

(A)

6

12

18

24

30

36

25˚C125˚C

Figure 7: Reverse Drain-Source Characteristics

Capa

citan

ce (p

F)

600

500

400

300

200

100

00 20 40 60 80 100

Figure 5a: Capacitance (Linear Scale)

Capa

citan

ce (p

F)

10

100

1000

10 20 40 60 80 100

Figure 5b: Capacitance (Log Scale)V G

S – G

ate t

o Sou

rce

Volta

ge (V

)

QG – Gate Charge (nC)

5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

00 0.5 1.0 1.5 2.0 2.5 3.0 3.5

ID = 11 AVDS = 50 V

Figure 6: Gate Charge

VDS – Drain-to-Source Voltage (V) VDS – Drain-to-Source Voltage (V)

COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

VSD – Source-to-Drain Voltage (V)

All measurements were done with substrate shortened to source.

eGaN® FET DATASHEET EPC2016C

EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 4

Figure 11: Transient Thermal Response Curves

0.001

0.01

0.1

1

10-5 10-4 10-3 10-2 10-1 1 10tp - Rectangular Pulse Duration [s]

Z θJB

, Nor

mal

ized T

herm

al Im

peda

nce Duty Factors:

0.5

0.10.05

0.020.01

Single Pulse

0.2

Notes:Duty Factor = tp/TPeak TJ = PDM x ZθJB x RθJB + TB

t p P

T

DM

Junction-to-Board

0.0001

0.01

0.001

0.1

1

tp - Rectangular Pulse Duration [s]

Z θC,

Norm

alize

d The

rmal

Impe

danc

e

0.001

Junction-to-Case

Duty Factors:0.5

0.10.050.020.01

Single Pulse

0.2

Notes:Duty Factor = tp/TPeak TJ = PDM x ZθJC x RθJC + TC

t p P

T

DM

10-5 10-4 10-3 10-2 10-1 1 10

I G –

Gate

Curre

nt (m

A)

VGS – Gate-to-Source Voltage (V)

12

10

8

6

4

2

00 1 2 3 4 5 6

25˚C125˚C

Figure 10: Gate Current

eGaN® FET DATASHEET EPC2016C

EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 5

DIE MARKINGS

Figure 12: Safe Operating Area

0.1

1

10

100

0.1 1 10 100

I D- D

rain

Curre

nt (A

)

VDS - Drain-Source Voltage (V)

TJ = Max Rated, TC = +25°C, Single Pulse

Pulse Width100 ms10 ms1 ms100 μs

limited by RDS(on)

2016

YYYY

ZZZZ

TAPE AND REEL CONFIGURATION4 mm pitch, 8 mm wide tape on 7” reel

7” reel

a

d e f g

c

b

EPC2016C (note 1) Dimension (mm) target min max

a 8.00 7.90 8.30 b 1.75 1.65 1.85

c (see note) 3.50 3.45 3.55 d 4.00 3.90 4.10 e 4.00 3.90 4.10

f (see note) 2.00 1.95 2.05 g 1.5 1.5 1.6

Note 1: MSL 1 (moisture sensitivity level 1) classi�ed according to IPC/JEDEC industry standard.Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole.

Dieorientationdot

Gatesolder bar isunder thiscorner

Die is placed into pocketsolder bar side down(face side down)

Loaded Tape Feed Direction

2016

YYYY

ZZZZ

Part Number

Laser Markings

Part #Marking Line 1

Lot_Date CodeMarking line 2

Lot_Date CodeMarking Line 3

EPC2016C 2016 YYYY ZZZZ

Die orientation dot

Gate Pad bump isunder this corner

eGaN® FET DATASHEET EPC2016C

EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 6

Information subject to change without notice.

Revised August, 2019

Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.

eGaN® is a registered trademark of Efficient Power Conversion Corporation.EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx

1362

802

1632

560

180 180

X3

2106

X4

X2 3 4 5 61

2

RECOMMENDEDLAND PATTERN (units in µm)

Pad no. 1 is Gate;Pads no. 3, 5 are Drain;Pads no. 4, 6 are Source;Pad no. 2 is Substrate.*

*Substrate pin should be connected to Source

The land pattern is solder mask defined.

DIE OUTLINESolder Bar View

Side View

DIMMICROMETERS

MIN Nominal MAX

A 2076 2106 2136B 1602 1632 1662c 1379 1382 1385d 577 580 583e 235 250 265f 195 200 205g 400 400 400

B

A

d X2

c

e g

3 4 5 6

gX3

f f

2

1

X4

815

Max

100

+/- 2

0

Seating Plane

(685

)

Recommended stencil should be 4mil (100 µm)thick, must be laser cut , opening per drawing.The corner has a radius of R60

Intended for use with SAC305 Type 3 solder,reference 88.5% metals content.

Additional assembly resources available at https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx

RECOMMENDEDSTENCIL DRAWING (measurements in µm)

Pad no. 1 is Gate;Pads no. 3, 5 are Drain;Pads no. 4, 6 are Source;Pad no. 2 is Substrate. *

*Substrate pin should be connected to Source

1362

802

1632

560

180 180

2106

X2 3 4 5 61

2