es 4: introduction to vhdl
TRANSCRIPT
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ES 4: Introduction to VHDLSteven Bell29 September 2021
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By the end of class today, you should be able to:
Use VHDL to implement a boolean equation or truth table
Using a cheatsheet, write a complete VHDL entity
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VHDL vs SystemVerilog
It's kinda like MATLAB vs Python/NumPy
We're using VHDL because other courses at Tufts use VHDL
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digital designPOWER TOOLS!
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When all you haveis a hammer...
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VHDL doesn't act like C/C++
Funky assignments (y <= a or b)
Not case sensitive (INPUT_A is the same as input_a)
Lots of semicolons!
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VHDL is designed for multiple things
Design hardware you'll implement with an FPGA or ASIC process
Model hardware that you'll build with "real" components
Test designs or models for the above two scenarios
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Hierarchical modelingSpecify a circuit design by instantiating
and connecting smaller components.
Behavioral modeling TestingSpecify a design by describing its
behavior. The compiler creates a circuit
that matches the specified behavior.
Test a design by generating inputs
and verifying the corresponding outputs.
y <= a and b;
integer
unsigned
wait 10 ns;
process(clk) isif rising_edge(clk)
Non-synthesizeable
modules
process(abritrary stuff)assert CONDITION
report "A is ..."
string
Synthesizeable
modules
my_and : andgateport map(y<=y, ...)
Hierarchical and behavioral
techniques, plus:
process()
File I/O
Simulation constructs
Synthesizeable constructs
5
8d"5"
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Anatomy of a moduleRequired librarieslibrary IEEE;
use IEEE.std_logic_1164.all;use IEEE.numeric_std.all;
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Anatomy of a moduleRequired librarieslibrary IEEE;
use IEEE.std_logic_1164.all;use IEEE.numeric_std.all;
entity andgate is port( a : in std_logic; b : in std_logic; y : out std_logic );
end;
Entity declaration
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Anatomy of a moduleRequired librarieslibrary IEEE;
use IEEE.std_logic_1164.all;use IEEE.numeric_std.all;
entity andgate is port( a : in std_logic; b : in std_logic; y : out std_logic );
end;
Entity declaration
architecture synth of andgate isbegin y <= a and b;
end;
Implementation definition(architecture)
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Show and tell time
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Practice!Go to vhdlweb.com
I'll be making accounts for the class this afternoon
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1. Read the book (1.4) and complete the pre-class quiz
For Monday
3. Lab report 2 due next Wednesday (2/20)
2. Homework 3 posted tonight, due next Monday (2/18)