esd the broad impact and design challenges part2of2
DESCRIPTION
Ted Dangelmayer and Terry Welsher, of Dangelmayer Associates, present two topics involving Electrostatic Discharge (ESD) and the connection to product reliability. Please join both presentations to increase your understanding of the impact of ESD and specific considerations during product design. In this seminar, we discuss the challenges designers will be facing over the next several years. Changes in technology will continue to put pressure on designers to provide adequate protection but often without good information or tools. Highlights of the following will be covered: The shrinking design window for CMOS integrated circuits; changes in component level ESD threshold targets and the lack of availability of component information; the implications of new packaging and interconnect technologies such as through silicon vias (TSV); design of system connection and user interfaces; the use and misuse of component level ESD information for system level protection and emerging methods for co-design; and the evolution of EOS/ESD testing methods and standards.TRANSCRIPT
Part II:Challenges in the Design of
Integrated Circuits for ESD/EOSIntegrated Circuits for ESD/EOS RobustnessTerry Welsher
©2011 ASQ & Presentation TerryPresented live on Jul 07th, 2011
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professionals.
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Terry Welsher www.dangelmayer.com
Part II: Challenges in the Design of Integrated Circuits
for ESD/EOS Robustness
Copyright © 2011 Dangelmayer Associates
Outline • Factory Control vs. Device Protection • ESD Threshold Roadmap Revisited
• Industry Council on ESD Targets
• Changes in Design Targets • 2000 volts HBM • CDM Challenges • “Machine” Model
• System Level Issues
• EOS
p2
Copyright © 2011 Dangelmayer Associates
ESD Control and Protection
Device Sensitivity w/o protection circuits
10
10000
1000
100
Ele
ctro
stat
ic V
olta
ge
Range of Events Occurring without Static Controls
Events with Ordinary Controls
Cla
ss 0
Device Sensitivity with Protection Circuitry
MR Head Sensitivity Advanced Controls
Control Protection
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ESD Sensitivity Trends - Revisited
p4
Copyright © 2011 Dangelmayer Associates
ESDA Technology Roadmap
p5
HBM Roadmap (Min-Max)
1978 1983 1988 1993 1998 2003 2008
4kV
2kV
6kV
ESD Control is becoming increasingly critical!
0V
1kV
ESD Control Methods
2013
HBM Roadmap (Min-Max)
1978 1983 1988 1993 1998 2003 2008
4kV
2kV
6kV
ESD Control is becoming increasingly critical!
0V
1kV
ESD Control Methods
2013
Copyright © 2011 Dangelmayer Associates
Typical IC With Protection Circuitry
Functional Circuitry
Protection Circuits Protection Circuits Constrained or Omitted By:
• Technology Node Feature Sizes
• Circuit Functionality
• I/O Density
• Circuit Speed Requirements
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ESDA Technology Roadmap
p7
CDM Roadmap (Min-Max)
1978 1983 1988 1993 1998 2003 2008
750V
1000V
ESD Control is becoming increasingly critical!
0VESD Control Methods
2013
500V
250V
125V
CDM Roadmap (Min-Max)
1978 1983 1988 1993 1998 2003 2008
750V
1000V
ESD Control is becoming increasingly critical!
0VESD Control Methods
2013
500V
250V
125V
Copyright © 2011 Dangelmayer Associates
Copyright © 2011 Dangelmayer Associates
Misuse of ESD Classifications Classification Voltage Range (V)
0A < 125
0B 125 to < 250
1A 250 to < 500
1B 500 to < 1000
1C 1000 to < 2000
2 2000 to < 4000
3A 4000 to < 8000
3B ≥ 8000
There is no industry standard for tailoring control procedures according to these levels
Copyright © 2011 Dangelmayer Associates
Industry Council on ESD Target Levels
Mission • Review the ESD robustness requirements of modern IC products
to allow safe handling in an ESD protected area.
• While accommodating both the capability of the manufacturing sites and the constraints posed by downscaled process technologies on practical protection designs, the Council provides a consolidated recommendation for future ESD target levels.
• The Council Members and Associates promote these recommended targets for adoption as company goals.
• Being an independent entity, the Council presents the results and supportive data to all interested standardization bodies.
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Industry Council on ESD Target Levels
Copyright © 2011 Dangelmayer Associates
Industry Council White Papers
• White Paper 1: A Case for Lowering Component Level HBM/MM ESD Specifications and Requirements.
• White Paper 2: A Case for Lowering Component Level CDM ESD Specifications and Requirements
• White Paper 3: System Level ESD Part I: Common Misconceptions and Recommended Basic Approaches
Copyright © 2011 Dangelmayer Associates Industry Council 13
Challenge and Effort of Meeting ESD Level Requirements
130nm 90nm 65nm 45nm 32nm 22nm
Maintain
@2kV HBM
Design @1kV HBM
Meet Safe Handling Level
Requ
ired
Effo
rt an
d Re
sour
ces
2001 2003 2005 2008 2010 2014
Tech. Node
Qualification Year
Reducing to 1kV will alleviate a lot of ESD effort but as technologies are scaled down further the challenge will continue…
Copyright © 2011 Dangelmayer Associates
Effo
rt to
Ach
ieve
Hig
h Yi
eld
HBM Level 16 kV
Basic ESD Control
500V 1 kV
Cost of ESD Control
2 kV
The cost of ESD control does not increase for 2kV or 500V devices
Copyright © 2011 Dangelmayer Associates
Industry Council
15
Where is the data?
Ø ESD/EOS failures as provided by various members of the Industry Council
Ø Includes both automotive products and consumer ICs
Ø A vast majority of the returns are often found to be due to EOS
Ø Total return rate due to EOS/ESD fails < 1 dpm
Ø No obvious correlation of EOS/ESD returns to HBM levels of 500 V … 2 kV 500 1000 1500 2000
1E-4
1E-3
0,01
0,1
1
HBM robustness
all devices
9.3
billi
on s
old
witj
2kV
HB
M
0.7
billi
on s
old
with
1.5
kV H
BM
5.7
billi
on s
old
with
1kV
HB
M
4.8
billi
on s
old
with
500
V H
BM
based on 21 billion devices
1 dpm line
"EO
S/ES
D"
fails
per
mill
ion
devi
ces
This data represents products shipped at various ESD levels with the same basic factory control
Copyright © 2011 Dangelmayer Associates November 2010 Industry Council 16
Conclusion for HBM
• 2 kV HBM design is frequently causing unnecessary qualification delays across the technologies
• HBM qualification levels between 500 V and 2 kV exhibit the same level of manufacturing quality and field robustness
• Targeting 1kV HBM is safe and is proven to provide margin*
*AT&T used a 500 volt requirement starting in 1988 with no HBM problems
Copyright © 2011 Dangelmayer Associates
Copyright © 2011 Dangelmayer Associates
FICBM vs. FICDM Discharge Waveformsfor DSP with a 250V Charge Voltage
-2
0
2
4
6
8
10
0.00
0.25
0.50
0.75
1.00
1.25
1.50
Time (nanoseconds)
Peak
Cur
rent
(Am
ps) GND test pad FICBM
GND pin FICDM
CBE vs. CDM Discharge Waveform Comparison
(250 V)
Courtesy: Andrew Olney, Quality Director, Analog Devices
Copyright © 2011 Dangelmayer Associates
Copyright © 2011 Dangelmayer Associates
CDM Peak Current Dependence on Pin Count
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CDM Threshold Dependencies
Ref: Industry Council WPII 2009
Larger Device Package Size
Higher Operating Speeds
p21
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Conclusions for CDM
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Machine Model evolved from HBM
HBM MM Simple Plug-In Module for Existing HBM Tester
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MM Relation to HBM, CDM
Ø To avoid high charging voltages from the HBM test, MM* was thought to be a good substitute with lower pre-charging voltage but with equivalent current stress. Ø There was really no intention to address any different failure mechanisms to HBM. Ø In the vast majority of cases, analyses between HBM and MM show the same damage sites Ø This is in contrast to CDM, where the rise time is much faster – often leading to voltage drops and typically resulting in unique oxide failures
24
*It isn’t clear when the name “machine” was attached to this model.
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HBM 3.5kV
Electrical signatures for both HBM and MM failures: Increase in leakage; Site of damage: ESD Diode
MM 230V Failure Analysis on Same I/O Pin for Both HBM and MM Stress
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MM Relation to HBM, CDM
Ø It was also wrongly assumed that it models the fast discharge from or to a metal surface better than the HBM test. Ø Meanwhile, it is now known that fast discharges are reproduced best by CDM. Ø Field failures due to ESD are rare, and if any do occur they often can be correlated to weak CDM protection design or poor control of static charges in manufacturing
26
The root cause of almost all ESD failures of ICs is either poor CDM design and poor CDM controls in factories.
Copyright © 2011 Dangelmayer Associates
JEDEC’s New Official Position on MM:
JESD22-A115C is a reference document; it is not a requirement per JESD47G. Machine Model as described in JESD22-A115C should not be used as a requirement for IC ESD Qualification. Only HBM and CDM are the necessary ESD Qualification test methods as specified in Stress Test Driven Qualification of Integrated Circuits (JESD47G).
Copyright © 2011 Dangelmayer Associates
Typical Set-Up: IEC 61000-4-2 System Level ESD
GRP
0,1 minsulatingsupport
EUT
Groundstrap
Metallic part
Wall outlet
ESDgenerator
ESD tipperpendicular
to EUT surface
≥ 0,6 m
≥ 1 m
≥ 1 m
0,03 m
Insulating foam
Copyright © 2011 Dangelmayer Associates Industry Council 2010
ESD Testing
• Component ESD testing (i.e., HBM and CDM) of ICs is intended to ensure that ICs survive the manufacturing process inside ESD Protected Areas (EPA).
• System level ESD testing is intended to ensure that finished products can continue normal operation during and after a system level ESD strike. – The IEC ESD Test Method is used to represent one particular
scenario of a charged human holding a metal object to discharge. This is a common test method used to assess the ESD robustness of the system
– Other test standards(e.g., ISO10605, DO-160) are used depending on the application
§ How does one test for ESD robustness?
Copyright © 2011 Dangelmayer Associates Industry Council 2010
Industry Wide Problem There is a prevailing misunderstanding
between IC Suppliers and System Level Designers :
• ESD test specification requirements of system vs. component
providers; • Understanding of the ESD failure / upset mechanisms and
contributions to those mechanisms, from system specific vs. component specific constraints;
• Lack of acknowledged responsibility between system designers and component providers regarding proper system level ESD protection for their respective end products.
OEMs are attempting to use component ESD information as an indicator of system level performance!
Copyright © 2011 Dangelmayer Associates Industry Council 2010
Component Vs. System Test Results – Poor Correlation
Analysis of system failure case studies having both HBM and IEC data indicates no correlation of HBM failure voltage to IEC failure voltage.
Copyright © 2011 Dangelmayer Associates Industry Council 2010
Component ESD Versus System ESD • HBM/CDM and IEC are completely different tests, and thus there is a clear lack of correlation between the two methods
• High levels of HBM performance do not ensure that system ESD robustness can be achieved
• In fact in some cases, a high level of HBM performance can be a detrimental to optimum design of system protection
Copyright © 2011 Dangelmayer Associates Industry Council 2010
Differentiation of Internal Vs. External Pins
bus
conn
ecto
r
Inte
rchi
p
Printed Circuit Board
IC
IC
IC
IC
Internal External
• Internal Pins and External Pins should meet minimum HBM and CDM levels
• External Pins must be designed for proper system ESD protection
Copyright © 2011 Dangelmayer Associates Industry Council 2010
Designing for the Overall System
External Clamps
• The HBM and CDM levels are important only for component handling
• System ESD protection design involves an understanding of the system
Copyright © 2011 Dangelmayer Associates Industry Council 2010
System-Efficient ESD Design (SEED) Concept
• For an efficient system protection design, the IC pin breakdown characteristics play a critical role
• With this type of understanding, effective IEC protection design can be achieved for any IC pin that interfaces with the external world
External TVS
IC IEC
clamp
PCB With Components
External Component Response Characterization linked to the IC Pin’s Transient Characteristics
Copyright © 2011 Dangelmayer Associates Industry Council 2010
External TVS
External Pin
PCB With Components IC
SEED Concept Details
IEC
Board Component Design
Residual Pulse Stress
TLP Information
1. IC Supplier provides Transmission Line Pulse (TLP) data on the Interface Pin
2. Board Designer characterizes the Transient Voltage Pulse (TVP) to determine the Residual Pulse Stress (RPS) data (Voltage Vs. Time)
3. Board components are adjusted to balance the RPS data to the TLP data
clamp
Slide 37 37
Electrical Overstress (EOS) and Safe Operating Area (SOA)
P
Time to failure
EOS Area ESD Area
Over voltage tends to damage breakdown sites. Over current tends to fuse interconnects. Over power tends to melt larger areas. EOS: Wide spreading of heat resulting in large areas of damage. ESD: Heat does not disperse much causing localized failures.
SOA
I
V
Current limit
Voltage limit
Power limit
causing localized failures.
age tends to damage breakdown sites. Over current tends to fuse interconnects. Over power tends to melt larger areas. EOS: Wide spreading of heat resulting in large areas of damage.
Over voltage tends to damage breakdown sites. Over current tends to fuse interconnects. Over power tends to melt larger areas. EOS: Wide spreading of heat resulting in large areas of damage. ESD: Heat does not disperse much causing localized failures.
Sources of EOS from Power
" High ground impedance (inductive coupling) " Ground loops " Improper power wiring " DC voltage from tools in automated
equipment " DC voltage from ungrounded floating metal " Faulty soldering irons and power tools " Faulty power adaptors " Hot plug-in and faulty power sequencing " Wirebonding
p38 Copyright 2010, Dangelmayer Assoc. & Semitracks Inc.
EOS Control and Design
" Unlike ESD, formal EOS prevention, monitoring and auditing systems are not common in manufacturing
" Like ESD, EOS failures are often the result of lack of awareness of the problem
" Like ESD, many stakeholders n Product design n Test and Production equipment design n Facility design and maintenance n Quality/process control
" Unlike ESD, no standard tests, no standard design
39 Copyright 2010, Dangelmayer Assoc. & Semitracks Inc.
Copyright © 2011 Dangelmayer Associates
Questions? Contact information:
Ted Dangelmayer Terry Welsher 978 282 8888
[email protected] www.dangelmayer.com
ESD Training Event: DA ESD Workshop July 26th , 27th and 28th Cape Ann, Massachusetts