etch development for e-mode gan power hemt fabrication...

© IMEC 2014/ CONFIDENTIAL

ETCH DEVELOPMENT FOR E-MODE GaN POWER HEMT FABRICATION

G. MANNAERT, V. PARASCHIV*, B. DE JAEGER, M. VAN H OVE, V. PARASCHIV,

S. DECOUTERE, K. XU

IMEC, KAPELDREEF 75, LEUVEN, B-3000, BELGIUM

* S.C. ETCH TECH SOLUTIONS, STR. OANCEA 3 B1 D10 AP T. 2, IASI, ROMANIA

© IMEC 2014/ CONFIDENTIAL 2© IMEC 2014 G. MANNAERT

BACKGROUND

Applications:

• consumer electronics

• telecommunication

• AC/DC converters

• solar/wind power systems

Why GaN instead of Si ?

• High electron velocity� devices @ high speed

• High breakdown field� devices @ high voltage

• High thermal conductivity� devices @ high temperature

GaN has a wide band gap:3.4 eV vs 1.1 eV for Si

GaN has a higher e- mobility:2000 vs 1450 (cm2/V-sec) for Si

GaN is quite inert and wet etching is limited

© IMEC 2014/ CONFIDENTIAL 3© IMEC 2014

OUTLINE

� background GaN etch

� GaN high power transistor

� concept 1: MISHEMT

- Controlled barrier recess: concept + results

� concept 2: pGaN HEMT

- Selective pGaN/AlGaN etch: concept + results

� Conclusions

G. MANNAERT


Bond Strength

Ga-Ga 33+-5 kcal/mol

Ga-O 14.7eV

Ga-N 8.9 eV

Ga-As 6.5 eV

Al-N 11.52 eV

Al-O 21.2 eV

In-N 7.72 eV

BACKGROUND- GaN ETCH

• Bond strength: Ga-O/Al-O >> Ga-N� Important for selective etch

G. MANNAERT

• GaCl3 mainly formed during etch:� GaCl3 more stable than GaCl2• GaF3 is very non-volatile

Etch tool : LAM Versys2300 TCP (ICP) reactor


GaN POWER (E-MODE) TRANSISTOR- ZOOM IN

5

Source DrainGate

GaN

Al Ga Nx 1-x

PSP

PSPPPE

Si N3 4

Al Ga N buffer-layersx 1-x

Silicon wafer

AlN nucleation layer

Ohmic (metal: Al)

Ohmic(metal:Al)

passivation

large gate-draindistance

Gate metal/dielectric

thick (2-3 µm) buffer

HEMT: High Electron Mobility transistorMISHEMT: Metal-Insulator-Semiconductor High Electron Mobility Transistor

40 – 150 nm channel

10 - 20 nm barrier20 – 25% (Al)GaN

2-DEG

Gate dielectricum: SiN/Al2O3Gate metal: Ti/TiN – Al- Ti/TiN

G. MANNAERT


CONCEPT 1: MISHEMT

GaN Channel

AlGaN barrier

AlN Spacer

Gate Metal

Stack

GaN cap

SiN

Gate Dielectric

Recessed Barrier

2DEG

Concept 1: Barrier Recess Principle: suppressing 2-DEG formation below gate area by recessing the barrier � E(nhancement)-mode device if Vth > 0 is applied to the gate electrode

Etch requirements:• Very low/controllable AlGaN barrier etch

rate • Minimal surface roughness• Clean Surface • Low non-uniformity

G. MANNAERT


CONTROLLED BARRIER RECESS- ALE (ATOMIC LAYER ETCH)*

G. MANNAERT

*reference: US patent 8.124.505: Two stage plasma etching method for E-mode GaN HFET

Linear behaviour of the ALE etch depth vs. number of ALE cycles

- BCl3 etches oxidized AlGaN almost 2 timesfaster than the non-oxidized layer.- GaN and AlGaN etches substantially identicallybecause the Al does not prevent the oxidation orthe etching by BCl3.- The thickness of the oxide layer in theAlGaN/GaN material depends on the plasmapower used to oxidize the material.

Alternating self-limiting oxidation and etchstep

© IMEC 2014/ CONFIDENTIAL 8© IMEC 2014 G. MANNAERT

R² = 0,9371

0

5

10

15

20

25

0 5 10 15 20 25

dept

h (n

m)

# cycles

AlGaN etch depth (nm) afo # cycles

10 cycles

SiN

AlGaN

15 cycles

20 cycles

SiN etch (SF6) + PR strip + #cy(90” oxidation (O2) / 30” BCl 3 etch ) + wet clean

Minimum oxidation time = 60 s Etch rate = 1.1 nm/cycle

140nm SiN

10nm Al0.25GaN

150nm GaN

1nm AlN

2nm GaN cap

~1.5 um

Test wafers:

CONTROLLED BARRIER RECESS- RESULTS


14.5 nm

CONTROLLED BARRIER RECESS- INTEGRATED RESULTS13 cycles + wet clean

G. MANNAERT

Sloped recess

140nm SiN

15nm Al0.25GaN

150nm GaN

3nm GaN

GateMetl

GateDiel

60˚

45˚

To be investigated:• Effect of wet clean• Effect of pressure in dry etch• Effect of gas additive Cl2, SF6,

CH3F

Tilted top down SEM

AlGaN barrier

SiN


CONCEPT 2: P-GaN HEMT

Concept 2: p-GaN etch(stacked etch)

GaN Channel

AlGaN barrier

AlN Spacer

Gate Metal

Stack

GaN cap

2DEG

in-situ P-GaN

Principle: Mg-doped GaN locally lifts up conduction band below gate area unless Vth >0 is applied to the gate electrode (E-mode)

Etch requirements:• high selective p-GaN/AlGaN etch

process.• Minimal Surface roughness• Clean surface • Low non-uniformity

Parameters that affect the etch result:• presence of photoresist• HM nature (oxide or nitride)• % of Al in AlGaN barrier• Chamber conditioning (CWAC)

PR based pGaN etch

G. MANNAERT


BCl3/SF6 ICP plasma**

**SELECTIVE DRY ETCHING OF GaN OVER AlGaN IN BCL3/SF6 MIXTURESD. BUTTARI, A. CHINI, A. CHAKRABORTY, L. MCCARTHY, H. XING,T. PALACIOS, L. SHEN, S. KELLER, AND U. K. MISHRADepartment ofElectrical and Computer Engineering,University ofCalifornia Santa Barbara, Santa Barbara, California 93106, U.S.A.

Cl2/O2/N2 ICP plasma*

*Highly Selective Dry Etching of GaN over AlGaN Using Inductively Coupled Cl2/N2/O2 PlasmasJpn. J. Appl. Phys. Vol. 42 (2003) pp. L 1139–L 1141Part 2, No. 10A, 1 October 2003The Japan Society of Applied Physics

HIGHLY SELECTIVE PGaN ETCH- LITERATURE*/**

G. MANNAERT

© IMEC 2014/ CONFIDENTIAL 12

Cl2/O2/N2 PLASMA- 1-STEP RESULT

GaN

AlGaNp-GaN

TiN

SiN

75% over-etch- No wet clean

IB3 = GaCl3 = 335 nm

G. MANNAERT

150nm GaN Channel

15nm 25%AlGaN

Gate Metal ~ 100 nm TiN

2DEG

~ 100nm P-GaN

HM 150 nm SiN

PR 860 nm


= 21:1P-GaN removed everywhereEtch rate pGaN:AlGaN = 21:1

Cl2/O2/N2: PROCESS WINDOW- OVER ETCH VARIATION

G. MANNAERT

SiNTiN

p-GaNAlGaN

GaN

huge p-GaN thickness variation: - 73 nm to 124 nm� Target 100 nm

GaN

SiN hardmask

TiN

p-GaNAlGaN

GaN

SiN

TiN

p-GaNAlGaN

75% over-etch 125% over-etch >300% over-etch

• Micro-trenching

• pitting

GaN

SiN

TiN

p-GaN

AlGaN


Cl2/O2/N2: PROCESS WINDOW - OXYGEN FLOW VARIATION

14

• No selectivity• Micro-

trenches/pitting

• Improved selectivity • Some micro-

trenches• p-GaN etch rate

~ 192nm/min

• Lower p-GaN etch rate ~ 30 nm/min

Ga-O bond formation:bond strength Ga-O >> Ga-N (etch stop !)

GaN

AlGaNp-GaN

TiNSiN

GaN

AlGaNp-GaNTiN

SiN

GaNAlGaNp-GaNTiN

SiN

G. MANNAERT

3 sccm O2 -120” 5 sccm O2 -120” 7 sccm O2 -100”


Cl2/O2/N2: PROCESS WINDOW - BIAS VOLTAGE VARIATION

80 Vb - 120” 40 Vb - 180”

G. MANNAERT

• reduced p-GaN etch rate

Not sufficient ion E to brake the Ga-O and Ga-N bond resulting in Etch stop !

© IMEC 2014/ CONFIDENTIAL 16© IMEC 2013 / CONFIDENTIAL

Cl2/O2/N2 PLASMA - MICRO-MASKING/ROUGHNESS

Etched @ EP – no over etch

AlGaNpGaN

Over etched

G. MANNAERT

*J. Ladroue, et al., “Deep GaN etching by ICP and induced surface defects”, J. Vac. Scie Technology A28 (5), Sep/Oct 2010 p1226

Mechanism*Our observation:


Cl2/O2/N2 PLASMA - MICRO MASKING / ROUGHNESS OPTIMIZATION

ME-step only: BCl3/Cl2/Ar

• Remove TiNresidue’s

• De-oxidize GaN

� Introduce main etch + selective over etch:� introduce CWAC !

SiN HM

TiN

P-GaN

Tune BCl3/Cl2

ratio

• Improved side wall protection

• avoid micro-trenching • reduce lateral TiN attack • Etch rate ~ 29.5 nm/minG. MANNAERT


Cl2/O2/N2 PLASMA SURFACE ROUGHNESS- MAIN ETCH + SELECTIVE OVER ETCH

GaN

AlGaN

p-GaN

TiN

SiN

1-steps: Cl2/O2/N2(wet clean)

GaNAlGaN

p-GaN

TiN

SiN

GaN

AlGaN

p-GaN

TiN

SiN

2-steps: ME: BCl3/Cl2/ArOE: Cl2/O2/N2(wet clean)Main etch

Sel. etch

Main etch + Purge + Sel. etch

2

Increase O2

Reduce

power

Reduce TCP

power

• Ar Purge step after main etch to remove BCl3

� BCl3 reduces available oxygen

• reduce active Cl content

2-steps: ME: BCl3/Cl2/ArOE: Cl2/O2/N2 (10% O2)(wet clean)

2

Increase N2

2

Increase O2

2

Decrease Cl2

• Increase O2 flow for improved selectivity

• Decrease Cl2 / increase N2 flow for improved surface morphology

• AlGaN loss observed 2 to 4 nm


CONCLUSIONS

� 2 E-mode device concepts have been proposed

� both concepts require particular etch development:

- ALE approach: slow, very controllable etch rate based on alternating oxidation/etch cycle

- Selective etch of pGaN/AlGaN: addition of O2 (or SF6) small process window – CWAC !AlGaN micromasking defects and surface roughness

� contribution of hard mask choice (effect of Si sputtering)

� both concepts resulted in working E-mode power transistors

G. Mannaert

Ids-Vds Power transistor

Vgs=8V


THANKS FOR YOUR ATTENTION !

etch development for e-mode gan power hemt fabrication...

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