Datasheet

TxFC(Mem)

RxFC(Mem)

Select

TxFC RxFC

DMACSR

OMRReg.

AXI/AHB

MasterInterface

AXI/AHB/APBSlave

Interface

DMAOptional

PHYinterfaces

RGMII/RTBI/TBI/

SGMII/SMII/RMII

GMAC

MACCSR

GMII/MII

DesignWare CoresEthernet MAC 10/100/1000 Universal

OverviewThe DesignWare Ethernet MAC 10/100/1000 Universal intellectual property (IP) core implements the link layer of an OSI Ethernet system. The silicon-proven core is configurable and scalable to meet multiple Ethernet application requirements.

` Optimal architecture provides low latency and low gate count ` Configurable to include only the features required for your application ` Configurable to accommodate different system architectures ` Supporting new Audio Video and Energy Efficient Ethernet applications

Synopsys offers a high-quality IP solution that is in volume production and has been successfully implemented in a wide range of applications.

` Switch/Router ` Set-top Boxes ` Network Processors ` Network Storage ` Network Appliances ` Industrial Controllers

Benefits

High-Performance Architecture

The DesignWare Ethernet MAC 10/100/1000 Universal core is designed to support

high-performance applications such as routers and network storage applications.

This is accomplished by removing any latency associated with configurable IP.

Typical design of configurable IP results in multiple layers that are bridged during

configuration. This results in many unnecessary latencies due to double buffering of

data as it crosses from one layer to another. The coreConsultant configuration tool

removes such latencies at configuration time, thus providing high-performance IP.

Fully Configurable Core

The DesignWare Ethernet MAC 10/100/1000 Universal core is highly configurable

and reduces integration time, gate count and power consumption. Features such as

data bus widths, FIFO depths, DMA integration or interface types are readily defined

during integration. Moreover, unused features do not result in any gate penalty thus

minimizing gate count and power consumption.

Figure 1: DesignWare Ethernet MAC 10/100/1000 Universal Block Diagram

DesignWare Cores 2

General Features ` Compliant with IEEE 802.3-2005 standard ` Support for IEEE 1588-2002 and IEEE 1588-2008 standards for precision

networked clock synchronization

` Supports IEEE 802.1-AS, version D6.0 and IEEE 802.1-Qav, version D6.0 for

Audio Video (AV) traffic

y Supports separate channels or queues for AV data transfer in 100

Mbps and 1000 Mbps modes

y Supports configuring up to two additional channels (Channel 1 and

Channel 2) on transmit and receive

paths for AV traffic

y Supports IEEE 802.1-Qav specified credit-based shaper (CBS) algorithm

for additional transmit channels

y Provides separate DMA, TxFIFO, and RxFIFO (MTL) for each additional

channel while maintain the system-

side interface (AHB, AXI, or native)

` Supports IEEE 802.3-az, version D2.0 for Energy Efficient Ethernet (EEE)

` Supports AMBA 2.0 for AHB Master/Slave ports

` Supports AMBA 3.0 for AXI Master/Slave ports

MAC Features ` Configurable to support data transfer rates of:

y 10/100/100 Mbps y 10/100 Mbps only y 1000 Mbps only ` Supports both full-duplex and half-duplex operation

y IEEE 802.3x flow control automatic transmission of zero-quanta pause

frame on flow control input de-assertion.

y Optional forwarding of received pause control frames to the user

application

y Supports CSMA/CD Protocol for half-duplex operation

y Supports packet bursting and frame extension in 1000 Mbps half-duplex

operation

y Back-pressure support for half-duplex operation

` Preamble and start-of-frame data (SFD) insertion in Transmit, and

deletion in Receive paths

` Automatic CRC and pad generation controllable on a per-frame basis

` Options for Automatic Pad/CRC Stripping on receive frames

` Programmable frame length to support Standard or Jumbo Ethernet

frames with sizes up to 16 KB

` Programmable InterFrameGap (40-96 bit times in steps of 8)

` Supports a variety of flexible address filtering modes:

y Up to 31 additional 48-bit perfect (DA) address filters with masks for

each byte

y Up to 31 48-bit SA address comparison check with masks for

each byte

y 64-bit Hash filter (optional) for multicast and uni-cast (DA)

addresses

y Option to pass all multicast addressed frames

y Promiscuous mode support to pass all frames without any filtering for

network monitoring

y Passes all incoming packets (as per filter) with a status report

` Separate 32-bit status returned for transmission and reception packets

` Supports IEEE 802.1Q VLAN tag detection for reception frames

` Separate transmission, reception, and control interfaces to the Application

` Configurable big endian and little endian support for transmission and

reception data paths

` Supports 32/64/128-bit data transfer interface on the system-side

PHY InterfacesThe GMAC-UNIV supports any one

or a combination of the following PHY

interfaces:

` Gigabit Media Independent Interface (GMII)

` Media Independent Interface (MII)

` Reduced GMII (RGMII) ` Serial GMII (SGMII) ` Ten Bit Interface (TBI) ` Reduced MII (RMII) ` Serial MII (SMII) ` Reduced TBI (RTBI) ` Reverse MII (RevMII)

Transaction Layer (MTL) Features ` 32, 64, or 128-bit Transaction Layer block providing a bridge between the

application and the GMAC-CORE

` Single-channel Transmit and Receive engines

` Data transfers executed using simple FIFO-protocol

` Synchronization for all clocks in the design (Transmit, Receive and system

clocks)

` Optimization for packet-oriented transfers with frame delimiters

` Four Separate ports for system-side and GMAC-CORE-side transmission

and reception

` Two 2-port RAM-based asynchronous FIFOs with synchronous/asynchronous

Read and Write operation with respect

to the Read and Write clocks (one for

transmission and one for reception)

` FIFO instantiation outside the top-level module to facilitate memory testing/

instantiation

` Supports 128-, 256-, or 512-byte, or 1-, 2-, 4-, 8-, 16-, or 32-KB receive

FIFO depths on reception.

` Optional interface to indicate the length of a received frame at the top

of the MTL Rx FIFO in the GMAC-MTL

configuration

` Programmable burst-length support for starting a burst up to half the size

of the MTL Rx and Tx FIFO in the

GMAC-MTL configuration

` Receive Status vectors inserted into the Receive FIFO after the EOF

transfer enables multiple-frame

storage in the Receive FIFO without

requiring another FIFO to store those

frames Receive Status.

DesignWare Cores 3

` Configurable Receive FIFO threshold (default fixed at 64 bytes) in Cut-

Through mode

` Option to filter all error frames on reception and not forward them to

the application in Store-and- Forward

mode

` Option to forward under-sized good frames

` Supports statistics by generating pulses for frames dropped or

corrupted (due to overflow) in the

Receive FIFO

` Supports 256- or 512-byte, or 1-, 2-, 4-, 8-, or 16-KB FIFO depth on

transmission

` Supports Store and Forward mechanism for transmission to the

GMAC core

` Supports threshold control for transmit buffer management

` Supports configurable number of frames to be stored in FIFO at any

time. The default is 2 frames (fixed)

with internal DMA, and up to 8 frames

in GMAC-MTL configuration.

` Automatic generation of PAUSE frame control or backpressure signal to the

GMAC core based on Receive FIFO-fill

(threshold configurable) level.

` Handles automatic retransmission of Collision frames for transmission

` Discards frames on late collision, excessive collisions, excessive

deferral and underrun conditions

` Software control to flush Tx FIFO ` Data FIFO RAM chip-select disabled when inactive, to reduce power

consumption

` Optional module to calculate and insert IPv4 header checksum and TCP,

UDP, or ICMP checksum in frames

transmitted in Store-and-Forward

mode

DMA Block Features ` Supports 32/64/128-bit data transfers ` Supports single-channel Transmit and Receive engines

` Provides fully synchronous design operating on a single system clock

(except for CSR module, when a

separate CSR clock is configured)

` Provides optimization for packet-oriented DMA transfers with frame

delimiters

` Supports byte-aligned addressing for data buffer support

` Supports dual-buffer (ring) or linked-list (chained) descriptor chaining

` Supports descriptor architecture that allows large blocks of data transfer

with minimum CPU intervention; each

descriptor can transfer up to 8 KB of data

` Supports comprehensive status reporting for normal operation and

transfers with errors.

` Supports individual programmable burst size for Transmit and Receive

DMA Engines for optimal host bus

utilization.

` Supports programmable interrupt options for different operational

conditions. Provides per-frame

Transmit/Receive complete interrupt

control

` Supports round-robin or fixed-priority arbitration between Receive and

Transmit engines.

` Supports Start/Stop modes ` Provides separate ports for host CSR access and host data interface.

AHB Master Interface Features ` Interfaces with the application through AHB

` Supports little-endian and big-endian modes

` Supports 32-bit, 64-bit, or 128-bit data on the AHB Master port

` Provides option to select address-aligned bursts from AHB Master port

` Supports Split, Retry, and Error AHB responses

` Handles the AHB 1K boundary burst splitting

` Does not generate wrap burst ` Software can select the type of AHB burst (fixed burst, indefinite burst, or

mix of both)

AHB Slave Interface Features ` Interfaces with the application through AHB

` Supports little-endian and big-endian modes

` AHB Slave interface (32-bit, 64-bit, or 128-bit) for CSR access, in which

only 32-bit or less (byte, half-word)

accesses are possible

` Provides option for a 32-bit APB port for CSR access instead of an AHB

Slave port

` Supports all AHB burst types ` Does not generate Split, Retry, or Error responses

AMBA AXI Master Interface Features ` Interfaces with the application through AXI

` Supports 32-bit address width ` Supports little-endian and byte-invariant big-endian modes

` Supports AXI low-power interface ` Supports 32-bit, 64-bit, or 128-bit data ` Supports OKAY, SLVERR, and DECERR responses

` Software can select the type of AXI burst (fixed and variable length burst)

in the AXI Master interface with an

option to select extended length fixed

bursts of 32, 64, 128, and 256.

` Provides an option to select address-aligned bursts

` Handles the AXI 4K boundary burst splitting

` Supports up to 16 read and write outstanding transactions

` Supports using posted writes from the AXI Master interface to maximize

the bus utilization

DesignWare Cores 4

AMBA AXI Slave Interface Features ` Interfaces with the application through AXI

` AXI Slave interface (32-bit, 64-bit, or 128-bit) for CSR access

` Supports 32-bit address width ` Supports little-endian and byte-invariant big-endian modes

` Provides option for a APB or AHB Slave port for CSR access instead of

AXI Slave port

` Supports narrow burst and FIXED/INCR burst

Functional DescriptionThe DesignWare Ethernet MAC

10/100/1000 Universal core simplifies

system-on-chips (SoC) implementation

efforts by providing designers with

a highly configurable IP with ample

features to fit different architectures.

The IP is configured using the Synopsys

coreConsultant configuration tool. The

coreConsultant tool enables designers

to choose types of interfaces, specify

different architectures and optimize

other variables.

Packet Handling The DesignWare Ethernet MAC

10/100/1000 Universal core handles

preamble generation and removal.

32-bit CRC generation and checking

is performed automatically to verify

data integrity. Insertion and stripping

of padding bytes on transmission and

reception are also available. To minimize

system overhead, the flexible address

filter scheme enables data filtering in

the network that is not addressed to the

node in which it resides.

Industry-Standard Interfaces Using the coreConsultant the

DesignWare Ethernet MAC 10/100/1000

Universal core may be configured to any

of the following:

` MAC Layer Only ( MAC/GMAC)

` MAC layer with a FIFO layer (MAC-MTL; GMAC-MTL)

` MAC Layer with a FIFO layer and a DMA (MAC-DMA; GMAC-DMA)

` MAC Layer with a FIFO layer and a DMA with an AHB interface (MAC-

AHB; GMAC-AHB)MAC Layer with

a FIFO Layer and a DMA with AXI

Interface (MAC AXI; GMAC AXI)

In addition, the PHY interface can be

configured to have one or more of the

supported PHY interfaces.

In the case of support for multiple PHY

interfaces, a MUX is instantiated as well.

Network Management Support The DesignWare Ethernet MAC

10/100/1000 Universal core includes

configurable counters (16 or 32 bit)

for a number of network management

protocols, including Remote Monitoring

(RMON), Simple Network Management

Protocol (SNMP), and Ethernet-Like.

These counters track events such as the

number of CRC errors, the number of

network collisions, and the number of

Runt frames.

Checksum Offload EngineThe DesignWare Ethernet MAC

10/100/1000 Universal core detects

IPv4/IPv6 payload in received Ethernet

frames and verifies whether or not

the IPv4, TCP, UDP or ICMP header

checksums are correct. Similarly, it

can calculate and insert the IPv4, TCP,

UDP or ICMP header checksums in the

appropriate locations in the transmitted

frames.

IEEE 1588 SupportThe DesignWare Ethernet MAC core

provides support for capturing the time-

stamp of frames transmitted or received

at the PHY interface. The time-stamps

for the frames are provided in the

corresponding frame-status at the end

of the frame transfer. The captured time-

stamp can have a resolution up to 1 ns.

When configured for IEEE 1588-2008

mode automatically identifies received

PTP packets and provide time-stamps

for the valid PTP packets defined for

that node.

Verification Environment The DesignWare Ethernet MAC

10/100/1000 Universal core is delivered

with a test environment that verifies its

functionality in compliance with the IEEE

specifications. The test environment

includes a GMII bus functional model

and a GMII monitor to facilitate system-

level testing. The GMII model drives

gigabit Ethernet traffic on the GMII bus,

while the GMII monitor reports protocol

violations.

Power ManagementSupports advanced power management

including:

` Wake-on-LAN ` AMD Magic Packet ` IEEE 802.3az Energy Efficient Ethernet

` UPF

Monitoring, Testing, and Debugging Support ` Supports internal loopback on the GMII/MII for debugging

` Provides DMA states (Tx and Rx) as status bits

` Provides Debug status register that gives status of FSMs in Transmit and

Receive data-paths and FIFO fill-levels

` Application Abort status bits ` MMC (RMON) module in the GMAC core

` Current Tx/Rx Buffer pointer as status registers

` Current Tx/Rx Descriptor pointer as status registers

` Statistical counters that help in calculating the bandwidth served

by each transmit channel when AV

support is enabled

Synopsys, Inc. y 700 East Middlefield Road y Mountain View, CA 94043 y www.synopsys.com

2009 Synopsys, Inc. All rights reserved. Synopsys is a registered trademarks of Synopsys, Inc. in the United States and other countries. A list of Synopsys trademarks is available at http://www.synopsys.com/copyright.html. All other names mentioned herein are trademarks or registered trademarks of their respective owners.

10/09.TT.09-18001.

Targeting a TechnologyThe DesignWare Ethernet MAC

10/100/1000 Universal core is designed

to easily map to most modern ASIC

(0.18 micron or below) and FPGA

technologies. The design is based

on simple rising edge flops, and is

compatible with all standard synthesis,

test insertion, and physical design flows.

Users supply standard technology-

specific compiled static memories for

the retry buffer and receive queues.

Transmit and receive FIFO sizes and

datawidths are configurable. 2-port

memory (1 read and 1 write port) are

required for the FIFOs.

DeliverablesThe following deliverables are provided

with a DesignWare Ethernet MAC

10/100/1000 Universal core license:

` Synopsys Ethernet Core Kit: y Verilog RTL source code ` Verification environment that includes:

y DesignWare AMBA and DesignWare Ethernet VIP models

y Verilog BFM models for Ethernet PHY and Ethernet monitor

y Verilog testbench (VTB): Example test vectors in Verilog

` Documentation: Users Manual

` Examples y Linux demonstration software package

y Scripts- Design Compiler, Scan, ATPG, and Formality

` Licenses downloaded from Synopsys y DesignWare Ethernet MAC 10/100/1000 Universal core license

y DesignWare Verification IP Licenses

Tools Supported ` Simulation: VCS, NC-Verilog, MTI-Verilog

` Synthesis: Design Compiler, Synplify FPGA Synthesis

About DesignWare IPSynopsys is a leading provider of

high-quality, silicon-proven interface

and analog IP solutions for system-

on-chip designs. Synopsys broad IP

portfolio delivers complete connectivity

IP solutions consisting of controllers,

PHY and verification IP for widely used

protocols such as USB, PCI Express,

DDR, SATA, HDMI, MIPI and Ethernet.

The analog IP family includes Analog-

to-Digital Converters, Digital-to-Analog

Converters, Audio Codecs, Video

Analog Front Ends, Touch Screen

Controllers and more. In addition,

Synopsys offers SystemC transaction-

level models to build virtual platforms

for rapid, pre-silicon development of

software. With a robust IP development

methodology, extensive investment in

quality and comprehensive technical

support, Synopsys enables designers to

accelerate time-to-market and reduce

integration risk.

For more information on

DesignWare IP, visit:

www.synopsys.com/designware.