© 2011 TSMC, Ltd

TSMC Property

1

EUV Lithography for High-Volume ManufacturingProgress and Challenges

Anthony Yen

Taiwan Semiconductor Manufacturing Company

© 2011 TSMC, Ltd

TSMC Property

2

TSMC Lithography Roadmap

28 nm is the limit of conventional single-patterning lithography

TSMC has innovations to extend immersion to 20 nm

NGL technologies are preferred beyond 20 nm

193nm 193nm ImmersionImmersionNA = 1.2NA = 1.2

193nm 193nm Immersion Immersion NA = 1.35NA = 1.35

40 nm 28 nm 20 nm 14 nm

EUVEUV0.33 NA0.33 NA

>100 wph>100 wph

MEBDWMEBDWClusters Clusters >100 wph>100 wph

NGL

193i193iNA = 1.35 NA = 1.35 Innovative Innovative

RET / LayoutRET / Layout

MEBDWMEBDWCT/Via CT/Via 100 wph100 wph

EUVEUV0.25 NA0.25 NA

Restricted rules and extended DFM for variability reduction

© 2011 TSMC, Ltd

TSMC Property

3

Why EUVL for 14 nm and Beyond?Migration to NGL is necessary to sustain Moore’s law economically

Waf

er C

ost I

ncre

ase

from

28

nm

ArF ImmersionEUVMEBDWTarget

20 nm 14 nm 10 nm 7 nm

© 2011 TSMC, Ltd

TSMC Property

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Progress in EUVL Development at TSMC

Carried out EUV exposure on Alpha Demo Tool at IMEC and ASML Veldhoven with further processing in Taiwan

Installation of NXE3100 EUV scanner is nearly complete

Resist screening is being carried out at SEMATECH facilities in Albany and Berkeley

Mask making technology including patterning, inspection, repair, cleaning, and handling is being developed

An R&D mask facility has been established for EUV mask making

Mask handling and transportation are being studied

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TSMC Property

5

20-nm back-end short-loop wafers processed

M1 layer patterned by single EUV exposure

M2

M1

V1

Back-end short-loop wafers for WAT

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TSMC Property

6

EUVL Infrastructure and Timing

Scanner

2012 2014

　 　 　 　 　 　 　 　 　 　 　 　

　 　 　 　 　 　 　 　 　 　 　 　

　 　 　 　 　 　 　 　 　 　 　 　

　 　 　 　 　 　 　 　 　 　 　 　

　 　 　 　 　 　 　 　 　 　 　 　

　 　 　 　 　 　 　 　 　 　 　 　

　 　 　 　 　 　 　 　 　 　 　 　

　 　 　 　 　 　 　 　 　 　 　 　

　 　 　 　 　 　 　 　 　 　 　 　

　 　 　 　 　 　 　 　 　 　 　 　

　 　 　 　 　 　 　 　 　 　 　 　

　 　 　 　 　 　 　 　 　 　 　 　

　 　 　 　 　 　 　 　 　 　 　 　

　 　 　 　 　 　 　 　 　 　 　 　

　 　 　 　 　 　 　 　 　 　 　 　

　 　 　 　 　 　 　 　 　 　 　 　

　 　 　 　 　 　 　 　 　 　 　 　

2016

NXE3100 HVM EUV Scanner

Mask Inspector

193nm Based

APMIEPMI

Mask Defect/Repair

Verification Tool

ActinicAIMS

Wafer Printing

© 2011 TSMC, Ltd

TSMC Property

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Challenges in Defects Management of EUV Masks

1st InspectionRepair?

Repaired Feature Aerial Image?

Falling ParticleSource?

1. Wafer printing 2. Simulated AIMS

Images3. Repair all defects

1. Wafer printing2. Simulated AIMS

Images

1. Dual-pod cleanliness inspection

2. How to maintain cleanliness w/o pellicles?

Defect Classification Repaired Defect Verification

Soft Defect De-Bugging

Challenges in Defect Management

© 2011 TSMC, Ltd

TSMC Property

8

Mask Defect Classification ChallengeBefore actinic AIMS becomes available, only wafer printing can perform defect classification after 1st inspection

Mask 1st

Inspection

EPMI

PMI

Simulated AIMS Image

Repair printable defects

Wafer Printing

EUV Mask Defect Classification Flow

Repair alldefects

No classification

© 2011 TSMC, Ltd

TSMC Property

9

Repaired Defect Verification ChallengeWafer printing will consume 6X~50X the time required by AIMS-EUV

<1> Data normalized to the time usage of 1st cycle repair<2> One complete cycle includes validation time + defect repair time

<2>

6 X

50 X

© 2011 TSMC, Ltd

TSMC Property

10

Soft Defect De-Bugging ChallengeIdentifying defect source from completed masks to the scanner is a big challenge once repeating defects are found on wafer

Mask final inspection

Mask Shop Wafer Fab

Transportation in dual-pods

Stocker/ Scanner

Where is the soft defect source ?

© 2011 TSMC, Ltd

TSMC Property

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Mask Shop Wafer Fab

EUVScanner

MaskStocker

MaskCleaner Mask

Inspector

OHT

Dual-Pods

Mask Inspector

Mask Handling between Mask Shop and Wafer Fab

© 2011 TSMC, Ltd

TSMC Property

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Courtesy of Hoya

© 2011 TSMC, Ltd

TSMC Property

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Courtesy of AGC

© 2011 TSMC, Ltd

TSMC Property

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50

100

150

200

250

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

2009 2010 2011 2012 2013 2014

Sou

rce

Pow

er (W

)Challenges in Delivering Source Power

11W - 6WPH22W - 12WPH

40W - 22WPH

60WPH@10mJ/cm2

125WPH@15mJ/cm2

140WPH@10mJ/cm2

© 2011 TSMC, Ltd

TSMC Property

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19761979198219851988199119941997200020032006200920122015

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2011

J. Sturtevant, B.J. Lin, A. Yen

ImmersionDPMP

RDRSMOILT

.

.

.

20 nm

45 / 40 nm28 nm

0.35 µm

0.5 µm

0.25 µm

90 nm

0.18 µm

0.13 µm

65 nm

14 nm?

CMPOAIPSMOPC

λ down to 193 nm

Optical Projectionλ down to i-line

λ down to 248 nm

Improvements in optics, precision, overlay, throughput, resists, etc.

Can Optical Lithography Be Extended to 14 nm?

© 2011 TSMC, Ltd

TSMC Property

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What should this community immediately address

On-time delivery of HVM scanners w/ good throughput Roadmap slip for EUV sources must stop

On-time delivery of defect-free EUV mask blanks May have to allow repair to achieve defect-free blanks Blank inspector must be able to provide defect coordinates

down to nm accuracy

New resists having better resolution and sensitivity Need 22-nm half-pitch resolution with < 10 mJ/cm2 sensitivity New resist platforms for application below 14-nm node

© 2011 TSMC, Ltd

TSMC Property

17

Very Preliminary Results from TSMC’s NXE3100

23-nm HP

Mag. 250K

24-nm HP

Mag. 250K Mag. 250K

22-nm HP 21-nm HP

Mag. 250K