eval-ad765xcb/ad766xcb/ad767xcb evaluation board …

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Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.

aEVAL-AD765XCB/AD766XCB/AD767XCB

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 World Wide Web Site: http://www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 2002

Preliminary Technical Data

PRELIMINARY TECHNICAL DATA

ORDERING GUIDE

Evaluation board Model Product

EVAL-AD7650CB AD7650AST/ACP EVAL-AD7651CB AD7651AST/ACP EVAL-AD7652CB AD7652AST/ACP EVAL-AD7653CB AD7653AST/ACP EVAL-AD7654CB AD7654AST/ACP EVAL-AD7655CB AD7655AST/ACP EVAL-AD7660CB AD7660AST/ACP EVAL-AD7661CB AD7661AST/ACP EVAL-AD7663CB AD7663AST/ACP EVAL-AD7664CB AD7664AST/ACP EVAL-AD7665CB AD7665AST/ACP EVAL-AD7666CB AD7666AST/ACP EVAL-AD7667CB AD7667AST/ACP EVAL-AD7671CB AD7671AST/ACP EVAL-AD7674CB AD7674AST/ACP EVAL-AD7675CB AD7675AST/ACP EVAL-AD7676CB AD7676AST/ACP EVAL-AD7677CB AD7677AST/ACP EVAL-AD7678CB AD7678AST/ACP EVAL-AD7679CB AD7679AST/ACP EVAL-CONTROL BRD2 Controller Board

The evaluation software described in this document is alsocompatible with the following previous generation of highresolution ADCs.

Evaluation Board AD765X/AD766X/AD767X

FEATURES

Versatile Analog Signal Conditioning Circuitry

On-Board Reference, Crystal Oscillator and Buffers

16-Bit Parallel Buffered Outputs

Ideal For DSP and Data Acquisition Card Interfaces

Analog and Digital Prototyping Area

EVAL-CONTROL BOARD Compatibility

PC Software for Control and Data Analysis

GENERAL DESCRIPTIONThe EVAL-AD765XCB/AD766XCB/AD767XCB is an evalu-ation board for the AD765X/AD766X/AD767X 16-bit A/Dconverter family. The AD765X/AD766X/AD767X family (see ordering guide for product list ) is a high speed, succes-sive approximation based architecture with very highperformance, low power family of 16-Bit and 18-Bit ADCswhich operate from a single +5V supply with a 100kSPS to1MSPS throughput rate range, and a flexible parallel or serialinterface. The AD765X/AD766X/AD767X evaluation boardis designed to demonstrate the ADC's performance and toprovide an easy to understand interface for a variety of systemapplications. A full description of the AD765X/AD766X/AD767X is available in the Analog Devices AD765X/AD766X/AD767X data sheets and should be consulted whenutilizing this evaluation board.The EVAL-AD765XCB/AD766XCB/AD767XCB is ideal foruse with either the Analog Devices EVAL-CONTROL BRD2,or as a stand-alone evaluation board. The design offers theflexibility of applying external control signals and is capable ofgenerating conversion results on a parallel 16-Bit wide buff-ered outputs.

On-board components include an AD780, a +2.5V ultrahighprecision bandgap reference, a signal conditioning circuitwith two op-amps and digital logic. The board interfaces witha 96-way connector for the EVAL-CONTROL BRD2, a 26-pin IDC connector for serial output interface, and a 40-pinIDC connector for parallel output data. SMB connectors areprovided for the low noise analog signal source, an externalmaster clock and an external start/convert input.

The term AD76XX is used in this document to represent allthe ADCs listed in the ordering guide.

Other software compatible Product

EVAL-AD676EBEVAL-AD677EBEVAL-AD974CBEVAL-AD976CBEVAL-AD976ACBEVAL-AD977CBEVAL-AD977ACB

http://www.analog.com/UploadedFiles/Evaluation_Boards/Tools/33328613EvalBoardController.pdf

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EVAL-AD765XCB/AD766XCB/AD767XCB

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P3. Additionally, BD data is updated on the falling/rising edgeof DBUSY and BBUSY on P3. When either parallel or serialreading mode of the ADC is used, the data is available on thisparallel bus. When serial reading mode of the ADC is used, theserial interface signals of the ADC are buffered and available onthe 26-pin connector P1. When slave serial reading mode of theAD765X/AD766X/AD767X is used, the external serial clockSCLK applied to the ADC is the MCLK frequency.

Power Supplies and Grounding

The evaluation board ground plane is separated into two sec-tions: a plane for the digital interface circuitry and an analogplane for the analog input and external reference circuitry. Toattain high resolution performance, the board was designed toensure that all digital ground return paths do not cross the ana-log ground return paths.

The EVAL-AD765XCB/AD766XCB/AD767XCB is supplied bythe EVAL-CONTROL BRD2 or through the two power supplyblocks SJ1 and SJ2 in stand-alone operation.

Analog Input RangesThe analog front-end amplifier circuitry U6 and U7 allows flex-ible configuration changes such as positive or negative gain,input range scaling, filtering, addition of a DC component, useof different op-amp and supplies.Table VII shows the front end op-amp configuration used withthe AD76XX. In some applications, it is desired to use a bipolaror wider analog input range like, for instance, ± 10V, ± 5V, ±2.5V, or 0 to +5V. For the AD76XX parts which do not havedirectly those input ranges like the AD7650-3/7660-1/7664/7666-7, by simple modifications of the input driver circuitry ofthe EVAL-AD765XCB/AD766XCB/AD767XCB, bipolar andwider input ranges can be used without any performance degra-dation. Components values required and resulting full-scaleranges are shown in table IV and table V.In factory, the analog input of U6 is set at mid-scale(R6=R7=590�) for the AD7650/7660/7664/7675/7676/7677.For AD7663/7665/7671, R7 is not connected to maintain the

OPERATING THE EVAL-AD765XCB/AD766XCB/AD767XCBThe EVAL-AD765XCB/AD766XCB/AD767XCB is a four-layer board carefully laid out and tested to demonstrate thespecific high accuracy performance of the AD765X/AD766X/AD767X. Figure 1 shows the schematics of theevaluation board. The layouts of the board are given in :Top side silk-screen - Figure 2Top side layer - Figure 3Ground layer - Figure 4Shield layer - Figure 5Bottom side layer - Figure 6Bottom side silk-screen - Figure 7.The EVAL-AD765XCB/AD766XCB/AD767XCB is a flex-ible design that enables the user to choose among manydifferent board configurations. A description of each select-able jumper/switch is listed in Table II and the available testpoints are listed in Table III. Note that the button of aswitch in position A ( U10 side ) defines a low level. Theswitches are active only in stand-alone mode.

The EVAL-AD765XCB/AD766XCB/AD767XCB is config-ured in factory for the range shown in Table I. Thefront-end amplifiers U6 and U7 are set with a gain of +1.The board is set to be powered through the EVAL-CON-TROL BRD2, and the on-board CNVST generation isused.

On-board or external CNVST could be used. When anexternal CNVST signal is applied, this signal should havevery low jitter and sharp edges to get the best noise perfor-mance of the part. Meanwhile, it is recommended to use theon-board CNVST generation which is done by dividingMCLK signal (40MHZ) by the numbers shown in Table I,which are entered in the software. MCLK can come eitherfrom the local oscillator or the EVAL-CONTROL BRD2’sDSP. Activity on BUSY pin of the ADC turns on the LED.

Conversion data is available at the output bus BD on U10,on the 40-pin connector P2, and on the 96-pin connector

FUNCTIONAL BLOCK DIAGRAM

40 PINCONN

26 PINCONN

+/-12 V

+/-5 V

VL

96 PINCONN

+5 V

AIN-

SIGNALCONDITIONING

REF 2.5V AD780

AD765X orAD766x orAD767x

REF

DATA

CNVST

AIN+

IN

Clock

DIGITAL LOGIC

Configuration switches

MCLK

BUSY

CNVST

MCLK

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input at 0V (mid-scale). This allows a transition noise testwithout any other equipment. An FFT test can be done byapplying a very low distortion AC source.

Table I. CNVST GENERATION

Part Division Throughput RangeRatio kSPS

AD7650 70 571KSPS 0 to 2.5VAD7651 400 100KSPS 0 to 2.5VAD7652 80 500KSPS 0 to 2.5VAD7653 40 1MSPS 0 to 2.5VAD7654 80 500KSPS 0 to 5VAD7655 80 500KSPS 0 to 5VAD7660 400 100KSPS 0 to 2.5VAD7661 400 100KSPS 0 to 2.5VAD7663 160 250KSPS +/-5VAD7664 70 571KSPS 0 to 2.5VAD7665 70 571KSPS +/-5VAD7666 80 500KSPS 0 to 2.5VAD7667 40 1MSPS 0 to 2.5VAD7671 40 1MSPS +/-5VAD7674 50 800KSPS +/-5VAD7675 400 100KSPS +/-2.5VAD7676 70 500KSPS +/-2.5VAD7677 40 1MSPS +/-2.5VAD7678 400 100KSPS +/-5VAD7679 70 571KSPS +/-5V

EVAL-CONTROL BOARD INTERFACE

The EVAL-AD765XCB/AD766XCB/AD767XCB interfacesto the EVAL-CONTROL BRD2 through the 96-way connec-tor. The EVAL-CONTROL BRD2 provides all necessarysupplies to the EVAL-AD765XCB/AD766XCB/AD767XCB.

RUNNING THE EVAL-AD765X/AD766X/AD767XCBSOFTWARE

Software Description

The EVAL-AD765XCB/AD766XCB/AD767XCB comes withsoftware for analyzing the AD765X/AD766X/AD767X, theAD67X and AD97x family. Through the EVAL-CONTROLBRD2 one can perform a histogram to determine code transi-tion noise, and Fast Fourier Transforms (FFT's) to determinethe Signal-to-Noise Ratio (SNR), Signal-to-Noise-plus-Distor-tion (SNRD) and Total-Harmonic-Distortion (THD). The ACperformances can also been evaluated after digital filtering (averaging ) with enhanced resolution ( up to 32 bits ). Thefront-end PC software has four screens as shown in Figure8,9,10 and 11. Figure 8 is the Setup Screen where input volt-age range, sample rate, number of samples are selected. Figure9 is the Histogram Screen, which allows the code distributionfor DC input and computes the mean and standard deviation.Figure 10 is the FFT Screen, which performs an FFT on thecaptured data, computes the Signal-to-Noise Ratio (SNR),Signal-to-Noise-plus-Distortion (SINAD) and total-Harmonic-Distortion (THD). Figure 11 is the time domainrepresentation of the output. When the on-board CNVSTgeneration is used, a synchronous FFT could be achieved bysynchronizing the external AC generator with the Fsync signal(J5) which is an exact division by 2 of MCLK. Figure 12 is theFFT Screen when averaging is used.

Software Installation

- Double-Click on Setup.exe from the CD-ROM and follow theinstallation instructions.

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TABLE II. JUMPER DESCRIPTION

Jumper Default position FunctionDesignation with the control

board ( Factorysettings)*

JP6* A, U10 side Selection of RDC ( Read during convert ). When the button of the switch is close toJ4 connector ( not A position ) and when the serial reading mode is selected, the dataare read during conversion otherwise the data are read after conversion.

JP7* A, U10 side Selection of PD ( Powerdown ). When the button of the switch is close to J4 connec-tor ( not A position ), the ADC is in power-down mode.

JP8* A, U10 side BYTESWAP. Outputs MSB on D[15:8] and LSB on D[7:0]. When in not A position, outputs LSB on D[15:8] and MSB on D[7:0].

JP9* A, U10 side Selection of RESET. When the button of the switch is close to J4 connector ( not Aposition ), the ADC is reset.

JP10* A, U10 side Selection of SER/PAR ( serial/parallel reading mode ). When the button of the switchis close to J4 connector ( not A position ), the data are read in serial mode otherwisethe data are read in parallel mode.

JP11* not A, J4 side Selection of OB/2C ( coding ). When the button of the switch is close to J4 connector( not A position ), the ADC uses a straight binary coding otherwise the twos comple-ment coding is used.

JP12* A, U10 side Selection of WARP. When the button of the switch is close to J4 connector ( not Aposition ), the ADC uses the WARP mode which is the fastest one.

JP13* A, U10 side Selection of IMPULSE. When the button of the switch is close to J4 connector( not A position ), the ADC uses the IMPULSE mode which is the mode with thelowest power dissipation.

JP14* A, U10 side TEST1. For factory use only and it is pull down.

JP15* A, U10 side TEST0. For factory use only and it is pull down. Should be in A position instandalone

JP16* A, U10 side Selection of EXT/INT ( use of external or internal serial clock ). When the button ofthe switch is close to J4 connector ( not A position ) and when the serial readingmode is selected, the data are read with an external serial clock SCLK generated fromthe master clock MCLK otherwise the data are read with the ADC serial clock. Whenexternal serial clock reading mode is selected, MCLK has to be fast enough to be ablethe read the data properly as explained in the AD766X data sheet. JP16 has no use inparallel reading mode.

JP17* A, U10 side Selection of INVSYNC ( SYNC active level ). When the button of the switch is closeto J4 connector ( not A position ) and when the master serial reading mode is selected, the SYNC signal is active Low. JP17 has no use in parallel reading mode orslave serial reading mode.

JP18* A, U10 side Selection of INVSCLK ( SCLK active edge ). When the button of the switch is closeto J4 connector ( not A position ) and when the serial reading mode is selected,INVSCLK is high. JP18 has no use in parallel reading mode.

JP20 NO BUF Selection of REF signal. When JP20 is in BUF position, the REF is buffered. WhenJP20 is NO BUF position, the REF is the AD780 output.

JP22 not A Selection of CNVST signal. When JP22 is in position A, the signal on J3 is usedotherwise the on-board CNVST generation is used. MCLK signal is used to generatethe on-board CNVST signal.

*JP6-JP18 are used only in stand-alone mode.

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Table III. EVAL-AD765XCB/AD766XCB/AD767XCB TestPoints

Test Point Available Signal

TP1 BUSY ADC BUSY signalTP2 A0TP3 SIG+ ADC Analog inputTP4 AGND Analog ground close to SIG+TP5 REF ADC Reference inputTP7 DGND Digital groundTP8 CNVST ADC CNVST signalTP9 AGND Analog ground close to REFTP10 C S ADC CS signalTP11 R D ADC RD signalTP12 OVDD ADC digital output supplyTP13 DVDD ADC digital core supplyTP14 AVDD ADC analog supplyTP15 AGND Analog groundTP16 SIG- ADC Analog inputTP17 DGND Digital ground

Table IV. Component values Vs. Input ranges ( AD7660 )

Input range R1 R3 R6 R7

± 10V 8k� 1k� 8k� 10k�± 5V 8k� 2k� 6.67k� 10k�

0 to -5V 8k� 8k� 0� none

Table V. Component values Vs. Input ranges ( AD7650AD7664 )

Input range R1 R3 R6 R7

± 10V 2k� 250� 8k� 10k�± 5V 2k� 500� 6.67k� 10k�

0 to -5V 1k� 1k� 0� none

Jumper Default position FunctionDesignation with the control

board ( Factorysettings)

JP23 not A Selection of the master clock MCLK signal. When JP5 is in position A, the J4signal is used otherwise the on-board 40 MHz clock is used as a MCLK signal.MCLK signal is used to generate the on-board CNVST signal and the external serialclock SCLK.

TABLE II. JUMPER DESCRIPTION

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TESTING METHODS

Histogram

To perform a histogram test, apply a DC signal to the input. Itis advised to filter the signal to make the DC Source noise com-patible with that of the ADC. C26 provides this filtering.

AC Testing

To perform an AC test, apply a sinusoidal signal to theevaluation board. Low distortion, better than 100dB, is requiredto allow true evaluation of the part. One possibility is to filter theinput signal from the AC source. There is no suggestedbandpass filter but consideration should be taken in the choice.Furthermore, when the full-scale input range is more than a fewVpp, it is recommended that you use the on board amplifier toamplify the signal, thus preventing the filter from distorting theinput signal.

Decimated Testing ( Averaging )This test can be run as the AC test.

Please refer to Figures 8,9,10,11 and 12 to see the screens ofthe software.

Software DescriptionThe AD16bit.exe is the software which allows you to analyzedifferent performance characteristics of the AD765X,AD766X, AD767X, AD97X and AD67X 16-bit ADC family.The software allows you to test the histogram as well as per-form different AC tests.

Setup Requirements

- Evaluation Control Board 2 (ADSP2189)

- Evaluation Board

- Power Supply (AC 15V/1A source could be bought fromADI)

- Parallel Port Cable (provided with the evaluation controlboard)

- AC Source (low distortion)

- DC Source (low noise)

- Bandpass Filter (value based on your signal frequency, lowdistortion)

USE OF EVAL-AD765XCB/AD766XCB/AD767XCB ASSTAND-ALONE EVALUATION BOARD

You have the option of using theEVAL-AD765XCB/AD766XCB/AD767XCB as a stand-aloneevaluation board. This method does not require theEVAL-CONTROL BRD2, nor does it require use of the ac-companied software. The digital output will now be availableon P1 (26-pin connector, for use in master serial mode) or P2(40-pin connector, for use in both serial and parallel mode).When in stand-alone, CNVST could be externally applied or isgenerated internally according to Table I.

Please refer to Figure 1 to obtain the data output pins on theconnectors.

Data is updated on the falling edge of BUSY. When BCS andCONTROL are low, which is the default value defined by theon-board pull-down resistors, the data bus BD available on theP2 connector is enabled.

SUPPLYING THE BOARD FOR STAND-ALONE USE

SJ1 is the analog supply. Apply +/-12V on +12V and -12Vpins and +5V on +5V pin. SJ2 is the digital supply. Apply 5Von VDIG pin.

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EVAL-BOARD SETTING FOR INPUTCONFIGURATIONSThe AD7663/AD7665 and AD7671 have the ability to oper-ate both unipolar and bipolar range. The available options are+/- 10V, +/- 5V, +/- 2.5V, 0 to 10V, 0 to 5V and 0 to 2.5V. (See application note AN594 on the product web page forother ranges )

Table VI shows the required configurations for each inputrange. (REF = 2.5V). Table VII lists the default settings ofthe board for all parts.

Table VI. AD7663/7665/7671 Analog Input Configuration

Input Voltage IND(4R) INC(4R) INB(2R) INA(R) Range

±4 REF VIN INGND INGND REF ±2 REF VIN VIN INGND REF ±REF VIN VIN VIN REF 0 V to 4REF VIN VIN INGND INGND 0 V to 2REF VIN VIN VIN INGND 0 V to REF VIN VIN VIN VIN

Table VII. Default Settings

Component/Part R7 S9 S10 R48 C40 R47 C39

AD7650 590� None 0� 15� 2.7nF N/A N/A

AD7651 590� None 0� 0� None N/A N/A

AD7652 590� None 0� 15� 2.7nF N/A N/A

AD7653 590� None 0� 15� 2.7nF N/A N/A





AD7663 None None 0� 0� None N/A N/A

AD7664 590� None 0� 15� 2.7nF N/A N/A


AD7666 590� None 0� 15� 2.7nF N/A N/A

AD7667 590� None 0� 15� 2.7nF N/A N/A


AD7674 590� 0� None 15� 2.7nF 15� 2.7nF

AD7675 590� 0� None 15� 2.7nF 15� 2.7nF

AD7676 590� 0� None 15� 2.7nF 15� 2.7nF

AD7677 590� 0� None 15� 2.7nF 15� 2.7nF

AD7678 590� 0� None 15� 2.7nF 15� 2.7nF

AD7679 590� 0� None 15� 2.7nF 15� 2.7nF

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R59

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R7 590

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Figure 1. Schematic

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Figure 1 Schematic

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BD5

BD6

BD7

BD8

BD9

BD10

BD11

BD12

BD13

BD14

BD15

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D

VIO

R32

100

R55

10K

R68

49.9

TP1

BUSY

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TP10

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T0PD

R

SER/

PAR

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2C

WA

RP

IMPU

LSE

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RESE

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NV

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T

BYTE

RESE

T

OB/

2C

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PAR

IMPU

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ST

D[0

..15]

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1

D0

D1

D2

D3

D4

D5

D6

D7 D8

D9 D10

D11

D12

D13

D14

D15

D[0

..15]

A0

WA

RP

PDRT

0

T1/E

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D9

A0

S26

TP2

A0

S24

S25

S22

S23

S28

S29

S27

GN

D

T1 T2 T3 T4 T5 T6

R50

10K

R49

10K

R54

10K

GN

D

DCL

K12

8

CO

NF_

D10

5

CE4

CON

FIG

53

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TA12

5

BCS

111

86

MSE

L33

STA

TUS

56

BD3

120

AD

CO

K49

BD4

117

D11

10

MCL

K13

2

AD

093

AD

196

AD

295

DR0

122

TFS0

118

SCLK

011

6

FSY

NC

131

BBU

SY85

BD15

73

BD13

81BD

1272

BD11

84BD

1087

BWR

114

BD9

94BD

810

9BD

711

0BD

611

2BD

511

5

BD2

123

BD1

124

BD0

129

CON

TRO

L13

0

D12

2

D13

1

BRD

113

BD14

82

DT0

121

RFS0

119

MO

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47

MO

DE1

46

MO

DE2

45

DSP

CLK

71

MO

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44

RESE

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D10

11D

912

D8

14

D14

144

D0

26

CNV

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7

D6

16

D7

15

D15

143

D1

25

D2

24

D3

23

D4

22

D5

21

BUSY

142

RD

141

CS14

0

RESE

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9

PD13

8

CNV

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136

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35

IMPU

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36

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37

OB/

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39

A0

57

PDRE

F58

TEST

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60

TEST

1_O

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61

PDB

UF

62

SCLK

IN13

S2/S

141

DBU

SY40

U10

EPF6

010A

TC14

4

R66

10K

3.3V

AD

CO

K

SDO

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SCLK

BD0

BD1

BD2

BD3

BD4

BD5

BD6

BD7

BD8

BD9

BD10

BD11

BD12

BD13

BD14

BD15

BBU

SY

CON

TRO

L

R52

10K

R51

10K

R31

100

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TP15

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ND

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ND

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1K

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GN

D

BD0

BD1

BD2

BD3

BD4

BD5

BD6

BD7

BD8

BD9

BD10

BD11

BD12

BD13

BD14

BD15

AD

0

DSP

CLK

AD

1

GN

D

CON

TRO

L

BBU

SY

SCLK

TFS0

SDO

UT

TFS0

SDIN

CO

NF_

D

DCL

K

DA

TA

SDIN

C5 C7C19

B18

A18 B1

7

B15

B14

B13

B11

B10

B7 B6 B5 B3 B2 A14 C1

5

B9C18

A19C1

0

C17

A9

C9 B1A17 A

5

A6

C6C14

P3A

DA

TA

DCL

K

SDIN

SDO

UT

STATUS

FSY

NC

SCLK

CO

NF_

D

CONFIG

12

34

56

78

910

1112

1314

1516

1718

1920 22

21 2324

2526

P1

M0

M1

M2

SYN

C

SYN

C

AD

2

GN

D

AD

2

GN

D

3.3V

SYN

C

3.3V

R65

10K

R63

10K

R64

10K

GN

D

M0

M1

M2

DSP

CLK

R58

10K

R57

10K

M3

R56

10K

R62

10K

M3

TP6

BBU

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R34

100

R33

100

J4

JP23

GN

D

GN

DFSY

NC

GN

D

T0

T1

T1

T0

+VA

-VA

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VD

IG

-12V

A4

A12

A16

A20

B4 B12

B16

C4 C12

C16

C20

B20

B26

B27

B28

B29

B30

C21

C22

C23

C24

C25

C26

C29

A21

A22

A32

B32

C32

A31

B31

C31

C30

A8

B8 C8 A30

P3B A

23

A24

A25

A26

A29

B21

B22

B23

B24

B25

P3C

+VA

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GN

D

GN

D

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VD

IG

C23

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C24

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C17

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C18

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C25

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C5 .1uF

C7 .1uF

C8 .1uF

C10

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C11

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C12

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GN

D

3.3V

S2/S

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R53

10K

R41

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710

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VIO

3.3V

GN

D

JP6

JP7

JP8

JP9

JP10

JP11

JP12

JP13

JP14

JP15

JP16

JP17

JP18

RDC

INVSCLK

INVSYNC

EXT/INT

TEST0_IN

R1110K

R1210K

R1310K

R1610K

R1410K

R1710K

R1510K

R1910K

R2010K

R2110K

R2210K

R3510K

SER/PAR

OB/2C

WARP

IMPULSE

RESET

BYTE

PD

D4

D5

D6

D7

RESE

TS

DSE

LBWR

BRD

BCS

BCS

BWR

FSY

NC

BCS

BRD

BWR

CONFIG

STATUS

RESE

TS

DSE

LD

SEL

AD

76X

X-D

IGIT

AL

REV. Pr T


–10–


Figure 1 Schematic

12

34

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8-3.

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C33

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C46

1uF

SJ2

GN

D

GN

DV

DIGV

DIG

2.5V

3.3V

GN

D

+VA

+12V

JP4 12

43

JP5

-VA

JP3

VD

RV

-

GN

D

3.3V

GN

D

VD

RV

+

VR

EF+

JP19

31 2 54 6

SJ1

C54

10uF

C51

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C53

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C50

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+VA

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GN

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AV

DD

GN

D+VA

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+12V

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D

GN

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IN3

GND1

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C49

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DD

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1 24

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JP1

2.5V

3.3V

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IG

AV

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1 23

JP2

2.5V

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IGR

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-12V

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DD

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IG

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REV Pr T –11–



Figure 2. Top side silk-screen ( Not to Scale ).

Figure 3. Top side ( Not to Scale ).

REV. Pr T


–12–


Figure 4. Ground Layer ( Not to Scale ).

Figure 5. Shield Layer ( Not to Scale ).

REV Pr T –13–



Figure 6. Bottom side layer ( Not to Scale ).

Figure 7. Bottom side silk-screen ( Not to Scale ).

REV. Pr T


–14–


2) The part under evaluation is chosen from this menu. Theavailable choices are AD765X, AD766X,AD767X AD97xand AD67x.

1) The Run button starts the software. All input configurationsare read by the software after running the software. You willneed to press this button first.

3) Input Configurations are chosen here. For the AD765X/AD766X/AD767X, the available choices are: PwDown, Re-set, Interface, Coding, Byte, and Reading.

Figure 8. Setup Screen

5) You may choose to take one sample (Sample,F3), or per-form continuous sampling (Continuous,F4). You may alsochoose the Help, Save, Print or Quit options. The Help menuwill show you a description of the functionality of the chosencommand.

This is the performance window.

4) The choice of test is madehere. You may choose to per-form either :- an Histogram test- an AC test- an AC test with decimateddigital filtering.

6) (Documentation.F2) gives direct acces to datasheets

And evaluation documentation...

REV Pr T –15–



Figure 9. Histogram Screen

Different measurements are displayed here. The DC value,transition noise, and other values.

This control allows you the choice of display. You have theoption of Time or Histogram. You also have the option ofchanging the X-axis unit

The results are displayed on this chart. You may also use thecursor (yellow) and drag it to your desired location, where theX-axis value and the Y-axis value will be displayed.

REV. Pr T


–16–


Figure 10. FFT Screen

AC test results are shown here. You also have thechoice of viewing the amplitude of a certain FFTcomponent by changing the FFT componentmenu.

You may choose either a Kaiser window or a Blackmann-Har-ris window or a Sync FFT from this menu. . When choosing aSync FFT, you will need to synchronize your analog source tothe sampling frequency. The input frequency should be thevalue Sync Fr, which is to the right of Target frequency. Theprocess for this is as follows:1. You Choose a Target frequency2. The software calculates an integer n based on the targetfrequency you entered and the sampling frequency, Fsamp.

3. The software rounds up the value n to the next primenumber.4. The software then calculates the corresponding input fre-quency (Fin) and displays that as Sync Fr.The equation, (capture window size) is shown below:(1/Fsamp) * (number of samples) = n * (1/Fin)

This is the control that allows youthe choice of either time domainor frequency domain. You mayalso change the X-axis unit here.


REV Pr T –17–



To view the Time domain, select Time in this menu.

You can also view the output in the Time domain as shown below.

Figure 11. Time-Domain Screen

REV. Pr T


–18–


AC test results with decimated averaging areshown here. The SNR indicator also represent thedynamic range when no AC signal is applied.

This is the control that allows youthe choice of either time domainor frequency domain. You mayalso change the X-axis unit here.


The decimation ratio and theaverage length is defined here.

Figure 10. Decimated ( Averaging ) Screen

The ADC sampling frequency isdefined by the ratio.

The output word rate after deci-mation is shown here. It is theratio between the ADC samplingrate and the decimattion ratio.

REV Pr T –19–



1 HEADER 2X20 CONNECTOR P2 3M 2540-6002UB

1 HEADER 2X13 CONNECTOR P1 3M 2526-6002UB

1 32X3 RT PC MOUNT CONNECTOR P3 ERNI 533402

Bill of Material for the Connectors

eval-ad765xcb/ad766xcb/ad767xcb evaluation board …

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