evaluation kit available high-speed step-down controller … · 2006-03-13 · for pricing,...

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

General DescriptionThe MAX1714 pulse-width modulation (PWM) controllerprovides the high efficiency, excellent transientresponse, and high DC output accuracy needed forstepping down high-voltage batteries to generate low-voltage CPU core or chip-set/RAM supplies in notebookcomputers.

Maxim’s proprietary Quick-PWM™ quick-response,constant-on-time PWM control scheme handles wideinput/output voltage ratios with ease and provides100ns “instant-on” response to load transients whilemaintaining a relatively constant switching frequency.

The MAX1714 achieves high efficiency at a reducedcost by eliminating the current-sense resistor found intraditional current-mode PWMs. Efficiency is furtherenhanced by an ability to drive very large synchronous-rectifier MOSFETs.

Single-stage buck conversion allows these devices todirectly step down high-voltage batteries for the highestpossible efficiency. Alternatively, two-stage conversion(stepping down the +5V system supply instead of thebattery) at a higher switching frequency allows the mini-mum possible physical size.

The MAX1714 is intended for CPU core, chipset,DRAM, or other low-voltage supplies as low as 1V. TheMAX1714A is available in a 20-pin QSOP package andincludes overvoltage protection. The MAX1714B isavailable in a 16-pin QSOP package with no overvolt-age protection. For applications requiring VID compli-ance or DAC control of output voltage, refer to theMAX1710/MAX1711 data sheet. For a dual output ver-sion, refer to the MAX1715† data sheet.

ApplicationsNotebook Computers

CPU Core Supply

Chipset/RAM Supply as Low as 1V

1.8V and 2.5V I/O Supply

Features♦ Ultra-High Efficiency♦ No Current-Sense Resistor (Lossless ILIMIT)♦ Quick-PWM with 100ns Load-Step Response♦ 1% VOUT Accuracy Over Line and Load♦ 2.5V/3.3V Fixed or 1V to 5.5V Adjustable Output

Range♦ 2V to 28V Battery Input Range♦ 200/300/450/600kHz Switching Frequency♦ Overvoltage Protection (MAX1714A)♦ Undervoltage Protection♦ 1.7ms Digital Soft-Start♦ Drives Large Synchronous-Rectifier FETs♦ 2V ±1% Reference Output♦ Power-Good Indicator

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High-Speed Step-Down Controllerfor Notebook Computers

________________________________________________________________ Maxim Integrated Products 1

19-1536; Rev 2; 8/05

Pin Configurations appear at end of data sheet.

Quick-PWM is a trademark of Maxim Integrated Products.† Future product—contact factory for availability.

-40°C to +85°C

PART

MAX1714AEEP

TEMP RANGE PIN-PACKAGE

20 QSOP

Ordering Information

VCC

+5V INPUT

BATTERY 4.5V TO 28V

OUTPUT1.25V TO 2V

SHDN

ILIM

DL

LX

V+

BST

DH

PGND(GND)

OUT

SKIP

VDD

MAX1714

REF

PGOOD

FB

AGND(GND)

( ) ARE FOR THE MAX1714B ONLY.

Minimal Operating Circuit

MAX1714AEEP+ -40°C to +85°C 20 QSOP

+Denotes lead-free package.

MAX1714BEEE -40°C to +85°C 16 QSOP

MAX1714BEEE+ -40°C to +85°C 16 QSOP

EVALUATION KIT

AVAILABLE

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ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.

V+ to AGND (Note 1)..............................................-0.3V to +30V VDD, VCC to AGND (Note 1).....................................-0.3V to +6VPGND to AGND (Note 1) ................................................... ±0.3VSHDN, PGOOD, OUT to AGND (Note 1)..................-0.3V to +6VILIM, FB, REF, SKIP,

TON to AGND (Notes 1, 2)....................-0.3V to (VCC + 0.3V)DL to PGND (Note 1)..................................-0.3V to (VDD + 0.3V)BST to AGND (Note 1) ...........................................-0.3V to +36V DH to LX.....................................................-0.3V to (BST + 0.3V)

LX to BST..................................................................-6V to +0.3VREF Short Circuit to AGND.........................................Continuous Continuous Power Dissipation (TA = +70°C)

16-Pin QSOP (derate 8.3mW/°C above +70°C)..........667mW20-Pin QSOP (derate 9.1mW/°C above +70°C)..........727mW

Operating Temperature Range ..........................-40°C to +85°CJunction Temperature ......................................................+150°CStorage Temperature Range ............................-65°C to +150°CLead Temperature (soldering, 10s) .................................+300°C

V+ = 4.5V to 28V, SKIP = VCC

V SHDN = 0 , V+ = 28V, VCC = VDD = 0 or 5VV SHDN = 0

VCC, VDD

V SHDN = 0

Battery voltage, V+

FB forced above the regulation point


Rising edge of SHDN to full ILIM

(Note 4)

V+ = 24V,VOUT = 2V(Note 4)

ILOAD = 0 to 3A, SKIP = VCC

VCC = 4.5V to 5.5V, V+ = 4.5V to 28V

CONDITIONS

µA<1 5Shutdown Supply Current (V+)

µA<1 5Shutdown Supply Current (VDD)

µA<1 5Shutdown Supply Current (VCC)

µA25 40Quiescent Supply Current (V+)

µA<1 5Quiescent Supply Current (VDD)

µA550 750Quiescent Supply Current (VCC)

ns400 500Minimum Off-Time

380 425 470

260 290 320

175 200 225

V

0.99 1.0 1.01Error Comparator Threshold (DC Output Voltage Accuracy)(Note 3)

TON = REF (450kHz)

4.5 5.5V

2 28Input Voltage Range

TON = AGND (600kHz)

ns

140 160 180

On-Time

ms1.7Soft-Start Ramp Time

µA-0.1 0.1FB Input Bias Current

TON = unconnected (300kHz)

mV9Load Regulation Error

mV5Line Regulation Error

UNITSMIN TYP MAXPARAMETER

Falling edge, hysteresis = 40mV

REF in regulation

IREF = 0 to 50µA

VCC = 4.5V to 5.5V, no external REF load

V1.6REF Fault Lockout Voltage

µA10REF Sink Current

V0.01Reference Load Regulation

V1.98 2 2.02Reference Voltage

TON = VCC (200kHz)

Note 1: For the MAX1714B, AGND and PGND refer to a single pin designated GND.Note 2: SKIP may be forced below -0.3V, temporarily exceeding the absolute maximum rating, disabling over/undervoltage fault

detection for the purpose of debugging prototypes (Figure 6). Limit the current drawn to 5mA maximum.

ELECTRICAL CHARACTERISTICS(Circuit of Figure 1, 4A components from Table 1, V+ = +15V, VCC = VDD = +5V, SKIP = AGND, TA = 0°C to +85°C, unless otherwisenoted.) (Note 1)

FB = AGND kΩ100 190 300OUT Input Resistance

FB = OUT

2.475 2.5 2.525FB = AGND

FB = VCC 3.267 3.3 3.333

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ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, 4A components from Table 1, V+ = +15V, VCC = VDD = +5V, SKIP = AGND, TA = 0°C to +85°C, unless otherwisenoted.) (Note 1)

CONDITIONS UNITSMIN TYP MAXPARAMETER

PGND - LX

PGND - LX, ILIM = VCC

From SHDN signal going high

mV40 50 60Current-Limit Threshold

(Positive Direction, Adjustable)

mV90 100 110Current-Limit Threshold(Positive Direction, Fixed)

ms10 30Output Undervoltage ProtectionBlanking Time

%65 70 75Output Undervoltage ProtectionThreshold

PGND - LX, SKIP = VCC, TA = +25°C, with respect to positive current-limit threshold

%-90 -120 -140Current-Limit Threshold(Negative Direction)

VILIM = 0.5V

VILIM = 2.0V 170 200 230

Rising edge, hysteresis = 20mV, PWM disabled below this level

V4.1 4.4VCC Undervoltage LockoutThreshold

BST - LX forced to 5V Ω1.5 5DH Gate-Driver On-Resistance

DL, high state Ω1.5 5DL Gate-Driver On-Resistance(Pull-Up)

DL, low state Ω0.5 1.7DL Gate-Driver On-Resistance(Pull-Down)

DH forced to 2.5V, BST - LX forced to 5V A1DH Gate-Driver Source/SinkCurrent

DL forced to 2.5V A1DL Gate-Driver Source Current

DL forced to 2.5V A3DL Gate-Driver Sink Current

FB forced 2% above trip threshold (MAX1714A only) µs1.5Overvoltage Fault PropagationDelay

%10.5 12.5 14.5Overvoltage Trip Threshold

FB forced 2% below PGOOD trip threshold, falling edge µs1.5PGOOD Propagation Delay

PGND - LX, SKIP = AGND mV3Current-Limit Threshold(Zero Crossing)

ISINK = 1mA V0.4PGOOD Output Low Voltage

High state, forced to 5.5V µA1PGOOD Leakage Current

Hysteresis = 10°C °C150Thermal Shutdown Threshold

With respect to error comparator threshold (MAX1714A only)

With respect to error comparator threshold

DL risingns

35Dead Time

DH rising 26

mASKIP Input Current LogicThreshold

To disable overvoltage and undervoltage fault detection, TA = +25°C

-1.5 -0.1

%PGOOD Trip ThresholdMeasured at FB with respect to error comparator threshold, falling edge

-8 -6 -4

VLogic Input High Voltage SHDN, SKIP 2.4

VLogic Input Low Voltage SHDN, SKIP 0.8

µALogic Input Current SHDN, SKIP -1 1

nAILIM Input Current SHDN, SKIP ±10

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ELECTRICAL CHARACTERISTICS(Circuit of Figure 1, 4A components from Table 1, V+ = 15V, VCC = VDD = +5V, SKIP = AGND, TA = -40°C to +85°C, unless other-wise noted.) (Notes 1, 5)

ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, 4A components from Table 1, V+ = +15V, VCC = VDD = +5V, SKIP = AGND, TA = 0°C to +85°C, unless otherwisenoted.) (Note 1)

CONDITIONS

VVCC - 0.4TON VCC Level

V3.15 3.85TON Float Voltage

V1.65 2.35TON Reference Level

V0.5TON AGND Level

Forced to AGND or VCC µA-3 3TON Input Current

UNITSMIN TYP MAXPARAMETER

TON = VCC (200kHz)

Reference Voltage 1.98 2.02 VVCC = 4.5V to 5.5V, no external REF load

PARAMETER MIN TYP MAX UNITS

TON = unconnected (300kHz)On-Time

140 180

ns

TON = AGND (600kHz)

Input Voltage Range 2 28

V4.5 5.5

TON = REF (450kHz)

Error Comparator Threshold (DC Output Voltage Accuracy)(Note 3)

0.985 1.015

V

175 225

With respect to error comparator threshold (MAX1714A only)

260 320

380 470

Minimum Off-Time

FB = AGND

500 ns

Quiescent Supply Current (VCC)

FB = OUT

750 µA

3.25 3.35

2.462 2.538

Logic Input Current -1 1 µASHDN, SKIP

Logic Input Low Voltage 0.8 VSHDN, SKIP

Logic Input High Voltage

FB = VDD

V

2.4 VSHDN, SKIP

VCC Undervoltage LockoutThreshold

4.1 4.4Rising edge, hysteresis = 20mV, PWM disabled belowthis level

Output UndervoltageProtection Threshold

65 75

CONDITIONS

%

160 240

With respect to error comparator threshold

VILIM = 2.0V

VILIM = 0.5VCurrent-Limit Threshold (Positive Direction, Adjustable)

35 65

V+ = 24V,VOUT = 2V(Note 4)

(Note 4)

mV

Overvoltage Trip Threshold


PGND - LX

Current-Limit Threshold (PositiveDirection, Fixed)

Battery voltage, V+

85 115

VCC, VDD

mVPGND - LX, ILIM = VCC

V+ = 4.5V to 28V,SKIP = VCC

10 15 %

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600.01 1010.1

EFFICIENCY vs. LOAD CURRENT(4A COMPONENTS, VOUT = 2.5V, 300kHz)

80

100

70

90

MAX

1714

B-01

LOAD CURRENT (A)

EFFI

CIEN

CY (%

)

VIN = 7V

VIN = 20V

VIN = 12V

600.01 1010.1

EFFICIENCY vs. LOAD CURRENT(8A COMPONENTS, VOUT = 1.6V, 300kHz)

100

70

90

80

MAX

1714

B-02

LOAD CURRENT (A)

EFFI

CIEN

CY (%

)

VIN = 20VVIN = 12V

VIN = 7V

600.01 1010.1

EFFICIENCY vs. LOAD CURRENT(1.5A COMPONENTS, VOUT = 2.5V,

TON = GND, 600kHz)

80

100

70

90

MAX

1714

B-03

LOAD CURRENT (A)

EFFI

CIEN

CY (%

)

VIN = 5V

Note 1: For the MAX1714B, AGND and PGND refer to a single pin designated GND.Note 2: SKIP may be forced below -0.3V, temporarily exceeding the absolute maximum rating, disabling over/undervoltage fault

detection for the purpose of debugging prototypes (Figure 6). Limit the current drawn to 5mA maximum.Note 3: When the inductor is in continuous conduction, the output voltage will have a DC regulation level higher than the error-

comparator threshold by 50% of the ripple. In discontinuous conduction (SKIP = AGND, light-loaded), the output voltagewill have a DC regulation level higher than the trip level by approximately 1.5% due to slope compensation.

Note 4: On-time and off-time specifications are measured from 50% point to 50% point at the DH pin with LX = PGND, VBST = 5V,and a 250pF capacitor connected from DH to LX. Actual in-circuit times may differ due to MOSFET switching speeds.

Note 5: Specifications to -40°C are guaranteed by design, not production tested.

__________________________________________Typical Operating Characteristics(Circuit of Figure 1, components from Table 1, VIN = +15V, SKIP = AGND, TON = unconnected, TA = +25°C, unless otherwise noted.)

CONDITIONS

Measured at FB with respect to error comparatorthreshold, falling edge

%-8 -4PGOOD Trip Threshold

ISINK = 1mA V0.4PGOOD Output Low Voltage

High state, forced to 5.5V µA1PGOOD Leakage Current

UNITMIN TYP MAXPARAMETER

ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, 4A components from Table 1, V+ = +15V, VCC = VDD = +5V, SKIP = AGND, TA = -40°C to +85°C, unless other-wise noted.) (Notes 1, 5)

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_____________________________Typical Operating Characteristics (continued)(Circuit of Figure 1, components from Table 1, VIN = +15V, SKIP = AGND, TON = unconnected, TA = +25°C, unless otherwise noted.)

0

2

1

3

4

5

6

7

8

9

0 105 15 20 25 30

INDUCTOR CURRENT PEAKS AND VALLEYSvs. INPUT VOLTAGE (4A COMPONENTS,

AT CURRENT-LIMIT TRIP POINT)

MAX

1714

B-09

INPUT VOLTAGE (V)

INDU

CTOR

CUR

RENT

(A)

IPEAK

IVALLEY

0

200

400

600

800

0 10 20 305 15 25

NO-LOAD SUPPLY CURRENT(4A COMPONENTS, SKIP MODE, 300kHz)

MAX

1714

B-10

INPUT VOLTAGE (V)

SUPP

LY C

URRE

NT (µ

A)

ICC

IIN IDD

10

8

00 5 20 30

NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE

(4A COMPONENTS, PWM MODE, 300kHz)

4

6

2

MAX

1714

B-11

INPUT VOLTAGE (V)

SUPP

LY C

URRE

NT (m

A)

10 15 25

ICC

IDD

IIN

0

200

100

400

300

500

600

4.0 5.04.5 5.5 6.0

NO-LOAD SUPPLY CURRENT vs. INPUTVOLTAGE (1.5A COMPONENTS,

SKIP MODE, VOUT = 2.5V, 600kHz)M

AX17

14B-

12

VCC, VDD, VIN INPUT VOLTAGE (V)

SUPP

LY C

URRE

NT (µ

A)

ICC

IDDIIN

0

12

10

2

4

8

6

IOUT AT CURRENT LIMIT vs. TEMPERATURE

(4A COMPONENTS, VOUT = 2.5V)

MAX

1714

B-07

TEMPERATURE (°C)

OUTP

UT C

URRE

NT (A

)

-40 20 40-20 0 60 80

VILIM = 1V

VILIM = 0.5V

0

200

100

300

400

500

600

700

0 105 15 20 25 30

CONTINUOUS TO DISCONTINUOUS INDUCTOR CURRENT POINT vs. INPUT VOLTAGE

(4A COMPONENTS, VOUT = 2.5V)

MAX

1714

B-08

INPUT VOLTAGE (V)

LOAD

CUR

RENT

(mA)

300

00.01 1010.1

FREQUENCY vs. LOAD CURRENT(4A COMPONENTS, VOUT = 2.5V)

100

50

250

200

350

150

MAX

1714

B-04

LOAD CURRENT (A)

FREQ

UENC

Y (k

Hz)

VIN = 7V, 15V, PWM MODE

VIN = 15VSKIP MODE

VIN = 7VSKIP MODE

280

290

300

310

320

FREQUENCY vs. INPUT VOLTAGE(4A COMPONENTS, VOUT = 2.5V, IOUT = 1A)

MAX

1714

B-05

INPUT VOLTAGE (V)

FREQ

UENC

Y (k

Hz)

0 10 155 20 3025TEMPERATURE (°C)

FREQ

UENC

Y (k

Hz)

300

310

305

320

315

330

325

FREQUENCY vs. TEMPERATURE(4A COMPONENTS, VOUT = 2.5V)

MAX

1714

B-06

-40 20 40-20 0 60 80

IOUT = 4A

IOUT = 1A

C

B

A

A = VOUT, AC-COUPLED, 100mV/divB = INDUCTOR CURRENT, 2A/divC = DL, 10V/div

10µs/div

LOAD-TRANSIENT RESPONSE(4A COMPONENTS, VOUT = 2.5V, 300kHz)

MAX

1714

B-13

C

B

A


10µs/div

LOAD-TRANSIENT RESPONSE(8A COMPONENTS, VOUT = 1.6V, 300kHz)

MAX

1714

B-14

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_____________________________Typical Operating Characteristics (continued)(Circuit of Figure 1, components from Table 1, VIN = +15V, SKIP = AGND, TON = unconnected, TA = +25°C, unless otherwise noted.)

C

B

A

A = VOUT, 1V/divB = INDUCTOR CURRENT, 5A/divC = DL, 5V/div

500µs/div

START-UP WAVEFORM(4A COMPONENTS, IOUT = 4A, ACTIVE LOAD,

VOUT = 2.5V, 300kHz)

MAX

1714

B-16

C

B

A


200µs/div

OUTPUT OVERLOAD WAVEFORM(4A COMPONENTS, VOUT = 2.5V, 300kHz)

MAX

1714

B-17

OUTPUT UNDERVOLTAGEPROTECTION THRESHOLD

C

B

A


50µs/div

SHUTDOWN WAVEFORM(4A COMPONENTS, VOUT = 2.5V, 300kHz)

MAX

1714

B-18

C

B

A


5µs/div

LOAD-TRANSIENT RESPONSE(1.5A COMPONENTS, VIN = 5V,

VOUT = 2.5V, 600kHz)

MAX

1714

B-15

PIN

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Pin Description

Analog and Power Ground. AGND and PGND connect together internally.GND–

No Connection. These pins are not connected to any internal circuitry. Connect N.C. pinsto the ground plane to enhance thermal conductivity.

N.C.2, 9,11

Power-Good Open-Drain Output. PGOOD is low when the output voltage is more than 6%below the normal regulation point or during soft-start. PGOOD is high impedance whenthe output is in regulation and the soft-start circuit has terminated.

PGOOD10

High-Side Gate Driver Output. Swings from LX to BST.DH1

Current-Limit Threshold Adjustment. Connect ILIM to VCC for 100mV current-limit threshold.For an adjustable threshold, connect an external voltage source to ILIM, or use a two-resis-tor divider from REF to AGND. The external adjustment range of 0.5V to 2.0V corresponds toa current-limit threshold of 50mV to 200mV.

ILIM6

+2.0V Reference Voltage Output. Bypass to AGND with 0.22µF (minimum) capacitor. Cansupply 50µA for external loads.

REF7

Analog Ground.AGND8

Shutdown Control Input. Drive SHDN to AGND to force the MAX1714 into shutdown. Driveor connect to VCC for normal operation. A rising edge on SHDN clears the fault latch.

SHDN3

Feedback Input. Connect to AGND for a +2.5V fixed output or to VCC for a +3.3V fixedoutput, or connect FB to a resistor divider from OUT for an adjustable output.

FB4

PIN

Output Voltage Connection. Connect directly to the junction of the external and output fil-ter capacitors. OUT senses the output voltage to determine the on-time and also servesas the feedback input in fixed-output modes.

OUT5

FUNCTIONNAME

Low-Side Gate-Driver Output. Swings from PGND to VDD. DL13

Supply Input for the DL Gate Drive. Connect to the system supply voltage, +4.5V to +5.5V.Bypass to PGND with a 1µF (min) ceramic capacitor.

VDD14

Analog-Supply Input. Connect to the system supply voltage, +4.5V to +5.5V, with a series20Ω resistor. Bypass to AGND with a 1µF (min) ceramic capacitor.

VCC15

On-Time Selection-Control Input. This is a four-level input used to determine DH on-time.Connect to AGND, REF, or VCC, or leave TON unconnected to set the following switchingfrequencies: AGND = 600kHz, REF = 450kHz, floating = 300kHz, and VCC = 200kHz.

TON16

Battery Voltage Sense Connection. Connect to input power source. V+ is used only to setthe PWM one-shot timing.

V+17

Pulse-Skipping Control Input. Connect to VCC for low-noise forced-PWM mode. Connectto AGND to enable pulse-skipping operation.SKIP18

Boost Flying-Capacitor Connection. Connect to an external capacitor and diode accordingto the Standard Application Circuit (Figure 1). See MOSFET Gate Drivers (DH, DL) section.

BST19

External Inductor Connection. Connect LX to the switched side of the inductor. LX servesas the lower supply rail for the DH high-side gate driver. LX is also the positive input to thecurrent-limit comparator.

LX20

8

–

7

1

5

6

–

2

3

4

9

10

11

12

13

14

15

16

Power Ground. Connect directly to the low-side MOSFET’s source. Serves as the negativeinput of the current-limit comparator.

PGND12 –

MAX1714A MAX1714B

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VCC

VIN4.5V TO 28V

+5VBIAS SUPPLY

C2

( ) = ARE FOR THE MAX1714B ONLY.NOTE: IN THE MAX 1714B, AGND AND PGND ARE INTERNALLY CONNECTED TO THE GND PIN.

POWER-GOODINDICATOR

L1VOUT

SHDN

V+

D2CMPSH-3

C63.3µF

C70.1µF

C40.22µF

Q1

D1

R2100k

Q2

C54.7µF

R120Ω

C1

SKIP

ON/OFFCONTROL

LOW-NOISECONTROL

DL

LX

BST

DH

PGND(GND)

OUT

FB

PGOOD

VDD

MAX1714

+5V

+5V

TON

REF

AGND(GND)

ILIM

Figure 1. Standard Application Circuit

Standard Application CircuitThe standard application circuit (Figure 1) generates alow-voltage rail for general-purpose use in a notebookcomputer (I/O supply, fixed CPU core supply, DRAMsupply). This DC-DC converter steps down a battery orAC adapter voltage to voltages from 1.0V to 5.5V withhigh efficiency and accuracy.

See Table 1 for a list of component selections for com-mon applications. Table 2 lists component manufacturers.

Detailed DescriptionThe MAX1714 buck controller is targeted for low-voltagepower supplies for notebook computers. Maxim‘s propri-etary Quick-PWM pulse-width modulator in the MAX1714is specifically designed for handling fast load stepswhile maintaining a relatively constant operating fre-quency and inductor operating point over a wide rangeof input voltages. The Quick-PWM architecture circum-vents the poor load-transient timing problems of fixed-frequency current-mode PWMs while also avoiding theproblems caused by widely varying switching frequen-cies in conventional constant-on-time and constant-off-time PWM schemes.

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+5V Bias Supply (VCC and VDD)The MAX1714 requires an external +5V bias supply inaddition to the battery. Typically, this +5V bias supply isthe notebook’s 95% efficient +5V system supply.Keeping the bias supply external to the IC improves effi-ciency and eliminates the cost associated with the +5Vlinear regulator that would otherwise be needed to sup-

ply the PWM circuit and gate drivers. If stand-alonecapability is needed, the +5V supply can be generatedwith an external linear regulator such as the MAX1615.

The battery and +5V bias inputs can be tied together ifthe input source is a fixed +4.5V to +5.5V supply. If the+5V bias supply is powered up prior to the battery sup-ply, the enable signal (SHDN) must be delayed until thebattery voltage is present in order to ensure startup. The+5V bias supply must provide VCC and gate-drivepower, so the maximum current drawn is:

IBIAS = ICC + f (QG1 + QG2) = 5mA to 30mA (typ)

where ICC is 600µA typical, f is the switching frequency,and QG1 and QG2 are the MOSFET data sheet totalgate-charge specification limits at VGS = 5V.

Free-Running, Constant-On-Time PWMController with Input Feed-Forward

The Quick-PWM control architecture is a pseudo-fixed-fre-quency, constant-on-time current-mode type with voltagefeed-forward (Figure 2). This architecture relies on the out-put filter capacitor’s ESR to act as the current-sense resis-tor, so the output ripple voltage provides the PWM rampsignal. The control algorithm is simple: the high-sideswitch on-time is determined solely by a one-shot whoseperiod is inversely proportional to input voltage and direct-ly proportional to output voltage. Another one-shot sets aminimum off-time (400ns typical). The on-time one-shot istriggered if the error comparator is low, the low-side switchcurrent is below the current-limit threshold, and the mini-mum off-time one-shot has timed out.


10 ______________________________________________________________________________________

Table 1. Component Selection for Standard Applications

Table 2. Component Suppliers

4.5V to 5.5V7V to 20V7V to 20VInput Range

100µF, 10V Sanyo POSCAP 10TPA100M

(2) 470µF 6V Kemet T510X477108M006AS

470µF, 6V Kemet T510X477108M006AS

C2 Output Capacitor

100µF, 10V Sanyo POSCAP 10TPA100M

(2) 10µF, 25V Taiyo Yuden TMK432BJ106KM

10µF, 25V Taiyo Yuden TMK432BJ106KM

C1 Input Capacitor

3.3µH Coiltronics UP1B-3R3

1.5µH Sumida CEP1251R5MC

6.8µH Coilcraft DO3316P-682L1 Inductor

Motorola MBR0520LT1Motorola MBRS340T3Nihon EP10QY03D2 Rectifier

International Rectifier 1/2 IRF7301

Fairchild SemiconductorFDS6670A

Fairchild Semiconductor1/2 FDS6982A

Q2 Low-Side MOSFET

International Rectifier 1/2 IRF7301

International Rectifier IRF7811

Fairchild Semiconductor1/2 FDS6982A

Q1 High-SideMOSFET

600kHz300kHz300kHzFrequency

2.5V AT 1.5A1.6V AT 8A2.5V AT 4ACOMPONENT

[1] 602-994-6430602-303-5454Motorola

[1] 408-986-1442408-986-0424Kemet

[1] 408-721-1635408-822-2181Fairchild[1] 561-241-9339561-241-7876Coiltronics[1] 847-639-1469847-639-6400Coilcraft[1] 516-435-1824516-435-1110Central Semiconductor[1] 803-626-3123803-946-0690AVX

FACTORY FAX[Country Code]

USA PHONEMANUFACTURER

[1] 714-960-6492714-969-2491Matsuo

[1] 310-322-3332310-322-3331International Rectifier

[1] 408-573-4159408-573-4150Taiyo Yuden

[1] 603-224-1430603-224-1961Sprague

[1] 408-970-3950408-988-8000800-554-5565

Siliconix

[81] 7-2070-1174619-661-6835Sanyo[81] 3-3494-7414805-867-2555*NIEC (Nihon)

[1] 814-238-0490814-237-1431800-831-9172

Murata

[81] 3-3607-5144847-956-0666Sumida

[1] 847-390-4405847-390-4461TDK

*Distributor

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On-Time One-Shot (TON)The heart of the PWM core is the one-shot that sets thehigh-side switch on-time. This fast, low-jitter, adjustableone-shot includes circuitry that varies the on-time inresponse to battery and output voltage. The high-sideswitch on-time is inversely proportional to the batteryvoltage as measured by the V+ input, and proportionalto the output voltage. This algorithm results in a nearlyconstant switching frequency despite the lack of a fixed-

frequency clock generator. The benefits of a constantswitching frequency are twofold: first, the frequency canbe selected to avoid noise-sensitive regions such as the455kHz IF band; second, the inductor ripple-currentoperating point remains relatively constant, resulting ineasy design methodology and predictable output volt-age ripple.

On-Time = K (VOUT + 0.075V) / VIN

REF-6%

FROMOUT

REF

FB

ERRORAMP

TOFF

TON

REF+12%

REF-30%

FEEDBACKMUX

(SEE FIGURE 9)

CHIPSUPPLY

x2

SHDN

PGOOD

MAX1714A ONLY

NOTE: IN THE MAX1714B, AGND AND PGND ARE INTERNALLY CONNECTED TO THE GND PIN. ( ) ARE FOR THE MAX1714B ONLY.

(MAX1714B ONLY)

OVP/UVLOLATCH

ON-TIMECOMPUTE

TON

1-SHOT

1-SHOT

TRIG

IN2V TO 28V

TRIG

Q

Q

S

R

2VREF

AGND

REF

OUT(GND)

(GND)

PGND

+5V

OUTPUT

DL

VCC

VDD

LX

ZERO CROSSING

CURRENTLIMIT

DH

BST9R

R

ILIM

+5V

+5V

Q

S1

QS2 TIMER

SKIP

TON

V+

Σ

MAX1714

S

RQ

Figure 2. MAX1714 Functional Diagram

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12 ______________________________________________________________________________________

where K is set by the TON pin-strap connection and0.075V is an approximation to accommodate for theexpected drop across the low-side MOSFET switch.One-shot timing error increases for the shorter on-timesettings due to fixed propagation delays; it is approxi-mately ±12.5% at 600kHz and 450kHz, and ±10% at thetwo slower settings. This translates to reduced switching-frequency accuracy at higher frequencies (Table 5).Switching frequency increases as a function of load cur-rent due to the increasing drop across the low-sideMOSFET, which causes a faster inductor-current dis-charge ramp. The on-times guaranteed in the ElectricalCharacteristics are influenced by switching delays in theexternal high-side power MOSFET.

Two external factors that influence switching-frequencyaccuracy are resistive drops in the two conduction loops(including inductor and PC board resistance) and thedead-time effect. These effects are the largest contribu-tors to the change of frequency with changing load cur-rent. The dead-time effect increases the effectiveon-time, reducing the switching frequency as one orboth dead times are added to the effective on-time. Itoccurs only in PWM mode (SKIP = high) when the induc-tor current reverses at light or negative load currents.With reversed inductor current, the inductor’s EMF caus-es LX to go high earlier than normal, extending the on-time by a period equal to the low-to-high dead time.

For loads above the critical conduction point, the actualswitching frequency is:

where VDROP1 is the sum of the parasitic voltage dropsin the inductor discharge path, including synchronousrectifier, inductor, and PC board resistances; VDROP2 isthe sum of the resistances in the charging path, and tONis the on-time calculated by the MAX1714.

Automatic Pulse-Skipping SwitchoverIn skip mode (SKIP low), an inherent automaticswitchover to PFM takes place at light loads. Thisswitchover is effected by a comparator that truncates thelow-side switch on-time at the inductor current’s zerocrossing. This mechanism causes the threshold betweenpulse-skipping PFM and nonskipping PWM operation tocoincide with the boundary between continuous and dis-continuous inductor-current operation (also known as the“critical conduction” point; see the Continuous toDiscontinuous Inductor Current Point vs. Input Voltagegraph in the Typical Operating Characteristics). In low-

duty-cycle applications, this threshold is relatively con-stant, with only a minor dependence on battery voltage.

where K is the on-time scale factor (Table 5). The load-current level at which PFM/PWM crossover occurs,ILOAD(SKIP), is equal to 1/2 the peak-to-peak ripple cur-rent, which is a function of the inductor value (Figure 3).For example, in the standard application circuit with K = 3.3µs (Table 5), VOUT = 2.5V, VIN = 15V, and L =6.8µH, switchover to pulse-skipping operation occurs atILOAD = 0.51A or about 1/8 full load. The crossover pointoccurs at an even lower value if a swinging (soft-satura-tion) inductor is used.

The switching waveforms may appear noisy and asyn-chronous when light loading causes pulse-skippingoperation, but this is a normal operating condition thatresults in high light-load efficiency. Trade-offs in PFMnoise vs. light-load efficiency are made by varying theinductor value. Generally, low inductor values produce abroader efficiency vs. load curve, while higher valuesresult in higher full-load efficiency (assuming that the coilresistance remains fixed) and less output voltage ripple.Penalties for using higher inductor values include largerphysical size and degraded load-transient response(especially at low input voltage levels).

DC output accuracy specifications refer to the error-com-parator threshold of the error comparator. When theinductor is in continuous conduction, the output voltagewill have a DC regulation level higher than the trip levelby 50% of the ripple. In discontinuous conduction (SKIP= AGND, light-loaded), the output voltage will have a DCregulation level higher than the error-comparator thresh-old by approximately 1.5% due to slope compensation.

Forced-PWM Mode (SKIP = High)The low-noise forced-PWM mode (SKIP = high) disablesthe zero-crossing comparator, which controls the low-side switch on-time. This causes the low-side gate-drivewaveform to become the complement of the high-sidegate-drive waveform. This in turn causes the inductorcurrent to reverse at light loads while DH maintains aduty factor of VOUT/VIN. The benefit of forced-PWMmode is to keep the switching frequency fairly constant,but it comes at a cost: the no-load battery current can be10mA to 40mA, depending on the external MOSFETs.

Forced-PWM mode is most useful for reducing audio-frequency noise, improving load-transient response, pro-viding sink-current capability for dynamic output voltage adjustment, and improving the cross-regulation of

IKV

2L

V - V

V LOAD(SKIP)

OUT IN OUT

IN≈ ⋅

f V V

t (V V )OUT DROP1

ON IN DROP2

=+

+

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______________________________________________________________________________________ 13

multiple-output applications that use a flyback trans-former or coupled inductor.

Current-Limit Circuit (ILIM)The current-limit circuit employs a unique “valley” cur-rent-sensing algorithm that uses the on-state resistanceof the low-side MOSFET as a current-sensing element(Figure 4). If the current-sense voltage (PGND - LX) isabove the current-limit threshold, the PWM is not allowedto initiate a new cycle. The actual peak current is greaterthan the current-limit threshold by an amount equal tothe inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are afunction of the MOSFET on-resistance, inductor value,and battery voltage. The reward for this uncertainty isrobust, lossless overcurrent sensing. When combinedwith the UVP protection circuit, this current-limit methodis effective in almost every circumstance.

There is also a negative current limit that preventsexcessive reverse inductor currents when VOUT is sink-ing current. The negative current-limit threshold is set toapproximately 120% of the positive current limit, andtherefore tracks the positive current limit when ILIM isadjusted.

The current-limit threshold is adjusted with an externalresistor-divider at ILIM. A 1µA min divider current is rec-ommended. The current-limit threshold adjustmentrange is from 50mV to 200mV. In the adjustable mode,the current-limit threshold voltage is precisely 1/10 thevoltage seen at ILIM. The threshold defaults to 100mVwhen ILIM is connected to VCC. The logic threshold forswitchover to the 100mV default value is approximatelyVCC - 1V.

The adjustable current limit accommodates MOSFETswith a wide range of on-resistance characteristics (seeDesign Procedure).

Carefully observe the PC board layout guidelines toensure that noise and DC errors don’t corrupt the cur-rent-sense signals seen by LX and PGND. Mount orplace the IC close to the low-side MOSFET with short,direct traces, making a Kelvin sense connection to thesource and drain terminals.

MOSFET Gate Drivers (DH, DL)The DH and DL drivers are optimized for driving moder-ate-sized high-side, and larger low-side powerMOSFETs. This is consistent with the low duty factorseen in the notebook environment, where a large VBATT -VOUT differential exists. An adaptive dead-time circuitmonitors the DL output and prevents the high-side FETfrom turning on until DL is fully off. There must be a low-resistance, low-inductance path from the DL driver to theMOSFET gate for the adaptive dead-time circuit to workproperly; otherwise, the sense circuitry in the MAX1714will interpret the MOSFET gate as “off” while there isactually still charge left on the gate. Use very short, widetraces measuring no more than 20 squares (50 to 100mils wide if the MOSFET is 1 inch from the MAX1714).

The dead time at the other edge (DH turning off) isdetermined by a fixed 35ns (typical) internal delay.

The internal pull-down transistor that drives DL low isrobust, with a 0.5Ω typical on-resistance. This helps pre-vent DL from being pulled up during the fast rise-time ofthe inductor node, due to capacitive coupling from thedrain to the gate of the low-side synchronous-rectifierMOSFET. However, for high-current applications, youmight still encounter some combinations of high- andlow-side FETs that will cause excessive gate-drain cou-pling, which can lead to efficiency-killing, EMI-producingshoot-through currents. This is often remedied by addinga resistor in series with BST, which increases the turn-ontime of the high-side FET without degrading the turn-offtime (Figure 5).

Figure 3. Pulse-Skipping/Discontinuous Crossover Point

INDU

CTOR

CUR

RENT

ILOAD = IPEAK/2

ON-TIME0 TIME

-IPEAKL

VBATT -VOUT∆i∆t

=

Figure 4. ‘‘Valley’’ Current-Limit Threshold Point

ILIMIT

ILOAD

0 TIME

-IPEAK

INDU

CTOR

CUR

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14 ______________________________________________________________________________________

POR, UVLO, and Soft-StartPower-on reset (POR) occurs when VCC rises aboveapproximately 2V, resetting the fault latch and soft-startcounter, and preparing the PWM for operation. VCCundervoltage lockout (UVLO) circuitry inhibits switchingand forces the DL gate driver high (to enforce outputovervoltage protection) until VCC rises above 4.2V,whereupon an internal digital soft-start timer begins toramp up the maximum allowed current limit. The rampoccurs in five steps: 20%, 40%, 60%, 80%, and 100%;100% current is available after 1.7ms ±50%.

A continuously adjustable analog soft-start function canbe realized by adding a capacitor in parallel with theILIM resistor. This soft-start method requires a minimuminterval between power-down and power-up to dis-charge the capacitor.

Power-Good Output (PGOOD)The output voltage is continuously monitored for under-voltage by the PGOOD comparator. In shutdown,standby, and soft-start, PGOOD is actively held low.After digital soft-start has terminated, PGOOD isreleased if the digital output is within 6% of the error-comparator threshold. The PGOOD output is a trueopen-drain type with no parasitic ESD diodes. Note thatthe PGOOD undervoltage detector is completely inde-pendent of the output UVP fault detector.

Output Overvoltage ProtectionThe overvoltage protection (OVP) circuit is available inthe MAX1714A only, and is designed to protect againsta shorted high-side MOSFET by drawing high currentand blowing the battery fuse. The output voltage is con-tinuously monitored for overvoltage. If the output is morethan 12.5% above the trip level of the error amplifier,overvoltage protection (OVP) is triggered and the circuitshuts down. The DL low-side gate-driver output is then latched high until SHDN is toggled or VCC power is

cycled below 1V. This action turns on the synchronous-rectifier MOSFET with 100% duty and, in turn, rapidlydischarges the output filter capacitor and forces the out-put to ground. If the condition that caused the overvolt-age (such as a shorted high-side MOSFET) persists, thebattery fuse will blow. DL is also kept high continuouslywhen VCC UVLO is active, as well as in shutdown mode(Table 3).

Note that DL latching high causes the output voltage togo slightly negative, due to energy stored in the outputLC tank circuit when OVP activates. If the load can’t tol-erate being forced to a negative voltage, it may be desir-able to place a power Schottky diode across the outputto act as a reverse-polarity clamp.

Overvoltage protection can be defeated using the no-fault test mode (see No-Fault Test Mode section).

Output Undervoltage ProtectionThe output undervoltage protection (OVP) function issimilar to foldback current limiting, but employs a timerrather than a variable current limit. If the MAX1714 out-put voltage is under 70% of the nominal value 20ms aftercoming out of shutdown, the PWM is latched off andwon’t restart until VCC power is cycled or SHDN is tog-gled. Under- voltage protection can be defeated usingthe no-fault test mode.

No-Fault Test ModeThe over/undervoltage protection features can compli-cate the process of debugging prototype breadboards,since there are (at most) a few milliseconds in which todetermine what went wrong. Therefore, a test mode isprovided to totally disable the OVP, UVP, and thermalshutdown features, and clear the fault latch if it has beenset. The PWM operates as if SKIP were grounded(PFM/PWM mode).

The no-fault test mode is entered by sinking 1.5mA fromSKIP through an external negative voltage source inseries with a resistor (Figure 6). SKIP is clamped toAGND with a silicon diode, so choose a resistor value ofapproximately (VFORCE - 0.65V) / 1.5mA.

Design ProcedureComponent selection for the MAX1714 is primarily dic-tated by the following four criteria:

1) Input voltage range. The maximum value (VIN(MAX))must accommodate the worst-case high AC adaptervoltage. The minimum value (VIN(MIN)) must accountfor the lowest battery voltage after drops due to con-nectors, fuses, and battery selector switches. Ifthere is a choice at all, lower input voltages result inbetter efficiency.

BST

+5VVIN

5Ω

DH

LX

MAX1714

Figure 5. Reducing the Switching-Node Rise Time

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2) Maximum load current. There are two values to con-sider. The peak load current (ILOAD(MAX)) determinesthe instantaneous component stresses and filteringrequirements, and thus drives output capacitor selec-tion, inductor saturation rating, and the design of thecurrent-limit circuit. The continuous load current(ILOAD) determines the thermal stresses and thus dri-ves the selection of input capacitors, MOSFETs, andother critical heat-contributing components. Modernnotebook CPUs generally exhibit:

ILOAD = ILOAD(MAX) · 80%

3) Switching frequency. This choice determines thebasic trade-off between size and efficiency. The opti-mal frequency is largely a function of maximum input

voltage, due to MOSFET switching losses that areproportional to frequency and VIN2. The optimum fre-quency is also a moving target, due to rapid improve-ments in MOSFET technology that are making higherfrequencies more practical (Table 4).

4) Inductor operating point. This choice providestrade-offs between size vs. efficiency. Low inductorvalues cause large ripple currents, resulting in thesmallest size, but poor efficiency and high output rip-ple. The minimum practical inductor value is one thatcauses the circuit to operate at the edge of criticalconduction (where the inductor current just toucheszero with every cycle at maximum load). Inductor val-ues lower than this grant no further size-reductionbenefit.

The MAX1714’s pulse-skipping algorithm initiates skipmode at the critical conduction point. So, the inductoroperating point also determines the load-current valueat which PFM/PWM switchover occurs.

These four factors impact the component selectionprocess. Selecting components and calculating theireffect on the MAX1714’s operation is best done with aspreadsheet. Using the formulas provided, calculate theLIR (the ratio of the inductor ripple current to thedesigned maximum load current) for both the minimumand maximum input voltages. Maintaining an LIR within a20% to 50% range is prudent. The use of a spreadsheetallows quick evaluation of component selection.

Table 3. Operating Mode Truth TableSHDN SKIP DL MODE COMMENTS

0 X High Shutdown Low-power shutdown state. DL is forced to VDD, enforcing OVP. ICC < 1µA typ.

1BelowAGND

Switching No FaultTest mode with OVP, UVP, and thermal faults disabled and latches cleared. Otherwisenormal operation, with automatic PWM/PFM switchover for pulse skipping at light loads(Figure 6).

1 VCC SwitchingRun (PWM),Low Noise

Low-noise operation with no automatic switchover. Fixed-frequency PWM action isforced regardless of load. Inductor current reverses at light load levels. Low noise, high IQ.

1 AGND SwitchingRun

(PFM/PWM)Normal operation with automatic PWM/PFM switchover for pulse skipping at light loads.Best light-load efficiency.

1 X High FaultFault latch has been set by OVP, output UVLO, or thermal shutdown. Device will remainin FAULT mode until VCC power is cycled, SKIP is forced below ground (Figure 6), orSHDN is toggled.

APPROXIMATELY -0.65V

1.5mA

VFORCE

SKIP

AGND(GND)


MAX1714

Figure 6. Disabling Over/Undervoltage Protection (No-Fault Test Mode)

Inductor SelectionThe switching frequency and inductor operating pointdetermine the inductor value as follows:

Example: ILOAD(MAX) = 8A, VIN = 7V, VOUT = 1.5V, f = 300kHz, 33% ripple current or LIR = 0.33.

Find a low-loss inductor having the lowest possible DCresistance that fits in the allotted dimensions. Ferritecores are often the best choice, although powdered ironis inexpensive and can work well at 200kHz. The coremust be large enough not to saturate at the peak induc-tor current (IPEAK).

IPEAK = ILOAD(MAX) + [(LIR / 2) · ILOAD(MAX)]

Most inductor manufacturers provide inductors in stan-dard values, such as 1.0µH, 1.5µH, 2.2µH, 3.3µH, etc.Also look for nonstandard values, which can provide abetter compromise in LIR across the input voltage range.For example, Sumida offers 3.1µH and 4.4µH in theirCDRH125 series. If using a swinging inductor (where theno-load inductance decreases linearly with increasingcurrent), evaluate the LIR with properly scaled induc-tance values.

Transient Response The inductor ripple current also impacts transient-response performance, especially at low VIN - VOUT dif-ferentials. Low inductor values allow the inductorcurrent to slew faster, replenishing charge removedfrom the output filter capacitors by a sudden load step.

The amount of output sag is also a function of the maxi-mum duty factor, which can be calculated from the on-time and minimum off-time:

where

and minimum off-time = 400ns typ (see Table 5 for K val-ues).

The amount of overshoot during a full-load to no-loadtransient due to stored inductor energy can be calculatedas:

where IPEAK is the peak inductor current.

Setting the Current LimitThe minimum current-limit threshold must be highenough to support the maximum load current. The valleyof the inductor current occurs at ILOAD(MAX) minus halfof the ripple current (Figure 4); therefore:

ILIMIT(LOW) > ILOAD(MAX) - (LIR / 2) ILOAD(MAX)

where ILIMIT(LOW) equals minimum current-limit thresh-old voltage divided by the RDS(ON) of Q2. For theMAX1714, the minimum current-limit threshold using the100mV default setting is 90mV. Use the worst-case maxi-mum value for RDS(ON) from the MOSFET Q2 data sheet,and add some margin for the rise in RDS(ON) with tem-perature. A good general rule is to allow 0.5% additionalresistance for each °C of temperature rise.

Examining the 8A circuit example with a maximumRDS(ON) = 12mΩ at high temperature reveals the follow-ing:

ILIMIT(LOW) = 90mV / 12mΩ = 7.5A

This 7.5A is greater than the valley current of 6.7A, so thecircuit can easily deliver the full rated 8A using the default100mV nominal ILIM threshold.

For an adjustable threshold, connect a two-resistordivider from REF to AGND, with ILIM connected at thecenter tap. The external adjustment range of 0.5V to 2.0Vcorresponds to a current-limit threshold of 50mV to200mV. When adjusting the current limit, use 1% toler-ance resistors to prevent a significant increase of errors in

VL I

2C VSOAR

PEAK2

OUT OUT≈

⋅

V( I ) L

2 C DUTY (V - V ) SAG

LOAD(MAX)2

F IN(MIN) OUT

=⋅

⋅ ⋅∆

L1.5V (7V -1.5V)

7V 300kHz 0.33 8A 1.49 H= =

⋅ ⋅ ⋅µ

L = V (V - V )

V f LIR IOUT IN OUT

IN LOAD(MAX) ⋅ ⋅ ⋅

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Good operating point forcompound buck designsor desktop circuits.

+5V input600

TON = AGND

450TON = REF

3-cell Li+ notebook

Useful in 3-cell systemsfor lighter loads than theCPU core or where size iskey.

Considered mainstreamby current standards.

4-cell Li+ notebook 300

TON = Float

200 TON = VCC

4-cell Li+ notebook Use for absolute bestefficiency.

COMMENTSTYPICAL

APPLICATIONFREQUENCY

(kHz)

Table 4. Frequency Selection Guidelines

DUTYK (V + 0.075V) V

K (V + 0.075V) V + min off - timeOUT IN

OUT OUT =

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______________________________________________________________________________________ 17

the current-limit tolerance. A 1µA minimum divider currentis recommended.

Output Capacitor SelectionThe output filter capacitor must have low enough effectiveseries resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to sat-isfy stability requirements. Also, the capacitance valuemust be high enough to absorb the inductor energygoing from a full-load to no-load condition without trippingthe overvoltage protection circuit.

In CPU VCORE converters and other applications wherethe output is subject to violent load transients, the outputcapacitor’s size depends on how much ESR is needed toprevent the output from dipping too low under a loadtransient. Ignoring the sag due to finite capacitance:

In non-CPU applications, the output capacitor’s sizedepends on how much ESR is needed to maintain anacceptable level of output voltage ripple:

The actual microfarad capacitance value required relatesto the physical size needed to achieve low ESR, as wellas to the chemistry of the capacitor technology. Thus, thecapacitor is usually selected by ESR and voltage ratingrather than by capacitance value (this is true of tantalums,OS-CONs, and other electrolytics).

When using low-capacity filter capacitors such as ceram-ic or polymer types, capacitor size is usually determinedby the capacity needed to prevent VSAG and VSOAR fromcausing problems during load transients. Generally, onceenough capacitance is added to meet the overshootrequirement, undershoot at the rising load edge is nolonger a problem (also, see the VSAG and VSOAR equa-tion in the Transient Response section).

Output Capacitor Stability ConsiderationsStability is determined by the value of the ESR zero rela-tive to the switching frequency. The point of instability isgiven by the following equation:

For a typical 300kHz application, the ESR zero frequencymust be well below 95kHz, preferably below 50kHz.

Tantalum and OS-CON capacitors in widespread use atthe time of publication have typical ESR zero frequenciesof 25kHz. In the design example used for inductor selec-tion, the ESR needed to support 50mVp-p ripple is 60mV/2.7A = 22mΩ. Two 470µF/4V Kemet T510 low-ESRtantalum capacitors in parallel provide 22mΩ max ESR.Their typical combined ESR results in a zero at 27kHz,well within the bounds of stability.

Don’t put high-value ceramic capacitors directly acrossthe feedback sense point without taking precautions toensure stability. Large ceramic capacitors can have ahigh ESR zero frequency and cause erratic, unstableoperation. However, it’s easy to add enough series resis-tance by placing the capacitors a couple of inchesdownstream from the feedback sense point, whichshould be as close as possible to the inductor (see theAll-Ceramic-Capacitor Application section).

Unstable operation manifests itself in two related but dis-tinctly different ways: double-pulsing and fast-feedbackloop instability.

Double-pulsing occurs due to noise on the output orbecause the ESR is so low that there isn’t enough volt-age ramp in the output voltage signal. This “fools” theerror comparator into triggering a new cycle immediatelyafter the 400ns minimum off-time period has expired.Double-pulsing is more annoying than harmful, resultingin nothing worse than increased output ripple. However,it can indicate the possible presence of loop instability,which is caused by insufficient ESR.

Loop instability can result in oscillations at the output after line or load perturbations that can trip the overvolt-age protection latch or cause the output voltage to fallbelow the tolerance limit.

The easiest method for checking stability is to apply avery fast zero-to-max load transient and carefullyobserve the output voltage ripple envelope for over-shoot and ringing. It can help to simultaneously monitorthe inductor current with an AC current probe. Don’tallow more than one cycle of ringing after the initialstep-response under- or overshoot.

Input Capacitor SelectionThe input capacitor must meet the ripple currentrequirement (IRMS) imposed by the switching currents.Nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to power-upsurge currents.

I IV V - V

V RMS LOAD

OUT IN OUT

IN=

( )

ff

where f1

2 R C

ESR

ESRESR F

=

=⋅ ⋅ ⋅

π

π

RVp- p

LIR IESR

LOAD(MAX)

≤⋅

RV

IESR

DIP

LOAD(MAX)

≤

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For optimal circuit reliability, choose a capacitor thathas less than 10°C temperature rise at the peak ripplecurrent.

Power MOSFET SelectionMost of the following MOSFET guidelines focus on thechallenge of obtaining high load-current capability (>5A)when using high-voltage (>20V) AC adapters. Low-cur-rent applications usually require less attention.

For maximum efficiency, choose a high-side MOSFET(Q1) that has conduction losses equal to the switchinglosses at the optimum battery voltage (15V). Check toensure that the conduction losses at minimum inputvoltage don’t exceed the package thermal limits or violate the overall thermal budget. Check to ensure thatconduction losses plus switching losses at the maxi-mum input voltage don’t exceed the package ratings orviolate the overall thermal budget.

Choose a low-side MOSFET (Q2) that has the lowestpossible RDS(ON), comes in a moderate to small pack-age (i.e., SO-8), and is reasonably priced. Ensure thatthe MAX1714 DL gate driver can drive Q2; in otherwords, check that the gate isn’t pulled up by the high-side switch turn on, due to parasitic drain-to-gate capac-itance, causing cross-conduction problems. Switchinglosses aren’t an issue for the low-side MOSFET, since it’sa zero-voltage switched device when used in the bucktopology.

MOSFET Power DissipationWorst-case conduction losses occur at the duty factorextremes. For the high-side MOSFET, the worst-casepower dissipation due to resistance occurs at minimumbattery voltage:

PD(Q1 Resistive) = (VOUT / VIN(MIN)) · ILOAD2 · RDS(ON)

Generally, a small high-side MOSFET is desired toreduce switching losses at high input voltages. However,the RDS(ON) required to stay within package power-dissi-pation limits often limits how small the MOSFET can be.Again, the optimum occurs when the switching (AC)losses equal the conduction (RDS(ON)) losses. High-sideswitching losses don’t usually become an issue until theinput is greater than approximately 15V.

Switching losses in the high-side MOSFET can becomean insidious heat problem when maximum AC adaptervoltages are applied, due to the squared term in theCV2F switching loss equation. If the high-side MOSFETyou’ve chosen for adequate RDS(ON) at low battery volt-ages becomes extraordinarily hot when subjected toVIN(MAX), you must reconsider your choice of MOSFET.

Calculating the power dissipation in Q1 due to switchinglosses is difficult, since it must allow for difficult-to-quanti-

fy factors that influence the turn-on and turn-off times.These factors include the internal gate resistance, gatecharge, threshold voltage, source inductance, and PCboard layout characteristics. The following switching losscalculation provides only a very rough estimate and is nosubstitute for breadboard evaluation, preferably includinga sanity check using a thermocouple mounted on Q1.

where CRSS is the reverse transfer capacitance of Q1and IGATE is the peak gate-drive source/sink current (1Atypical).

For the low-side MOSFET, Q2, the worst-case power dis-sipation always occurs at maximum battery voltage:

PD(Q2) = (1 - VOUT / VIN(MAX)) · ILOAD2 · RDS(ON)

The absolute worst case for MOSFET power dissipationoccurs under heavy overloads that are greater thanILOAD(MAX) but are not quite high enough to exceed thecurrent limit and cause the fault latch to trip. To protectagainst this possibility, you must “overdesign” the circuitto tolerate ILOAD = ILIMIT(HIGH) + [(LIR / 2) · ILOAD(MAX)],where ILIMIT(HIGH) is the maximum valley current allowedby the current-limit circuit, including threshold toleranceand on-resistance variation. This means that theMOSFETs must be very well heatsinked. If short-circuitprotection without overload protection is enough, a nor-mal ILOAD value can be used for calculating componentstresses.

Choose a Schottky diode D1 having a forward voltagelow enough to prevent the Q2 MOSFET body diode fromturning on during the dead time. As a general rule, adiode having a DC current rating equal to 1/3 of the loadcurrent is sufficient. This diode is optional, and if efficien-cy isn’t critical it can be removed.

Application IssuesDropout Performance

The output voltage adjust range for continuous-conduc-tion operation is restricted by the nonadjustable 500ns(max) minimum off-time one-shot. For best dropout per-formance, use the slowest (200kHz) on-time setting.When working with low input voltages, the duty-factorlimit must be calculated using worst-case values for on-and off-times. Manufacturing tolerances and internalpropagation delays introduce an error to the TON K-fac-tor. This error is greater at higher frequencies (Table 5).Also, keep in mind that transient response performanceof buck regulators operated close to dropout is poor,

PD(Q1 switching)C V f I

I

RSS IN(MAX)2

LOAD

GATE=

⋅ ⋅ ⋅

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______________________________________________________________________________________ 19

and bulk output capacitance must often be added (seethe VSAG equation in Transient Response section).

Dropout Design Example: VIN = 3V min, VOUT = 2V, f = 300kHz. The required duty is (VOUT + VSW) / (VIN -VSW) = (2V + 0.1V) / (3.0V - 0.1V) = 72.4%. The worst-case on-time is (VOUT + 0.075) / VIN · K = 2.075V / 3V ·3.35µs-V · 90% = 2.08µs. The IC duty-factor limitation is:

which meets the required duty.

Remember to include inductor resistance and MOSFETon-state voltage drops (VSW) when doing worst-casedropout duty-factor calculations.

All-Ceramic-Capacitor ApplicationCeramic capacitors have advantages and disadvan-tages. They have ultra-low ESR, are noncombustible, arerelatively small, and are nonpolarized. On the otherhand, they’re expensive and brittle, and their ultra-lowESR characteristic can result in excessively high ESRzero frequencies (affecting stability). In addition, their rel-atively low capacitance value can cause output over-shoot when going abruptly from full-load to no-loadconditions, unless there are some bulk tantalum or elec-trolytic capacitors in parallel to absorb the stored energyin the inductor. In some cases, there may be no room forelectrolytics, creating a need for a DC-DC design thatuses nothing but ceramics.

The all-ceramic-capacitor application of Figure 7replaces the standard, typical tantalum output capacitorswith ceramics in a 7A circuit. This design relies on hav-ing a minimum of 5mΩ parasitic PC board trace resis-tance in series with the capacitor in order to reduce theESR zero frequency. This small amount of resistance iseasily obtained by locating the MAX1714 circuit 2 or 3inches away from the CPU, and placing all the ceramic

DUTYt

t t

2.08 s

2.08 s 500ns80.6%,

ON(MIN)

ON(MIN) OFF(MAX)=

+=

+=µ

µ

V+ VCC

VIN = 7V TO 24V*

SHDN

SKIP

REF

ON/OFF

0.22µF

DL

LX

FB

BST5Ω

DH

PGND (GND)

AGND (GND)

OUT


Q1

+5V

20Ω1µF

1µF

Q2

0.5µH0.1µF

C1

1k

R1

C2 CPU

2.5V AT 7A

VDDILIM

MAX1714

R2

C1 = 2 x 10µF/25V TAIYO YUDEN (1812) (TMK432BJ106AM)C2 = 6 x 47µF/6.3V TAIYO YUDEN (1812) (JMK432BJ476MN)R1 + R2 = 5mΩ MINIMUM OF PCB TRACE RESISTANCE (TOTAL)

TON

* FOR HIGHER MINIMUM INPUT VOLTAGE, * LESS OUTPUT CAPACITANCE IS ACCEPTABLE.

Figure 7. All-Ceramic-Capacitor Application

Table 5. Approximate K-Factor ErrorsTON

SETTING(kHz)

APPROXIMATEK-FACTORERROR (%)

MIN VINAT VOUT = 2V

(V)

200 ±10 2.6

300 ±10 2.9

450 ±12.5 3.2

600 ±12.5 3.6

KFACTOR

(µs)

5

3.3

2.2

1.7

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20 ______________________________________________________________________________________

capacitors close to the CPU. Resistance values higherthan 5mΩ just improve the stability (which can beobserved by examining the load-transient responsecharacteristic as shown in the Typical OperatingCharacteristics). Avoid adding excess PC board traceresistance, as there’s an efficiency penalty; 5mΩ is suffi-cient for a 7A circuit.

VSOAR determines the minimum output capacitancerequirement. In this example, the switching frequencyhas been increased to 600kHz and the inductor valuehas been reduced to 0.5µH (compared to 300kHz and1.5µH for the standard 8A circuit) in order to minimize theenergy transferred from inductor to capacitor duringload-step recovery. The overshoot must be calculated toavoid tripping the OVP latch. The efficiency penalty foroperating at 600kHz is about 2% to 3%, depending onthe input voltage.

An optional 1kΩ resistor is placed in series with OUT.This resistor attenuates high-frequency noise in someboards, which can cause double pulsing.

Fixed Output VoltagesThe MAX1714’s Dual Mode™ operation allows the selec-tion of common voltages without requiring external com-ponents (Figure 8). Connect FB to AGND for a fixed+2.5V output or to VCC for a +3.3V output, or connect FBdirectly to OUT for a fixed +1.0V output.

Setting VOUT with a Resistor-DividerThe output voltage can be adjusted with a resistor-divider if desired (Figure 9). The equation for adjustingthe output voltage is:

where VFB is 1.0V.

2-Stage (5V Powered) Notebook CPU Buck Regulator

The most efficient and overall cost-effective solution forstepping down a high-voltage battery to a very low out-put voltage is to use a single-stage buck regulator that’spowered directly from the battery. However, there maybe situations where the battery bus can’t be routed nearthe CPU, or where space constraints dictate the smallestpossible local DC-DC converter. In such cases, the 5Vpowered circuit of Figure 10 may be appropriate. Thereduced input voltage allows a higher switching frequen-cy and a much smaller inductor value.

PC Board Layout GuidelinesCareful PC board layout is critical to achieving lowswitching losses and clean, stable operation. The switch-ing power stage requires particular attention (Figure 11).If possible, mount all of the power components on thetop side of the board with their ground terminals flushagainst one another. Follow these guidelines for good PCboard layout:

• Keep the high-current paths short, especially at theground terminals. This practice is essential for stable,jitter-free operation.

• Connect AGND and PGND together close to the IC.For the MAX1714B, these grounds are connectedinternally to the GND pin. Carefully follow the ground-ing instructions under step 4 of the Layout Procedure.

• Keep the power traces and load connections short.This practice is essential for high efficiency. Usingthick copper PC boards (2 oz vs. 1 oz) can enhancefull-load efficiency by 1% or more. Correctly routingPC board traces is a difficult task that must beapproached in terms of fractions of centimeters,

V V 1 R1

R2OUT FB= +

2V

0.2V

OUT

FB

FIXED2.5V

TO ERROR AMP

FIXED3.3V

MAX1714

Figure 8. Feedback Mux Dual Mode is a trademark of Maxim Integrated Products.

R1

2FCESR

OUT≥

where a single milliohm of excess trace resistancecauses a measurable efficiency penalty.

• LX and PGND connections to Q2 for current limitingmust be made using Kelvin sense connections toguarantee the current-limit accuracy. With SO-8MOSFETs, this is best done by routing power to theMOSFETs from outside using the top copper layer,while tying in PGND and LX inside (underneath) theSO-8 package.

• When trade-offs in trace lengths must be made, it’spreferable to allow the inductor charging path to bemade longer than the discharge path. For example,it’s better to allow some extra distance between theinput capacitors and the high-side MOSFET than toallow distance between the inductor and the low-side MOSFET or between the inductor and the out-put filter capacitor.

• Ensure that the OUT connection to COUT is short anddirect. However, in some cases it may be desirable todeliberately introduce some trace length between theOUT inductor node and the output filter capacitor (seethe All-Ceramic-Capacitor Application section).

• Route high-speed switching nodes (BST, LX, DH, andDL) away from sensitive analog areas (REF, FB).

• Make all pin-strap control input connections (SKIP,ILIM, etc.) to AGND or VCC rather than PGND or VDD.

Layout Procedure1) Place the power components first, with ground termi-

nals adjacent (Q2 source, CIN-, COUT-, D1 anode). Ifpossible, make all these connections on the top layerwith wide, copper-filled areas.

2) Mount the controller IC adjacent to MOSFET Q2,preferably on the back side opposite Q2 in order tokeep LX, PGND, and the DL gate-drive lines short andwide. The DL gate trace must be short and wide,measuring 10 to 20 squares (50 to 100 mils wide if theMOSFET is 1 inch from the controller IC).

3) Group the gate-drive components (BST diode andcapacitor, VDD bypass capacitor) together near thecontroller IC.

4) Make the DC-DC controller ground connections asshown in Figure 11. This diagram can be viewed ashaving three separate ground planes: output ground,where all the high-power components go; the PGNDplane, where the PGND pin and VDD bypass capaci-tor go; and an analog AGND plane, where sensitiveanalog components go. The analog ground plane andPGND plane must meet only at a single point directlybeneath the IC. For the MAX1714B, this point shouldbe the GND pin. These two planes are then connect-ed to the high-power output ground with a short con-nection from VDD cap/PGND to the source of thelow-side MOSFET, Q2 (the middle of the star ground).This point must also be very close to the outputcapacitor ground terminal.

5) Connect the output power planes (VCORE and systemground planes) directly to the output filter capacitorpositive and negative terminals with multiple vias.Place the entire DC-DC converter circuit as close tothe CPU as is practical.

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______________________________________________________________________________________ 21

DL

AGND

OUT

PGND(GND)

(GND)


DH

FB

VBATT

VOUT

R1

R2

MAX1714

Figure 9. Setting VOUT with a Resistor-Divider

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22 ______________________________________________________________________________________

ILIM VCC

VIN 4.5V TO 5.5V

L10.5µH

VOUT 2.5V AT 7A

SHDN

1µF

0.1µF

0.22µF

C23 x 470µFKEMET T510

IRF7805

IRF7805

1µF 20Ω

C14 x 10µF/25V

ON/OFF

DL

LX

BST

DH

PGND(GND)

(GND)( ) = ARE FOR THE MAX1714B ONLY.NOTE: IN THE MAX1714B, AGND AND PGND ARE INTERNALLY CONNECTED TO THE GND PIN.

OUT

FB

AGND

VDD

VCC

V+

MAX1714

REF

TON SKIP

100k

PGOOD

Figure 10. 5V Powered, 7A CPU Buck Regulator

Pin Configurations

TOP VIEW

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

LX

BST

SKIP

V+FB

SHDN

N.C.

DH

TON

VCC

VDD

DLAGND

REF

ILIM

OUT

12

11

9

10

PGND

N.C.PGOOD

N.C.

MAX1714A

QSOP

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

LX

BST

SKIP

V+OUT

FB

SHDN

DH

TON

VCC

VDD

DLGND

PGOOD

REF

ILIM

QSOP

MAX1714B

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______________________________________________________________________________________ 23

D1 Q2

VBATT GND IN

COUT

VIA TO OUTNEAR COUT+

VIA TO LX

VIA TO SOURCEOF Q2

VIA TO PGNDNEAR Q2 SOURCE

INDUCTOR DISCHARGE PATH HAS LOW DC RESISTANCE.

GNDOUT

VOUT

L1

Q1

VCC

VDD

REF

AGND

ALL ANALOG GROUNDS CONNECT TO AGND ONLY

NOTES: "STAR" GROUND IS USED. D1 IS DIRECTLY ACROSS Q2.

CONNECT AGND TO PGNDBENEATH IC, 1 POINT ONLY. SPLIT ANALOG GND PLANE AS SHOWN.

ILIM

MAX1714

CIN

Figure 11. Power-Stage PC Board Layout Example

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Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses areimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

QS

OP

.EP

S

Package Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to www.maxim-ic.com/packages.)

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