Exam 2 ReviewCOMP375

Computer Architecture and Organization

“Talk is cheap. Show me the code.”

Linus Torvalds

Second Exam

• The 2nd COMP375 exam in on Friday, October 25, 2019

• The exam should be graded and returned on Monday

• Tuesday is the last day to drop

Topics• Microcode chapter 16 & 19

• VLSI

• Digital logic chapter 12

• Memory types sections 4

• Cache section 5

Topics not covered in class will not be on the exam

The exam may contain questions from any of the material covered in class since the last exam

One Page of Notes

• You are allowed one and only one 8½ by 11 inch page of notes during this exam

• You are not allowed to use more than 187 square inches of paper surface

• You will do better if you make your own page of notes and not copy your friend’s notes

Simple CPU

Follow the Fetch/Execute Cycle

• The steps of the fetch/execute cycle are reflected in the microcode

1. Read the instruction from memory

2. Increment the program counter

3. Get the operands

4. Execute the instruction

5. Save the results

Microcode Rules

• Only one register can put a value on the bus at a time

• Multiple registers can copy a value from the bus

• A register cannot copy a value from the bus if no other register is putting a value on the bus

• A memory read is required ONLY for memory, not registers

• Only the last line of the instruction fetch puts something in the instruction register

Instruction Fetch &Program Counter Increment

bus

IR

IR

adr

bus

res

ult

bus

bus

A

L

U

bus

opr

nd

bus

PC

PC

bus

bus

R1

R1

bus

bus

R2

R2

bus

bus

MA

R

bus

M

B

R

M

B

R

bus

A

L

U

fun

Mem

func

X X X inc read

X X wait

X X

ALU(“inc”) = MAR = PC;Memory.read();PC = result;Memory.wait();IR = MBR;

Remember the Fetch and PC Increment

• The fetch/execute cycle always starts with reading the instruction from memory and incrementing the program counter

• In our simple computer, this takes three lines of microcode

• This is the only time anything is loaded into the instruction register

Jump Instructions

• The last microcode step of a jump is almost always copies a value into the program counter

• Jump instructions rarely access memory unless they are pushing or popping something on the stack

Arithmetic

• Most arithmetic instructions have the steps

–Copy something into the operand reg

–Put a value on the bus and do it

–Copy the result register someplace

• In a more realistic system, the ALU function would be determined by the opcode of the instruction

Subtract R1, cow

Instruction fetch not shown

bu

s

IR

IR

adr

bus

res

ult

bus

bus

A

L

U

bus

opr

nd

bus

PC

PC

bus

bus

R1

R1

bus

bus

R2

R2

bus

bus

M

A

R

bus

M

B

R

M

B

R

bus

ALU

func

Mem

func

X X read

X X wait

X X sub

X X

MBR = IRaddr;Memory.read();Operand = R1;Memory.wait();ALU(“sub”) = MBR;R1 = result;

Write the Microcode• Write the microcode (any format) to zero R1 (XOR R1 with

itself or subtract R1 from R1)

bu

s

IR

IR

adr

bus

res

ult

bus

bus

A

L

U

bus

opr

nd

bus

PC

PC

bus

bus

R1

R1

bus

bus

R2

R2

bus

bus

M

A

R

bus

M

B

R

M

B

R

bus

ALU

func

Mem

func

Possible Solution• Write the microcode (any format) to zero R1 (XOR R1 with

itself or subtract R1 from R1)

bu

s

IR

IR

adr

bus

res

ult

bus

bus

A

L

U

bus

opr

nd

bus

PC

PC

bus

bus

R1

R1

bus

bus

R2

R2

bus

bus

M

A

R

bus

M

B

R

M

B

R

bus

ALU

func

Mem

func

X X

X X xor

X X

operand = R1;ALU(“XOR”) = R1;R1 = result;

Program Memory Organization

Heap

Stack

Global data

Program instructions

Memory Types

Static RAM Dynamic RAM

Created with 6 transistors Created with 1 transistor

High power use Low power use

No refreshing Requires refreshing

Equal read & write time Writes faster than reads

Fastest fast

Used in cache Used in RAM

What type of memory technology would you use to hold the program

of your prototype?• Imagine you are building a prototype of a weather

toaster. The weather toaster connects to the Internet and burns today’s weather report into your morning toast.

A. DRAM

B. SRAM

C. EPROM

D. flip flop

Weather ToasterAny type of programmable read-only memory (PROM) would work well. You want non-volatile read only memory because it must hold the program when the toaster is turned off. Because this is a prototype, you are likely to be changing the program frequently. Therefore the PROM should be changeable.

NPN Transistor Stick Diagram

Source Drain

Gate

Conducts when the gate has current

PNP Transistor Stick Diagram

Source Drain

Gate

Conducts when the gate does not have current

NAND Gate• When either A or B is 0, the output is connected to power

• When both A and B are one, the output is connected to ground

A B output

0 0 1

0 1 1

1 0 1

1 1 0

Complete the Truth Table for this transistor circuit

A B output

0 0

0 1

1 0

1 1

Sum of Product Equation for Segment “a”

C’D’ C’D CD CD’

A’B’

A’B

AB

AB’

A B C D # a

0 0 0 0 0 1

0 0 0 1 1 0

0 0 1 0 2 1

0 0 1 1 3 1

0 1 0 0 4 0

0 1 0 1 5 1

0 1 1 0 6 0

0 1 1 1 7 1

1 0 0 0 8 1

1 0 0 1 9 1

Sum of Product Equation for Segment “a”

C’D’ C’D CD CD’

A’B’ 1 0 1 1

A’B 0 1 1 0

AB d d d d

AB’ 1 1 d d

A B C D # a

0 0 0 0 0 1

0 0 0 1 1 0

0 0 1 0 2 1

0 0 1 1 3 1

0 1 0 0 4 0

0 1 0 1 5 1

0 1 1 0 6 0

0 1 1 1 7 1

1 0 0 0 8 1

1 0 0 1 9 1

Simplify Segment “d”

C’D’ C’D CD CD’

A’B’

A’B

AB

AB’

A B C D # d

0 0 0 0 0 1

0 0 0 1 1 0

0 0 1 0 2 1

0 0 1 1 3 1

0 1 0 0 4 0

0 1 0 1 5 1

0 1 1 0 6 1

0 1 1 1 7 0

1 0 0 0 8 1

1 0 0 1 9 0

Simplified Segment “d”

C’D’ C’D CD CD’

A’B’ 1 0 1 1

A’B 0 1 0 1

AB d d d d

AB’ 1 0 d d

A B C D # d

0 0 0 0 0 1

0 0 0 1 1 0

0 0 1 0 2 1

0 0 1 1 3 1

0 1 0 0 4 0

0 1 0 1 5 1

0 1 1 0 6 1

0 1 1 1 7 0

1 0 0 0 8 1

1 0 0 1 9 0

Simplified Segment “d”

C’D’ C’D CD CD’

A’B’ 1 0 1 1

A’B 0 1 0 1

AB d d d d

AB’ 1 0 d d

A B C D # d

0 0 0 0 0 1

0 0 0 1 1 0

0 0 1 0 2 1

0 0 1 1 3 1

0 1 0 0 4 0

0 1 0 1 5 1

0 1 1 0 6 1

0 1 1 1 7 0

1 0 0 0 8 1

1 0 0 1 9 0 F = B’D’ + B’C + CD’ + BC’D

Locality of Reference

• Temporal Locality

– A memory location that is referenced is likely to be accessed again in the near future

• Spatial Locality

– Memory locations near the last access are likely to be accessed in the near future

Average Access Time• Let

– h = hit rate

– c = Time to access the cache

– m = Time to access the RAM

Access time = h * c + (1-h) * m

Example:

c = 6 ns, m = 60ns and h = 90%

Access = 0.9*6ns + (1-0.9)*60ns = 11.5ns

Number of Correction Bits

• To detect and correct a single bit error

d + p + 1 ≤ 2p

where:

–d is the number of data bits

–p is the number of check bits

approximately p = log2(d) + 1

example:

for 32 data bits, you need 6 check bits

Mapping

• The memory system has to quickly determine if a given address is in the cache

• There are three popular methods of mapping addresses to cache locations

– Fully Associative – Search the entire cache for an address

–Direct – Each address has a specific place in the cache

– Set Associative – Each address can be in any of a small set of cache locations

How many correct bits are required for a 64 bit word?

A. 6

B. 7

C. 8

D. 64

Direct Mapping• Each location in RAM has one specific place in

cache where the data will be held

• Consider the cache to be like an array. Part of the address is used as index into the cache to identify where the data will be held

• Since a data block from RAM can only be in one specific line in the cache, it must always replace the one block that was already there. There is no need for a replacement algorithm.

Direct Cache Addressing

• The lower log2(line size) bits define which byte in the block

• The next log2(number of lines) bits defines which line of the cache

• The remaining upper bits are the tag field

Tag Line Offset

Cache Constants

• cache size / line size = number of lines

• log2(line size) = bits for offset

• log2(number of lines) = bits for cache index

• remaining upper bits = tag address bits

Example direct addressAssume you have

• 32 bit addresses (can address 4 GB)

• 64 byte lines (offset is 6 bits)

• 32 KB of cache

• Number of lines = 32 KB / 64 = 512

• Bits to specify which line = log2(512) = 9

Tag Line Offset

6 bits9 bits17 bits

How many bits are in the tag, line and offset fields?

Direct Mapping

40 bit addresses

2MB bytes of cache

64 byte cache lines

A. tag=20, line=16, offset=4

B. tag=40, line=14, offset=6

C. tag=19, line=15, offset=6

D. tag=19, line=21, offset=6

Associative Mapping• In associative cache mapping, the data from any

location in RAM can be stored in any location in cache

• When the processor wants an address, all tag fields in the cache as checked to determine if the data is already in the cache

• Each tag line requires circuitry to compare the desired address with the tag field

• All tag fields are checked in parallel

Associative Cache Mapping

• The lower log2(line size) bits define which byte in the block

• The remaining upper bits are the tag field.

• For a 4 GB address space with 128 KB cache and 32 byte blocks:

Tag Offset

5 bits27 bits

Set Associative Mapping• Set associative mapping is a mixture of direct and

associative mapping

• The cache lines are grouped into sets

• The number of lines in a set can vary from 2 to 24

• A portion of the address is used to specify which set will hold an address

• The data can be stored in any of the lines in the set

Set Associative Mapping

• When the processor wants an address, it indexes to the set and then searches the tag fields of all lines in the set for the desired address

• n = cache size / line size = number of lines

• b = log2(line size) = bit for offset

• w = number of lines / set

• s = n / w = number of sets

Example Set AssociativeAssume you have

• 32 bit addresses

• 32 KB of cache 64 byte lines

• Number of lines = 32 KB / 64 = 512

• 4 way set associative

• Number of sets = 512 / 4 = 128

• Set bits = log2(128) = 7

Tag Set Offset

6 bits7 bits19 bits

How many bits are in the tag, set and offset fields?

4-way Set Associative

32 bit addresses

256K bytes of cache

32 byte cache lines

A. tag=16, set = 11, offset=5

B. tag=14, set = 13, offset=5

C. tag=11, set = 18, offset=5

D. tag=15, set = 12, offset=5

Program Memory Organization

Heap

Stack

Global data

Program instructions

Likely Test Questions

• Microcode for instruction

• Simplify and draw logic circuit

• Select the proper memory for an application

• Divide address into cache field

• Something from the CPU design assignment