exam review - doe.carleton.cajknight/97.267/2607_09w/wb/... · in the spirit of the code of honor...

Writing Exams:

© John Knight Electronics Department, Carleton University March 2, 2009

1

Writing Exams

Exam Review

Writing ExamsAsynchronous Circuits

Races, Cycles and State AssignmentSynchronous Circuits

State-Graph Constructionand Small Problems

AlsoMultiple Outputs,

and a Harder Combinational Problem

AX+X

=X

Writing Exams:


2

Writing Exams

1 Boolean If you use a map, indicate in the space underneath it, for which function it is. If you use algebra, indicate the rules used at the right side of each line.

Especially for Absorption, D2, Swap, Concesus and other less obvious onesMarks will be deducted if you don’t!

a) Simplify g= ABC +DEF + PEH +JKL +MNG

In the spirit of the code of honor of Carleton University I solemnly declare this examination is completelymy own work, and I did not aid my answer to any question by dishonorable means.

NAME______________________________________________STUDENT No_________________

Open book.

Write answers on the question sheet. Use additional paper if necessary. Attempt all questions.

ELEC 2607 A MIDTERMCarleton University March 4, 2008

AUTHORIZED MEMORANDA TURN OFF cell phones and personal communications equipment and LEAVE THEM IN YOUR KNAPSACK. Notes, books, and non-communicating calculator are allowed.

BA

C

00

01

1110

00 01 11 10ABCD

map of ___

D

Writing Exams:


3

Writing Exams

Writing ExamsTiming yourself: 80 min, 100% 5 min for 10%.

1/2 hour for cleanup. Give Up: If you can’t get it move on.

RTFQ: Read The Foolish Question; read it again DAMN IT What was asked for?

Just the state table? Then don’t make K-maps.Did it want a circuit. Then draw it!

Look for simple methods: Don’t do all algebra questions by multiplying out.

AX+X

=X

X+X=1

X+A ·X = X+A

Exam Ready

(X+A+B)(X+A+C)(BC+A)=

NO NO NO!F does notequal its dual

F = (X+A+B)(X+A+C)(BC+A)Fdual = XAB+XAC+(B+C)A

= XAB+XAC+BA+CA = BA+CA

Take dualDist 1BA+anythng·BA = BA (use simp twice)

(Fdual)dual = F = (B+A)(C+A)

Writing Exams:


4

Writing Exams

Writing ExamsTime yourself: 5 min for 10%.

1/2 hour for cleanup. Give Up: Try an easier question.

RTFQ: Read it Again

Look for simple methods: Don’t do all algebra questions by multiplying out.

First look for simplifications.Are there three cm space for the answer? Do you need thirty? No! see simplification below.

Simplify at each step:Right elbow: X+anything·X = XLeft leg: X+anything·X = X + anythingNose: X+X=1

X+X=1

+BA

BC

+BA

B+B

CB

C+B

CA

BXB

C

AAA + ACBC + ACA+

+BXA

AX+X

=X

X+A·X = X+A

(X+A+B)(X+A+C)(BC+A)=XXABC+XXA+XABC+XAA+XCBC+XCA+AXBC+AXA+AABC+

F and Fdual

F = (X+A+B)(X+A+C)(BC+A)Fdual = XAB+XAC+(B+C)A

= XAB+XAC+BA+CA = BA+CA

Take dualDist 1BA+anythng·BA = BA (use simp twice)

(Fdual)dual = F = (B+A)(C+A)

Common Mistakes:


5

Common Mistakes

Common Mistakes1. Saying

2. Saying an expression is equal to its dual.

3. Not using AB + A =A to simplify expressions before using complex rules.Not reducing using A + AE = A + E. Simplifying and reducing first saves algebra.

4. Saying Everybody knows better than this, but they still do it.

5. When you take dual, or general Demorgan, do not put in the brackets in your head.

6. Not knowing D2. X + AB=(X + A)(X +B)

7. A Karnaugh map may not give the simplest circuit, but it does give the simplest Σ of Π circuit. Unless you mess up the loops

a•b is the same as a•b

X + 1 = X

(AB + C) + DE ==> (A+BC)(D +E)(AB + C) + DE ==> ((AB) + C) + (DE) ==> ((A+B)C)(D +E)

Boolean Algebra:


6

Boolean Algebra

Boolean Algebra1. Simplify (1 + A)

2. Simplify CD +CE

3. Take the dual of F=(A + B)(X + Y) + Z

4. Factor X + BC

5. Factor X + ABC

AB + CD

6. Find the dual of G=(A + 1)(B + C) + D

7. Factor

8. Construct simplest circuit with MUXs

AC + AD + DCBA

A A

Boolean Algebra:


7

Boolean Algebra

Boolean Algebra1. Simplify (1 + A)

2. Simplify CD +CE

3. Take the dual of F=(A + B)(X + Y) + Z

4. Factor X + BC

5. Factor X + ABC

AB + CD

6. Find the dual of G=(A + 1)(B + C) + D

1 rule 1+Z=1

C + D + CE =C+D+E rule C+CE=C+Erule DeMorg

Fdual={(AB)+(XY)}Z F={(A + B)(X + Y)} + Z bracket ANDs

(X + B)(X + C) rule D2

(X +AB)(X + C) rule D2rule D2=(X + A)(X +B)(X + C)

7. Factor(AB + C)(AB + D)

=(A + C)(B + C)(A + D)(B + D)

{(A + 1)(B + C)} + D

Gdual={(A0)+(BC)}D

bracket ANDs

dual 1↔0

=BCD

rule D2

rule D2

rules A0=0; x+0=x

AC + AD + DCBA

A AD + DCBC + DCB

=D=C

8. Construct with MUXs

Boolean Algebra:


8

Boolean Algebra

K-Maps; Common Errors

b

c

d

11

1

1a 1111 b

c

d

11

1

1a 111

1

Map of F Map of G

• Check Your Map Entries One variable in the wrong square, you’re toast!

• Don’t Treat Multiple Output Problems Like Unrelated Circuits

b

c

d

11

1

1a 1111 b

c

d

11

1

1a 111

1

Map of F Map of G

12 gates, none shared 9 gates, 3 shared

dd

• Check for Wrap Around,b

c

d

1

1

1a 1 1

1d

1

b

c

d

1

1

1a 1 1

1d

1

b

c

d

11

1

1a

d

1d

1

1

Poor

A bit of factoring might lower gate count.

SHARE GATES

Good

b

c11

1

1a

d

1d

1

1

Find biggest loops

Poor and Wider Wrap Around

You find two better loops

• Using algebra after map simplification.Usually not a help:

A K-map gives the simplest Σ of Π circuit.

three gates ab + ac = a(b + c) two gates

Boolean Algebra:


9

Boolean Algebra

K-Maps; Common Errors

• Multiple Output Mapping Rules∗ Do Half-Maps First

b

c11

1

1a 1d1dd

1d

1 b

c

d

11

1

1a 1d1dd

1d

1 (Except for PLAs)

• Do not confuse 5-variable maps and dual-output maps.5-variable use the largest circles,

Try to enlarge circle by using both maps.Multiple output

Sharing is very important to save gatesOften (esp exams) some smaller circles will give fewer gates.

sharing lowers gate count. smaller circles increase letter count.

∗ No friend rule

Balance these

Last two rules are heuristics

They do not replace all thinking.

∗ All friends gone to dark side rule

They help, but but not always,

Multiple Outputs Detai ls:


10

Multiple Outputs Detai ls

Multiple Outputs DetailsExample.1-33 Find the equations with minimum logicMinimization with sharing(1) Half Maps

Look for half-map circles (one letter terms)These do not require an AND gate.and can be circled without

fWX

loss of potential gate sharing.

1 1 1 11

1 1b

XW

Z

Y

d d dd

dd

(2) Circle squares that are “1” on only one mapNo Friends (Lone “1”)Rule

1 1 111

1

11

1 1

11 1

Map A

XW

Z

Y

XW

Z

Y

d d dd

dd

d d dd

dd

thus cannot be shared.

(2a) Find squares that cannot be usefully shared because that square on other maps is already circled.

No Friends, They Went To The Dark Side, Rule

1 1 111

1

11

1 1

1 1

d g

XW

Z

Y

XW

Z

Y

d d dd

dd

d d dd

dd

1

half-map

quarter-map

Map B

Lone 1

No friendLone 1

Circle them

friend died



11


1

1

dd

b

d

c

d

1

cd00 01 11 10

1

d dd

1

a

ab0011

11

0110

1

1

dd b

d

c

d

cd00 01 11 10

1

d1 dd

a

ab0011

1

10110

1

1

dd

b

d

c

d

1

cd00 01 11 10

1

d1dd

a

ab0011

0110

11

1

1 1

dd

b

d

c

d

cd00 01 11 10

d dd

a

ab0011

10110

1

Map of Z

Map of W Map of X

Map of Y

a·b·c·d ⇒ best circled by ad (family)

No Best Friends Rule Lonesome “1” rule)(2) Loop squares that appear on only one map

There is no way to share them. Loop them with as many brothers, or ds, as possible.

No best friendsJustbrothersCircle him with his

brothers

No friend here

No friend here

No friend here



12


(2a) With no best friends left, we cannot usefully share loops.

1

1

dd b

d

c

d

1

cd00 01 11 10

1

d dd

1

a

ab0011

11

0110

1

1

dd

b

d

c

d

cd00 01 11 10

1

d1 dd

a

ab0011

1

10110

1

1

dd

b

d

c

d

1

cd00 01 11 10

1

d1dd

a

ab0011

0110

11

1

1 1

dd b

d

c

d

cd00 01 11 10

d dd

a

ab0011

10110

1

Map of Z

Map of WMap of X

Map of Y

My Best Friends Are Gone Rule. (They went over to the dark side)

His best friendis gone.

Loop these new friendless “1”s with family.

Friend went to the dark side

Best friend’sgone

Best friend’sgone

Loop him

Loop him with family

a·b·c·d had one best friend



13


1

1 1F

XW

Z

Y

d

1

1G

XW

Z

Y

d 11

1 1 1

1H

XW

Z

Y

d

Examp.1-33Find the minimum Σ of Π

(1) Circle half maps (none)

(2) No Friends, (“1”s on only one map)

Loop Friendless “1”s , they will never share

1

1 1F

XW

Z

Y

d

1

1G

XW

Z

Y

d 11

1 1 1

1H

XW

Z

Y

d

Largest circles7 AND terms

1

1 1F

XW

Z

Y

d

1

1G

XW

Z

Y

d 11

1 1 1

1H

XW

Z

Y

dMinimum number of AND terms

Poor Method

Better Method

1

1 1F

XW

Z

Y

d

1

1G

XW

Z

Y

d 11

1 1 1

1H

XW

Z

Y

d

Unfortunately you have choices;several ways to loop some squares

Choices

Choices

Find the minimum Σ of Π (Cont):


14

Find the minimum Σ of Π (Cont)

1

1 1F

XW

Z

Y

d

1

1G

XW

Z

Y

d 11

1 1

1H

XW

Z

Y

dJohn’s Solution6 AND terms

Candice’s Solution5 AND terms

Find the minimum Σ of Π(Cont)

1

1 1F

XW

Z

Y

d

1

1G

XW

Z

Y

d 11

1 1 1

1H

XW

Z

Y

d

1 11Tom’s Solution

5 AND terms

Choice (1)

1F

XW

Z

Y

1

1G

XW

Z

Y

d 11

1 1 1

H

XW

Z

Y

1

1

1 1F

XW

Z

Y

d

1

1G

XW

Z

Y

d 11

1 1 1

1H

XW

Z

Y

dChoices

Choices

Chosen circles are shaded

Choice (2)

Choice (3)

Shows unnecessary

redundancy

111

d d1 1

Problems from Dec ‘96.:


15

Problems from Dec ‘96.

Problems from Dec ‘96.Sketch the Output Waveforms

1DC1C

X L

L

X

C

D Flip-Flop

Transparent when?Latched when?

1DC1

X Q

Q

X

C

C

D Latch (inverted clock)

______ edge triggered

A

B

C

Z

B

AA ZB

Equilivalent to

1

1

G1

BD

C

L

L

B

C D Latch Transparent when ___ Latched when____

______ gate



16


Latches etc from Dec ‘96.Example.1-34 Sketch the Output Waveforms

1DC1C

X L

L

X

C

D Flip-Flop

Transparent when C lowLatched when C high

1DC1

X Q

Q

X

C

C


Rising edge triggered

A

B

C

Z

B

AA ZB

XNOR gate

1

1

G1

BD

C

L

L

B

C D Latch Transparent when C=1 Latched when C=0

T T T

T T T

A B 0

1

01

0+1 0+0

0+0 1+1



17


Latches etc from Dec ‘96.Latches etc from Dec ‘96.Example.1-35 Sketch the Output Waveforms

1DC1C

X L

L

X

C

D Flip-Flop

Transparent when clock lowLatched when high

1DC1

X Q

Q

X

C

C


Rising edge triggered

A

B

C

Z

B

AA ZB

XNOR gate

1

1

G1

BD

C

L

L

B

C D Latch Transparent when C=1 Latched whenC=0

T T

T T T

T

A B 0

1

01

0+1 0+0

0+0 1+1



18


Latches etc. from Dec ‘96.Example.1-36 Sketch the Output Waveforms

Set output =1 when RS=10

Reset(L) - set(L) Latch

L

S

RR

SL

x=0

x=1

x=010

x=1

z=0 z=1Z

X

CLK

FSynchronous State Graph

x=0/z=1

x=d

x=1BG

X

CLKSynchronous State Graph

State AShow state as well as Z

x=0

x=1/z=0z=1

A

Set output to 0 when R=0

Store output when SR=11

State=Z

E

State BState A

Z



19


Latches etc. from Dec ‘96.Example.1-37 Sketch the Output Waveforms

Set output =1 when RS=10Reset(L)-set(L) Latch

L

S(L)

R(L)R

SL

x=0

x=1

x=010

x=1

z=0 z=1Z

X

CLK

FSynchronous State Graph

Z=Xx=d

x=1BG

X

CLKSynchronous State Graph

State AShow state as well as Z

x=0

Z=1A

Set output to 0 when R=0Store output when SR=11

State=Z

E

State BState A

Z

Set dominant

Sketch the circuit.

State only changeson the clock edge

State AState B State B1X X

1 1 11

State 0 State 1State 1State 0

0 0 0

Summary So Far:


20

Summary So Far

Summary So Far• Read the question! All of it!• Always check for Ax + A = A Use this to simplify anywhere.• Always reduce A + Ax = A + x Use anywhere except for hazards• Too many people say

• Put state tables in K-map order

• To tell Moore from Mealy in word problems1. Moore Outputs

Outputs will appear after the next active clock edge.2. Mealy Outputs

Outputs will appear after the input changes• Flip flops

Sample D input just before the clock..Transfer this to the output just after the clock.Q never changes except at clock edges

• T-flip flopsToggle Q after every clock edge if - enabled (provided it has an enable)

x + 1 = x0 000 010 110 101 001 011 111 10

CLK

MooreMealy

Input causingoutput

1DC1R

D Q

CLK

D

CLKEnC1R

Q

CLK

T flip flop

Summary So Far:


21

Summary So Far

Must Do With Finite-State Machinesa. Rearrange the state table into Karnaugh map order.

b. Change states only at an active clock edge.Often done when on timing diagrams.

c. Remember that FSMs are multiple output machines.Watch for shared gates when you loop maps.

1DC1

X QC

X

C

Q

NoNo

Q2

1Q1

Q0

1

Q2

1Q1

Q0

1

1Q2

1Q1

Q0

1

Q2

Q1

Q0

1

1

Q2

1Q1

Q0

11

1

111 1

1

Next-State Logic Output Logic

1

1

11

D2 D1 D0 Y Z

MUX LOGIC:


22

MUX LOGIC

MUX LOGICF= acd + bce + ade + abd + cde

bce + a·e ac +bce + ab + ced d

e ee e

c c c c c c

b bb b

0

0 1 a

Recallx + xa = xx + xb = x + b

a

c

d

e e

b

bc a ac + bc + ab + c

a + ab

ab + c

b 1 ab

a

a + b

ac + ab

ab

These MUXs both need abUse the same input MUX

F= ac0 + bce + a1e + ab0 + c0e F= ac1 + bce + a0e + ab1 + c1e

bc1 + a·0 ac +bc0 + ab + c0

MUX LOGIC:


23

MUX LOGIC

GOOD LUCK

MUX LOGIC:


24

MUX LOGIC

MUX LOGIC:


25

MUX LOGIC

MUX LOGIC:


26

MUX LOGIC

MUX LOGIC:


27

MUX LOGIC

MUX LOGIC:


28

MUX LOGIC

MUX LOGIC:


29

MUX LOGIC

MUX LOGIC:


30

MUX LOGIC

MUX LOGIC:


31

MUX LOGIC

exam review - doe.carleton.cajknight/97.267/2607_09w/wb/... · in the spirit of the code of honor...

Documents