FPGA/ CPLD LABEXPERIMENT 5AIM : To design a 4:1 multiplexer at different levels of modelling.EDA TOOL USED : Xilinx ISE 8.1iMETHODOLOGY : A digital multiplexer is a combinational circuit that selects one digital information from several sources and transmits the selected information on a single output line. A mux is also called a data selector since it selects one of many inputs. If the number of n input lines is equal to 2m then m select lines are required to select one of the input lines, for example, if there are 4 inputs, then 2 select lines are required.Select linesOutput(Y)

S1S0

00I0

01I1

10I2

11I3

Truth Table :

Expression : Y = I0 + S0 I1 + S1I2 + S1 S0 I3Block Diagam :

Fig 5.1 Block diagram of 4 : 1 MUXVERILOG CODE : Gate level Modellingmodule muxb(I0, I1, I2, I3, S0, S1, Y);input I0,I1,I2,I3,S0,S1; output Y; wire t0,t1,r0,r1,r2,r3;not(t0,S0); not(t1,S1); and(r0,I0,t0,t1); and(r1,I1,S0,t1);and(r2,I2,t0,S1); and(r3,I3,S0,S1); or(Y,r0,r1,r2,r3);endmoduleData flow level ModellingUsing Continuous statements:module muxd1(I0, I1, I2, I3, S0, S1, Y);input I0,I1,I2,I3,S0,S1; output Y;assign {Y}=(I0&(~S1)&(~S0))|(I1&(~S1)&(S0))|(I2&(S1)&(~S0))|(I3&(S1)&(S0));endmoduleUsing conditional statement:module muxd2(I0, I1, I2, I3, S0, S1, Y);input I0,I1,I2, I3,S0,S1; output Y; assign {Y}=S0?(S1?I3:I1):(S1?I2:I0);endmoduleBehavioural level Modellingmodule muxb(I,S,Y);input [3:0]I; input [1:0]S; output reg Y; always@(I,S)begincase(S)0: begin Y=I[0]; end 1: begin Y=I[1]; end 2: begin Y=I[2]; end 3: begin Y=I[3]; endendcase end endmoduleRTL SCHEMATIC VIEW : Gate level Modelling

Fig 5.2 RTL schematic of 4 : 1 MUXData flow level Modelling

(a)

(b)Fig 5.3 (a) & (b) RTL schematic of 4 : 1 MUX

Behavioural level Modelling

(a)

(b)Fig 5.4 (a) & (b) RTL schematic of 4 : 1 MUX

OUTPUT WAVEFORM :

Fig 5.5 Output waveform of 4 : 1 MUX

RESULT : Successfully implemented 4 : 1 MUX using different levels of modelling and verified its operation through simulation. 29