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EXPERIMENT 18

AIM : To design and simulate given problem using Verilog HDL.

EDA TOOL USED : Xilinx ISE 8.1i

METHODOLOGY : Find the sequence in the given flow diagram and simulate the sequence

detector using that sequence.

Fig 16.1 State Diagram of Sequence Detector

Sequence detection is the act of recognizing a predefined series of inputs. A sequence detector can be

of two types: one is overlapping and other is non-overlapping. In overlapping the part of sequences

detected in the previous sequence can be used for future sequence detection but in non-overlapping

cannot be used. The state diagram represents a sequence detector for serial input x given by the

sequence of 1s and 0s 101001. The output of the non-overlapping sequence detector designed is a

single bit z which goes to 1 when the entire sequence is detected. Else it remains 0.

State Table:

Clk

Present State Next State Output

Q X=0 X = 1 Z=0 Z=1

000 000 001 0 0

001 010 001 0 0

010 000 011 0 0

011 100 001 0 0

100 101 001 0 0

101 000 000 0 1

Table 16.1- State table of Sequence Detector

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VERILOG CODE :

module seq3(x, clk, Q, z);

input x,clk;

output reg Q,z;

initial begin Q

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RTL SCHEMATIC VIEW :

Fig 16.2 RTL schematic view of Sequence Detector

OUTPUT WAVEFORM :

Fig 16.3 Output of Sequence Detector

RESULT : Sequence Detector for sequence '101001' is successfully implemented in Verilog HDL

with its operations verified by the simulation.