expirment #2(diode series&parallel config)

الرحيم الرحمن الله بسم

Al-Quds University

Faculty of Engineering

“Electronics Engineering Department”

Electronics Lab

“Experiment #1”“Diode Characteristics”

Supervisor: “Rajaa Nawahdah”Demonstrator: “Mahmoud dababseh.”

Prepared by: “Rafat Hanna Al-Hawash” [20913425]

“Tareq Hanna Al-Atrash” [20910083]

24-10-2011

Table of Contents:

2.1 Introduction……………………………………..…… 1 2.1.1 Objectives……………………………………….. 1 2.1.2 Equipments List…………………………………. 1

2.2 Theoretical Background………………………….………. 12.3 Experimental Results & Discussion……………………… 22.4 Conclusion………………………………………………8

Figures Table:

Figure No. Page No.

2.1 12.2 22.3 22.4 32.5 32.6 42.7 42.8 52.9 5

2.10 62.11 62.12 62.13 72.14 8

Tables Table:

Table No. Page No.

2.1 72.2 7

2.1 Introduction: 2.1.1 Objectives:

a) Study the analysis of circuits with diodes, applying DC input.b) Analyze diode networks; series & parallel configuration.

2.1.2 Equipment List:a) Si & Ge diodes.b) Resistors.c) Digital Multi Meter (DMM) as volt-meter.d) Power Supply.

2.2 Theoretical Background:

The analysis of circuits with diode and DC input requires that the state of the diode first be determined.

In general a diode is in the “on” state if the direction of the current established by the

applied sources matches that of the arrow in the diode symbol, noticing that:

VD>=0.7 V for the silicon.

VD>=0.3V for germanium.

The state of the diode is first determined by mentally replacing the diode with a resistive

element:

Firstly: ON state (diode forward biased)

Fig 2.1

The resulting voltage and current levels are the following:

V D=V K

V R=E−V K

ID=IR=V R

R

Voltage drop applied across the diode, and its value is equal to VK as shown in the equation.

1

Secondly: OFF state (diode reverse biased)

Fig 2.2

The resulting voltage and current levels are the following:

V R=IR R=ID R=( 0 A )R=0V

Open circuit assumed across diode, so ID is (0 A).

In the parallel configuration, the diode about small voltage (VK) is on and the other (high

voltage) is off, and Vo in parallel network equaled to the voltage of the diode on.

2.3 Experimental Results & Discussion:

2.3.1Part1: Threshold voltages VT

VT = .546 V VT = .233V

2.3.2Part2: Series Configurationa)

R (meas.) = 2.17 KΩ

Fig 2.3b) V D=V T=.546 c) V D (measured )=.6V V o=E−V D V o=5−.546V o (calc . )=4.454V

V o (measured )=4.39V ID (calc . )=V o

R

Error (V o)=|Theo .−exp .|

Theo .∗100 %

Error (V o)=|4.454−4.39|

4.454∗100%

Error (V o)=1.44 %

ID (¿measured )=V o (meas .)R(meas .)

ID (calc . )=4.4542200

ID (¿measured )= 4.392170

ID (calc . )=2.024mA ID (¿measured )=2.023mA

2d)

R1 (meas.) = 2.17 KΩ

Fig 2.4 R2 (meas.) =976 Ω

e) V D=V T=.546 f) V D (measured )=.58V V o=RI D V o=1000∗1.34∗10−3

V o (calc . )=1.39V V o (measured )=1.37V

ID (calc . )=E+V TR1+R2

ID (¿measured )=V o (meas . )

R2

ID (calc . )=5+ .5463200

ID (¿measured )=1.37976


In the two previous circuits the diode is forward biased, so a voltage drop applied across it in the circuit solving, in each calculated and measured, there is some source of error, because of less of accuracy in measuring components values. =======================================================================g)

R1 (meas.) = 2.17 KΩ

Fig 2.5 R2 (meas.) =976 Ω


Theo .∗100 %

Error (V o)=|1.39−1.37|

1.39∗100 %

Error (V o)=1.46%

V D=V T=.546 h) V D (measured )=−5.02V V o (calc . )=0V (o.c.) V o (measured )=0V ID (calc . )=0 A (o.c.) ID (measured )=0 A

In the previous circuit the diode is reversed, and that cause it to be reverse biased, so it becomes an open circuit. -E - VD = 0 VD = -EThe circuit current is zero because of the open circuit across the diode.=======================================================================

3i)

R (meas.) = 2.17 KΩ

Fig 2.6

j) V 1 (calc . )=.546+ .233=.779V k) V 1 (measured )=.876V V o=E−V 1 V o=5−.779V o (calc . )=4.221V

V o (measured )=4 .12V ID (calc . )=V o

R

ID (¿measured )=V o (meas .)R(meas .)

ID (calc . )=4.2212200



2.3.3Part3: Parallel Configurationa)

Error (ID)=|Theo .−exp .|

Theo .∗100%

Error (ID)=|1.92−1.89|

1.92∗100 %

Error (ID)=1.56%

R (meas.) = 2.17 KΩ

Fig 2.7b) V o (calc . )=.233V c) V o (measured )=.287V V R=E−V o V R=5−.233 V R (calc . )=4.77V V R (measured )=4.77V

In this parallel diode configuration circuit, the output voltage is equal to the smaller threshold voltage VT of the two diodes; that because the current flows through the branch with smaller voltage drop, so the current will not flow in the Silicon diode (o.c.), and the output voltage will be equal to VT of the Ge diode.=======================================================================

4d)

R1 (meas.) = 2.17 KΩ

Fig 2.8 R2 (meas.) =976 Ω

e) V o=V T f)V o (calc . )=.546V V o (measured )=.58V V R1=E−V o V R1=5−.546 V R1 (calc . )=4.454 V V R1 (measured )=4.41V


Theo .∗100 %

Error (V o)=|.233−.287|

.233∗100 %

Error (V o)=23.18 %


Theo .∗100 %

Error (V o)=|.546−.58|

.546∗100 %

Error (V o)=6.22%

ID (calc . )=V R1

R1

ID (¿measured )=V R1 (meas . )

R1 (meas . )

ID (calc . )=4.4542200



In this circuit, the output voltage is equal to VT of the diode, since no current flows in R2, because the voltage drop across R2 is greater than voltage drop across the diode.=======================================================================g)

R1 (meas.) = 2.17 KΩ

Fig 2.9 R2 (meas.) =976 Ω

h) V o=V T i)V o (calc . )=.546V V o (measured )=.58V V R1=E−V o V R1=5−.546 V R1 (calc . )=4.454 V V R1 (measured )=4.41V

ID (calc . )=V R1

R1

ID (¿measured )=V R1 (meas . )

R1 (meas . )

ID (calc . )=4.4542200



52.3.4Part4: Positive logic AND Gate


Theo .∗100 %

Error (V o)=|.546−.58|

.546∗100 %

Error (V o)=6.22%

a)

R1 (meas.) = 2.17 KΩ

Fig 2.10

b) V o=V T c) V o (calc . )=.546V V o (measured )=.59V

d) Applying voltage for each terminal of the gate:

Fig 2.11

V o (calc . )=0V e) V o (measured )=0V

f)

R1 (meas.) = 2.17 KΩ

Fig 2.12

V o=V T g) V o (calc . )=.546V V o (measured )=.566V


Theo .∗100 %

Error (V o)=|.546−.59|

.546∗100 %

Error (V o)=6.23%


Theo .∗100 %

Error (V o)=|.546−.566|

.546∗100 %

Error (V o)=3.66%

6In Positive Logic AND Gate, we found Voltage out in all cases, show in the table:

5(v) ≡ 1

0(v) ≡ 0

Table 2.1

In the positive logic AND Gate can the diode became the FB if the voltage on the anode is

equal and the voltage on the cathode is equal but the voltage in the cathode is largest. In the

OR Gate can the diode any one nut equality became FB if the diode voltage on the anode

smallest then cathode.

Table 2.2

2.3.5Part4: Bridge Configurationa)

R1 (meas.) = .75 KΩ

Fig 2.13 R2 (meas.) =2.17 KΩ

R3 (meas.) =2.17 KΩ b) V o=V T 2−V T 1 i)V o (calc . )=0V V o (measured )=0V V R3=E−V T 2 V R3=5−.546 V R3 ( calc . )=4.454 V V R3 (measured )=4.39V

Error (V R 3)=|Theo .−exp .|

Theo .∗100 %

Error (V R 3)=|4.454−4.39|

4.454∗100 %

Error (V R 3)=1.43%

AND A B

0 0 0

0 0 1

0 1 0

1 1 1

OR A B

0 0 0

1 0 1

1 1 0

1 1 1

72.3.6Part4: Practical Exercisea)

R1 (meas.) = .75 KΩ

Fig 2.14 R2 (meas.) =2.17 KΩ

R3 (meas.) =2.17 KΩ

V o=(E−V T 1)∗R1

R3+R1

V o=(5−.546 )∗1000

1000+2200 b)

V o (calc . )=1.392V V o (measured )=1.37V

V R3=(E−V T 1 )∗R3

R3+R1

V R3=(5−.546 )∗2200

1000+2200

V R3 ( calc . )=3.062V V R3 (measured )=2.99V

2.4 Conclusion:

* In the series configuration (Forward Bias), diode effect the circuit with voltage drop, and its value is VT.

VR = E - VT

*when using several diodes connected on series in the same direction, voltage drop is the summation of VT for each diode.

*In parallel configuration, when diode is on, no current flow in the network connected with it on parallel.

*when two diodes connected on parallel (both forward biased), the diode with less firing potential (VT) is on, and the other is off. Otherwise the forward biased diode is on.

*when configuring two parallel diodes, they could form logic gates such as AND & OR Gates.


Theo .∗100 %

Error (V o)=|1.392−1.37|

1.392∗100 %

Error (V o)=1.58 %

expirment #2(diode series&parallel config)

Documents