External Memory InterfaceHandbook Volume 2: DesignGuidelinesEMI_DG2017.05.08

Last updated for Intel Quartus Prime Design Suite: 17.0

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Contents

1 Planning Pin and FPGA Resources....................................................................................91.1 Interface Pins.........................................................................................................9

1.1.1 Estimating Pin Requirements...................................................................... 121.1.2 DDR, DDR2, DDR3, and DDR4 SDRAM Clock Signals.....................................131.1.3 DDR, DDR2, DDR3, and DDR4 SDRAM Command and Address Signals............ 131.1.4 DDR, DDR2, DDR3, and DDR4 SDRAM Data, Data Strobes, DM/DBI, and

Optional ECC Signals................................................................................ 141.1.5 DDR, DDR2, DDR3, and DDR4 SDRAM DIMM Options....................................151.1.6 QDR II, QDR II+, and QDR II+ Xtreme SRAM Clock Signals...........................181.1.7 QDR II, QDR II+ and QDR II+ Xtreme SRAM Command Signals..................... 191.1.8 QDR II, QDR II+ and QDR II+ Xtreme SRAM Address Signals........................ 191.1.9 QDR II, QDR II+ and QDR II+ Xtreme SRAM Data, BWS, and QVLD Signals.....201.1.10 QDR IV SRAM Clock Signals......................................................................201.1.11 QDR IV SRAM Commands and Addresses, AP, and AINV Signals.....................211.1.12 QDR IV SRAM Data, DINV, and QVLD Signals.............................................. 221.1.13 RLDRAM II and RLDRAM 3 Clock Signals....................................................231.1.14 RLDRAM II and RLDRAM 3 Commands and Addresses................................. 241.1.15 RLDRAM II and RLDRAM 3 Data, DM and QVLD Signals............................... 241.1.16 LPDDR2 and LPDDR3 Clock Signal............................................................ 251.1.17 LPDDR2 and LPDDR3 Command and Address Signal....................................261.1.18 LPDDR2 and LPDDR3 Data, Data Strobe, and DM Signals.............................261.1.19 Maximum Number of Interfaces................................................................ 261.1.20 OCT Support ..........................................................................................37

1.2 Guidelines for Intel Arria 10 External Memory Interface IP........................................381.2.1 General Pin-Out Guidelines for Arria 10 EMIF IP............................................ 381.2.2 Resource Sharing Guidelines for Arria 10 EMIF IP.......................................... 43

1.3 Guidelines for Intel Stratix 10 External Memory Interface IP..................................... 451.3.1 General Pin-Out Guidelines for Stratix 10 EMIF IP..........................................451.3.2 Resource Sharing Guidelines for Stratix 10 EMIF IP........................................50

1.4 Guidelines for UniPHY-based External Memory Interface IP......................................... 511.4.1 General Pin-out Guidelines for UniPHY-based External Memory Interface IP.......511.4.2 Pin-out Rule Exceptions for 36 Emulated QDR II and QDR II+ SRAM

Interfaces in Arria II, Stratix III and Stratix IV Devices................................. 541.4.3 Pin-out Rule Exceptions for RLDRAM II and RLDRAM 3 Interfaces.................... 591.4.4 Pin-out Rule Exceptions for QDR II and QDR II+ SRAM Burst-length-of-two

Interfaces............................................................................................... 611.4.5 Pin Connection Guidelines Tables.................................................................621.4.6 PLLs and Clock Networks........................................................................... 72

1.5 Using PLL Guidelines............................................................................................. 761.6 PLL Cascading...................................................................................................... 771.7 DLL.....................................................................................................................781.8 Other FPGA Resources...........................................................................................791.9 Document Revision History.....................................................................................80

2 DDR2, DDR3, and DDR4 SDRAM Board Design Guidelines.............................................. 832.1 Leveling and Dynamic Termination.......................................................................... 84

2.1.1 Read and Write Leveling............................................................................ 842.1.2 Dynamic ODT........................................................................................... 86

Contents

External Memory Interface Handbook Volume 2: Design Guidelines2

2.1.3 Dynamic On-Chip Termination.................................................................... 862.1.4 Dynamic On-Chip Termination in Stratix III and Stratix IV Devices...................872.1.5 Dynamic OCT in Stratix V Devices............................................................... 892.1.6 Dynamic On-Chip Termination (OCT) in Arria 10 and Stratix 10 Devices........... 89

2.2 DDR2 Terminations and Guidelines.......................................................................... 892.2.1 Termination for DDR2 SDRAM..................................................................... 892.2.2 DDR2 Design Layout Guidelines.................................................................. 952.2.3 General Layout Guidelines..........................................................................962.2.4 Layout Guidelines for DDR2 SDRAM Interface............................................... 96

2.3 DDR3 Terminations in Arria V, Cyclone V, Stratix III, Stratix IV, and Stratix V............... 992.3.1 Terminations for Single-Rank DDR3 SDRAM Unbuffered DIMM....................... 1002.3.2 Terminations for Multi-Rank DDR3 SDRAM Unbuffered DIMM......................... 1012.3.3 Terminations for DDR3 SDRAM Registered DIMM......................................... 1022.3.4 Terminations for DDR3 SDRAM Load-Reduced DIMM................................... 1022.3.5 Terminations for DDR3 SDRAM Components With Leveling........................... 103

2.4 DDR3 and DDR4 on Arria 10 and Stratix 10 Devices.................................................1032.4.1 Dynamic On-Chip Termination (OCT) in Arria 10 and Stratix 10 Devices..........1042.4.2 Dynamic On-Die Termination (ODT) in DDR4...............................................1042.4.3 Choosing Terminations on Arria 10 Devices.................................................1042.4.4 On-Chip Termination Recommendations for DDR3 and DDR4 on Arria 10

Devices.................................................................................................1052.5 Layout Approach.................................................................................................1052.6 Channel Signal Integrity Measurement...................................................................106

2.6.1 Importance of Accurate Channel Signal Integrity Information........................ 1062.6.2 Understanding Channel Signal Integrity Measurement..................................1062.6.3 How to Enter Calculated Channel Signal Integrity Values.............................. 1072.6.4 Guidelines for Calculating DDR3 Channel Signal Integrity..............................1082.6.5 Guidelines for Calculating DDR4 Channel Signal Integrity..............................110

2.7 Design Layout Guidelines..................................................................................... 1132.7.1 General Layout Guidelines........................................................................ 1142.7.2 Layout Guidelines for DDR3 and DDR4 SDRAM Interfaces............................. 1152.7.3 Length Matching Rules............................................................................. 1182.7.4 Spacing Guidelines.................................................................................. 1192.7.5 Layout Guidelines for DDR3 and DDR4 SDRAM Wide Interface (>72 bits)........120

2.8 Package Deskew................................................................................................. 1232.8.1 Package Deskew Recommendation for Stratix V Devices............................... 1232.8.2 DQ/DQS/DM Deskew............................................................................... 1242.8.3 Address and Command Deskew.................................................................1242.8.4 Package Deskew Recommendations for Arria 10 and Stratix 10 Devices..........1242.8.5 Deskew Example.....................................................................................1252.8.6 Package Migration................................................................................... 1262.8.7 Package Deskew for RLDRAM II and RLDRAM 3........................................... 127

2.9 Document Revision History...................................................................................127

3 Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines......................................1303.1 General Layout Guidelines.................................................................................... 1303.2 Dual-Slot Unbuffered DDR2 SD