eyeq3™ data sheet - best inc. · pdf fileconfidential information of mobileye, and may...
TRANSCRIPT
18-Nov-159-Nov-15 Proprietary
Rev. 7.27.1 confidential Page 1 of 90 and Confidential
EyeQ3™ Data Sheet
EyeQ3™ Data SheetEyeQ3™ Data Sheet
11/18/201511/9/2015 2
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Important Notice This material describing Mobileye is for general information purposes and may be
modified by Mobileye without notice. This material is the proprietary and/or
confidential information of Mobileye, and may not be disclosed or transferred to any
third party without Mobileye’s prior express consent. Mobileye, its logo and service
names are trademarks of Mobileye.
Mobileye makes no warranty for the use of its products, assumes no responsibility for
any errors that may appear in this document, and makes no commitment to update
the information contained herein. There are no express or implied licenses granted
hereunder to design or fabricate any integrated circuits based on information in this
document.
EyeQ3® is a trademark of Mobileye, N.V. and may be used to identify Mobileye
products only. All other marks are the property of their respective holders.
© Copyright 2006-2015 Mobileye. All rights reserved
Document name:
EyeQ3_DataSheet.doc
Revision History:
Rev Date Author Description
Approved by Date
0.0 14/Jul/10 Mois Preliminary Draft Elchanan 14/Jul/10
1.0 29/Mar/11 Mois First Draft Elchanan 29/Mar/11
2.0 30/May/11 Mois Preliminary Internal Release Elchanan 30/May/11
2.1 14/June/11 Elchanan Update EyeQ3 block diagram, DDR signals name and DDR3, LPDDR2 connections
Elchanan 14/June/11
3.0 26/Sep/11 Mois Preliminary Customer Release Elchanan 26/Sep/11
3.1 27/Sep/11 Mois add SFI timing Elchanan 27/Sep/11
3.2 2/Oct/11 Mois update package info Elchanan 2/Oct/11
3.3 5/Oct/11 Mois Temp Sensor acc. / pull-up to sfi_d2-3 / REXT Elchanan 5/Oct/11
3.4 25/Oct/11 Mois ddr_retention note Updated Ball Outs
Elchanan 25/Oct/11
3.5 30/Oct/11 Mois Remove EyeQ3Lite Usage Col form pinouts Elchanan 30/Oct/11
3.6 3/Nov/11 Mois Spia/b ck/cs are bidirectional; osc is 100ppm Elchanan 3/Nov/11
3.7 14/Nov/11 Mois -remove nmi, tdbgint (nc0,nc1) -spi timing
Elchanan 14/Nov/11
3.8 24/Nov/11 Mois modify spi timing modify i2c timing add pdt and vid out load values remove tdbgack (nc2)
Elchanan 24/Nov/11
3.9 13/Dec/11 Mois modify spi timing add rgmii timing modify video out features
Elchanan 13/Dec/11
EyeQ3™ Data SheetEyeQ3™ Data Sheet
11/18/201511/9/2015 3
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Rev Date Author Description
Approved by Date
4.0 4/Jan/2012 Mois update ac timing mips description update pinouts, balls update pwr/gnd pins various changes throughout
Elchanan 4/Jan/2012
4.1 4/Mar/2012 Mois video channel diagram; pinout diagram; i2c specs; reset deassertion note; various edtis throughout
Elchanan 4/Mar/2012
4.2 28/Mar/2012 Mois clock, reseti, por_vdd notes, mode bits on por_vdd only, pull-up pull-down notes
Elchanan 28/Mar/2012
4.3 5/Apr/2012 Mois 3V3 power note Elchanan 5/Apr/2012
4.4 15/May/2012 Mois Add PowerMode description; RGMII, CKE pulldown recommendations; pck, mclk maxrates, add XTAL specifications
Elchanan 15/May/2012
4.5 6/Jun/2012 Mois Add I2C pad info Elchanan 6/Jun/2012
4.6 17/Jun/2012 Mois Add Max Freq notes; change Ethernet naming; modify RGMII timing
Elchanan 17/Jun/2012
4.7 26/Jun/2012 Mois Modify OSC CL; Update EyeQ3 block diagram; D$=32K w/ECC; Thermal Data
Elchanan 28/Jun/2012
4.8 27/Aug/2012 Mois Add explanation of DC Characteristics Tables; Fix Pinout diagram; IO Default states; Max
SerFin rates; AGND notes; IO Power
Elchanan 27/Aug/2012
4.9 13-Nov-12 Mois Remove defunct comment about vic_d15,vib1_d15 being used for ring voltage select
Add note about IO in tristate when no core voltage present.
Add note about reseti_n debounce and effect Add info on power and thermal characteristics
Elchanan 13-Nov-12
5.0 23-Dec-12 Mois -Add note about SFI pins at POR_VDD=0 -Add 6L package data - remove AGND - update mechanical drawings
Elchanan 23-Dec-12
5.1 7-Feb -13 Mois - update pinout diagram - fix testen polarity - In ball out diagrams: label NC pins, change
XINT naming to not use parenthesis - revert back to AGND - GNDE_DDR_1V8_1V5_1V2 now GND - Increased max current draws of VDD (Core) VDDEDDR-LPDDR2
Elchanan 7-Feb -13
5.2 12-Feb-13 Mois - fix ball outs to show nc0-2 - changes to table 18 Steady State current
Power - add note about power up/down seq. - pin list diagram - add NC section - modify Power and GND references
throughout - XINT uses PD - I2C uses 1V8 and 3V3
Elchanan 12-Feb -13
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Audience and Scope
11/18/201511/9/2015 4
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Rev Date Author Description
Approved by Date
5.3 25-Feb-13 Mois - FUSE HV can float - note 1ms rise on Power for CUT1 only - note RGMII inputs have internal PD in CUT2 - note that $D in CUT1 is 64K w/o ECC
Elchanan 25-Feb-13
5.4 28-Feb-13 Mois - remove max 1ms power rise time constraint Elchanan 28-Feb-13
5.5 6-Mar-13 Mois - remove 3.3V power sequence from DDR3 sequence
-add note that the mechanical values are preliminary
Elchanan 6-Mar-13
5.6 14-Mar-2013 Mois - add temp info - mark VREG as “0” balls - update package info
Elchanan 14-Mar-2013
5.7 29-Apr-2013 Mois - 2V5 usage explanation - add note that DDR timing at die - add note that DDR timing is referenced to Vref crossing - remove DDR3 derating - remove clock jitter value - remove support of clock input - modify RGMII Tx to use skew only - change 3.3V range
Elchanan 29-Apr-2013
5.8 8-Oct -2013 Mois Change spia reset state to z Add note about PCB solder mask Clarify mode sampling 9.1 Modify Image Sensor connections diagram and add note about sensor placement Add pins to Power Ring Descr. MCLK reset to “1”
Elchanan 8-Oct -2013
5.9 21-Nov-2013 Mois -Modify DDR pin lists -Update Application diagram of the external clock to use pull-down. -Modify 2V5 usage explanation -Change sfi_d(2:3) from reserved mode bits to pcb version indicators. - Change XINT(0:1) to allow use as pcb version indicators. - DDR lane#0 constraint
Elchanan 21-Nov-2013
6.0 14-Jan-2014 Mois - add note about analog clk_in/out - remove DDR3 support
Elchanan 14-Jan-2014
6.1 25-Feb-2014 Mois - update mechanical package info - add DDR pins not documented: DQS(3:0) - update ball outs and pin diagram to reflect removal of DDR3 pins (we, reset,odt) - add three NC pins to ball outs
Elchanan 25-Feb-2014
6.2 26-Feb-2014 Mois Mechanical chart update Elchanan 26-Feb-2014
6.3 4-Mar-2014 Mois Remove 19x19x2.52 mechanical notation; add sec. “Reset”
Elchanan 24-Mar-2014
6.4 11-May-2014 Mois Modify reset notes Add note about SPI_DO Power sequence. DDR, IO (VDDE v VPAD). TMS note
Elchanan 11-May-2014
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Audience and Scope
11/18/201511/9/2015 5
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Rev Date Author Description
Approved by Date
6.5 29-Jun-2014 Mois ST comments integrated
Add supported DDR devices
Reseti_n notes.
BGA Ball Material
Elchanan 29-Jun-2014
6.6 7-Aug-14 Mois Add CTE info;
Add Storage Temp Min.
Elchanan 7-Aug-14
6.7 19-Oct-14 Mois
Dvir, Roei
- Update JTAG descriptions; remove unecc. SFI timing
- Update LPDDR2 533MHz timing
- Add DDR Routing Considerations to Maintain Good Signal Integrity
Dvir 19-Oct-14
6.8 11-Feb-15 Mois - modify LPDDR timing
- remove clock in details
Roei/Elchanan 11-Feb-15
6.9 1-Apr-15 Mois Remove references to clk in.
Add OSC power on sequence diagram
Elchanan 1-Apr-15
7.0 1-Sep-15 Mois Add clock stretching to I2C;
PowerUp Timing Diagram
DDR timing to 500MHz (from 533MHz)
Elchanan 1-Sep-2015
7.1 7-Sep-15 Mois Modify DDR VIH/VIL Meir 1-Nov-15
7.2 17-Nov-15 Mois Insert mechanical data without watermark
Fix Pin Diagram (pwrmode8)
Elchanan 17-Nov-15
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Audience and Scope
11/18/201511/9/2015 6
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Table of Contents
1. Audience and Scope ............................................................................................... 11
2. Acronyms and Abbreviations.................................................................................. 12
3. EyeQ3® Overview .................................................................................................... 13
4. EyeQ3® Architecture ............................................................................................... 14
4.1 MIPS1004K CPU Sub-System .......................................................................................................... 15
4.1.1 MIPS Cores Configuration ............................................................................................. 15 4.1.2 Coherence Manager Configuration .......................................................................... 16
4.2 Vector Microcode Processor (VMP) ........................................................................................... 16
4.3 Arteris Interconnect Block ............................................................................................................. 17
4.4 Video Input Interfaces ................................................................................................................... 17
4.5 Video Output Interface ................................................................................................................. 18
4.6 1Gb Ethernet / AVB ........................................................................................................................ 19
4.7 On-chip memory ............................................................................................................................ 19
4.8 Off-chip memory ............................................................................................................................ 19
4.9 Peripherals ........................................................................................................................................ 20
5. EyeQ3® Development Tools kit ............................................................................... 21
5.1 EyeQ3® Software Development Kit (SDK) Tools ....................................................................... 21
5.2 EyeQ3® Development platform .................................................................................................. 21
5.3 EyeQ3® Debug Configurations ................................................................................................... 24
6. Pin List ........................................................................................................................ 25
6.1 DDR-SDRAM connectivity ............................................................................................................. 31
6.2 Serial Flash Interface (SFI) .............................................................................................................. 32
6.3 Video Input Interface .................................................................................................................... 33
6.4 Video Output (and alternate Video Input) Interface ............................................................. 34
6.5 PDTrace Interface .......................................................................................................................... 35
6.6 1Gb Ethernet / AVB Interface ...................................................................................................... 35
6.7 I2C (a/b) Interfaces ........................................................................................................................ 36
6.8 UART (a/b) Interfaces (with alt. GPIO connectivity) ................................................................ 37
6.9 CAN (a/b) Interfaces (with alt. GPIO connectivity) ................................................................ 37
6.10 SPI (a/b) Interfaces (with alt. GPIO connectivity) .................................................................... 38
6.11 General Purpose Input Output (GPIO) and Timer I/O ............................................................. 39
6.12 Clocks, Reset, Controls Interface ................................................................................................ 41
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Audience and Scope
11/18/201511/9/2015 7
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
6.13 JTAG Interface ................................................................................................................................ 45
6.14 Power Interface .............................................................................................................................. 45
6.15 No Connects ................................................................................................................................... 46
7. Electrical Specifications ........................................................................................... 48
7.1 Absolute Maximum Ratings .......................................................................................................... 48
7.2 Power Supply Specifications ........................................................................................................ 48
7.2.1 Power Up/Down Sequence ......................................................................................... 49 7.2.2 IO Power Sequence ....................................................................................................... 50
7.3 DC I/O Characteristics................................................................................................................... 51
7.3.1 Special cases .................................................................................................................. 51
7.4 DDR SDRAM DC Characteristics .................................................................................................. 52
7.5 AC Characteristics ......................................................................................................................... 52
7.5.1 Clock AC .......................................................................................................................... 53 7.5.1 SPI Timing .......................................................................................................................... 53 7.5.2 Serial Flash Interface (SFI) Timing ................................................................................. 55 7.5.3 Serial i2c pin timing......................................................................................................... 57 7.5.4 RGMII Interface timing ................................................................................................... 58 7.5.5 Video Input Interface timing ........................................................................................ 59 7.5.6 Video Output Interface ................................................................................................. 61 7.5.7 PDtrace Interface timing .............................................................................................. 62 7.5.8 reseti-n pin timing ........................................................................................................... 62 7.5.9 DDR SDRAM AC Characteristics .................................................................................. 63
7.6 DDR SDRAM Timing Specification ................................................................................................ 63
7.6.1 LPDDR2 Address/Command/Control timing specification .................................... 64 7.6.2 LPDDR2 write timing specification ............................................................................... 65 7.6.3 LPDDR2 read timing specification ............................................................................... 67
8. Reset .......................................................................................................................... 68
9. Boundary Scan (JTAG1149.1) Functions ................................................................. 70
9.1 Boundary Scan Interface .............................................................................................................. 70
9.2 State Machine ................................................................................................................................. 70
9.3 EyeQ3 TAP Controllers.................................................................................................................... 70
9.4 MIPS JTAG Instruction Register ..................................................................................................... 70
9.5 System JTAG Instruction Register ................................................................................................. 71
9.6 Boundary Scan Register (BSR) ...................................................................................................... 71
9.6.1 Express and Normal BSRs ............................................................................................... 71
9.7 EyeQ3® Device ID Register........................................................................................................... 72
10. Power-On Configurations......................................................................................... 73
10.1 sfi_d0 .................................................................................................................................................. 73
10.2 sfi_d1 = mode1 ................................................................................................................................ 73
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Audience and Scope
11/18/201511/9/2015 8
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
10.3 sfi_d(2-3) = board version .............................................................................................................. 73
10.4 GPIO(8:2) = PowerMode (8:2) ...................................................................................................... 73
10.5 por_vdd – Power On Reset ........................................................................................................... 74
10.6 ntrst_n –JTAG Reset ........................................................................................................................ 74
10.7 clk_in and clk_out ........................................................................................................................... 74
11. External Connection Examples ............................................................................... 76
11.1 DDR-SDRAM ..................................................................................................................................... 76
11.1.1 DDR supported................................................................................................................ 76
11.2 Flash memory .................................................................................................................................. 77
11.2.1 Serial flashes supported ................................................................................................. 77
11.3 Image sensor connection ............................................................................................................. 78
12. Chip Package Data ................................................................................................. 80
12.1 Mechanical Data ........................................................................................................................... 80
12.2 Package Thermal Data ............................................................................................................. 8783
12.2.1 Operational Thermal Data ....................................................................................... 8783 12.2.2 Package Related Temperature Data .................................................................... 8783
12.3 Package Solder Mask ................................................................................................................ 8884
13. Special Considerations and Checklist ................................................................ 8985
13.1 Power considerations ................................................................................................................ 8985
13.2 PCB considerations .................................................................................................................... 8985
13.2.1 DDR Routing Considerations for Good Signal Integrity ....................................... 8985
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Audience and Scope
11/18/201511/9/2015 9
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
List of Figures Figure 1: EyeQ3® Block Diagram ........................................................................................................... 14
Figure 2: Video Channels ......................................................................................................................... 18
Figure 3: SIM3 in Online Mode................................................................................................................. 22
Figure 4: SIM3 in Offline Mode ................................................................................................................ 23
Figure 5: PDTrace Mictor Connections .................................................................................................. 24
Figure 6: EyeQ3® Pinout Diagram .......................................................................................................... 26
Figure 7: EyeQ3® balls top-view North-West ........................................................................................ 27
Figure 8: EyeQ3® balls top-view North-East ......................................................................................... 28
Figure 9: EyeQ3® balls top-view South-West........................................................................................ 29
Figure 10: EyeQ3® balls top-view South-East ....................................................................................... 30
Figure 11: I2C timing waveform .............................................................................................................. 57
Figure 12: RGMII TX timing ........................................................................................................................ 59
Figure 13: RGMII RX timing ....................................................................................................................... 59
Figure 14: Video Input Interface inputs timing ..................................................................................... 60
Figure 15: Video Output Interface outputs timing .............................................................................. 61
Figure 16: PDTrace Timing Diagram ....................................................................................................... 62
Figure 17: System Set-Up and Hold Uncertainties and Margin ......................................................... 63
Figure 18: LPDDR2 Command/Address/Control Timing Diagram .................................................... 64
Figure 19: LPDDR2 Write Timing Diagram .............................................................................................. 66
Figure 20: LPDDR2 Read Timing Diagram ............................................................................................. 67
Figure 21: Application diagram of the crystal oscillator .................................................................... 74
Figure 23: Two 32-bit data width LPDDR2 devices interface ............................................................ 76
Figure 24: Single 32-bit data width LPDDR2 device interface .......................................................... 77
List of Tables Table 1: LPDDR2-SDRAM ball description ............................................................................................. 31
Table 2: Vision Serial Flash ball description ........................................................................................... 32
Table 3: Video Interface ball description ............................................................................................. 33
Table 4: Video Output Interface balls description .............................................................................. 34
Table 5: PDTrace Interface ball description ......................................................................................... 35
Table 6: Ethernet Interface ball description ......................................................................................... 35
Table 7: I2C balls description .................................................................................................................. 36
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Audience and Scope
11/18/201511/9/2015 10
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Table 8: UART balls description ............................................................................................................... 37
Table 9: CAN balls description ................................................................................................................ 38
Table 10: SPI balls description ................................................................................................................. 38
Table 11: GPIO / Timer balls description ............................................................................................... 39
Table 12: Clocks, Resets, Interrupts, Analog pins description ........................................................... 42
Table 13: Jtag0 for boundary balls scan ............................................................................................... 45
Table 14: Power pin description ............................................................................................................. 45
Table 15: NC pin description ................................................................................................................... 47
Table 16: Absolute maximum ratings .................................................................................................... 48
Table 17: Voltage variation ..................................................................................................................... 49
Table 18: Steady state current Power ................................................................................................... 49
Table 19: 1.8V DC IO Characterization* ............................................................................................... 51
Table 20: 3.3V DC IO Characterization* ............................................................................................... 51
Table 21: LPDDR2 Interface DC Electrical Characteristics ................................................................ 52
Table 22: Crystal Input .............................................................................................................................. 53
Table 23: Serial Port Interface timing(2)
.................................................................................................. 54
Table 24: Serial Flash SDR & DDR Timing (3.3V@15pF/30pF load) .................................................... 57
Table 25: I2C Interface Timing(Fast Mode Plus – 1Mbs) ..................................................................... 57
Table 26: RGMII TX Timing ......................................................................................................................... 59
Table 27: RGMII RX Timing ........................................................................................................................ 59
Table 28: Video Input Interface timing .................................................................................................. 61
Table 29: Video Output Interface timing .............................................................................................. 61
Table 30: PDtrace timing (3.3V) .............................................................................................................. 62
Table 31: LPDDR2 Interface AC Electrical Characteristics ................................................................ 63
Table 32: LPDDR2 Command/Address/Control Timing Specifications ........................................... 65
Table 33: LPDDR2 Write Timing Specifications...................................................................................... 66
Table 34: LPDDR2 Read Timing Specifications ..................................................................................... 67
Table 35: Supported JTAG Instructions of EyeQ3® ............................................................................. 71
Table 36: Package Thermal Data ...................................................................................................... 8783
Table 37: Package Temperature ratings .......................................................................................... 8783
Table 38: Recommended Skew Budgets ......................................................................................... 9086
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Audience and Scope
11/18/201511/9/2015 11
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
1. Audience and Scope This data sheet provides the technical details of the EyeQ3® system. This will help
technical personnel understand the various EyeQ3® system components, including
their features, characteristics, and connectivity options.
Section 22 contains a glossary of the mnemonics used in this document; section 3
provides an overview of the system.
Section 44 describes EyeQ3® system architecture as a whole. A brief description is
provided together with the main features of the various EyeQ3® system peripherals,
including MIPS1004K CPU, Vector Microcode Processor (VMP), memories and
video interfaces.
Section 55 lists the EyeQ3® software and hardware development tools.
Section 66 describes the pinouts of the EyeQ3® system peripherals which includes a
depiction of the overall EyeQ3® pinout).
Section 77 provides the AC and DC electrical specifications and characteristics as
well as interface timing details and diagrams for system components.
Section 88 describes the JTAG configuration. Section 1010 provides power-on
configurations, including diagrams of the crystal oscillator hook up.
External connection examples are provided in Section 1111, including for SDRAM
and Flash memory as well as various configurations of vision sensor systems.
Physical details of EyeQ3® package are provided in Section 1212, including thermal
data details.
Section 1313 includes special considerations for balls, power, and the PCB.
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Acronyms and Abbreviations
11/18/201511/9/2015 12
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
2. Acronyms and Abbreviations Mnemonic Description
AHB AMBA High Performance Bus
AXI Advanced eXtensible Interface
BALL Package’s pin
CAN Controller Area Network
CIS CMOS Image Sensor
CPU Central Processing Unit
DMA Dynamic Memory Access
DDRAM Double Data Rate Dynamic Random Access Memory
DSP Digital Signal Processor
EEPROM Electrically Erasable Programmable Read-Only Memory
EPM EyeQ3® Processing Module
ESD Electrostatic Discharge
ETM Embedded Trace Module
FIFO First In First Out
GND Ground
GPIO General Purpose Input Output
HSBGA Heat Slug Ball Grid Array
ICE In Circuit Emulator
JTAG IEEE standard boundary scan protocol
LVDS Low Voltage Differential Signalling
OCP Open Core Protocol (bus)
PCB Printed Circuit Board
PLL Phase Locked Loop
POR Power On Reset
RGMII Reduced Gigabit Media Independent Interface
RISC Reduced Instruction Set Computer
ROM Read Only Memory
SIM Serial Interface Module
SoC System On Chip
SRAM Static Random Access Memory
TCM Tightly Coupled Memory
UART Universal Asynchronous Receiver Transmitter
USB Universal Serial Bus
EyeQ3™ Data SheetEyeQ3™ Data Sheet
EyeQ3® Overview
11/18/201511/9/2015 13
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
3. EyeQ3® Overview The Mobileye EyeQ3® System-on-Chip (SoC) is the third-generation Vision-System-
on-Chip produced by Mobileye. Following the success of its two predecessors -
EyeQ® & EyeQ2® - the EyeQ3® SoC offers a solution for computationally
intensive, real-time visual recognition and scene interpretation applications that can
be customized for use in intelligent vehicle systems. The chip architecture is designed
to maximize cost performance by executing a full-fledged application on a single
ultra-low-cost chip. An example of such an application is low-cost Adaptive Cruise
Control using a single video input source. The EyeQ3® system detects vehicles,
motorcycles, pedestrians, and road markings to provide an intelligent driver-
assistance system.
The EyeQ3® is completely programmable to accommodate a wide range of vision
processing applications beyond the automotive field.
To maximize total system cost performance, all peripheral circuits are integrated into
the EyeQ3®, including dual CAN, UARTs, I2C, SPI interfaces. Dual Data Rate 64bit
LPDDR2 controller, 32bit parallel GPIO, timers, high resolution Video interface and
1Gb 1GB Ethernet interface unit.
The EyeQ3® is manufactured using the STMicroelectronics 40 nanometer-low power
technology and is designed to comply with cabin-grade automotive standard AEC-
Q100.
EyeQ3® main features:
On Chip Processors:
Four floating point, hyper-thread, cache-coherent 32bit RISC 1004KfMIPS CPU
Four custom Vector Microcode Processors (VMPs)
800Mb/sec LPDDR2 SDRAM Controller
Serial Flash Interface (SFI) Serial Multi-SPI DDR/SDR FLASH/SRAM Controller
Arteris Interconnect
Three 16/12/8-bit 2Mpixel Video and Image preprocessing input ports
16-bit 2Mpixel Video output.
Two CAN ports (1Mbps)
Two UART ports (5Mbps)
Two I2C Interfaces (1Mbs)
Two SPI interfaces (31.25M (Master) / 15.62 (Slave) )
32-bit General Purpose I/O (GPIO)
Eight Timers (max output frequency 62.5MHz)
1Gb Ethernet / Audio Video Bridge (AVB)
Power management
EyeQ3™ Data SheetEyeQ3™ Data Sheet
EyeQ3® Architecture
11/18/201511/9/2015 14
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
4. EyeQ3® Architecture The EyeQ3® architecture consists of one quad floating point, hyper-thread 64bit
RISC 1004KMIPS CPU, four custom Vector Microcode Processors (VMPs), and
several other peripherals. The on chip power management can turn off and on several
processors by SW in order to budget the device power dissipation and operation
temperatures.
Figure 1: EyeQ3® Block Diagram
OCP
EyeQ3
block diagram D
FI 2
.1
4b
Da
tab
ah
n
/ 1
28b
LPDDR2 Controller
Interconnect &
Quality of Service
OCP
OCP
16b
2x
SPI
2x
I2C
2x
CAN
8X
Timer
APB 32b
16b
MIPS-1004K with
Cache-coherency
Ca
ch
e-c
oh
ere
ncy
OCP
IOC
U
OCP
1Gbs Ethernet /
Audio Video Bridge
2x
UART
32x
GPIO
8b
OCP
OCP VMP3
34Kf32/32K
D/I$
16KB ECC iSRAM
AXI
OCP
34Kf32/32K
D/I$
34Kf32/32K
D/I$
34Kf32/32K
D/I$
50
0M
hz
Scheduler
64/32b
DDR SDRAM LPDDR
400/533MHz
OCP
OCP
32b CRCOCP
OCP
DMAs & CTR
3xPar
Video_in
1xPar
Video_out
AXI
SlaveMaster2x Temp
Sensor
3x
PLLs
16b
16b
AHB 32b
500Mhz
VMP3
VMP3
VMP3
2.5V 3x
DC2DC
AHB 32b
16b
PDTrace
DM
As
DM
As
DM
As
DM
As
Serial Flash
Quad DDR/SDR
I/F
RGMII
sFlash
LPDDR2 PHY
EyeQ3™ Data SheetEyeQ3™ Data Sheet
EyeQ3® Architecture
11/18/201511/9/2015 15
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
The EyeQ3® architecture employs an Arteris interconnect block to route the multiple
master ports to the various slave ports, and enables concurrent operation over 128bit
busses. The interconnect block offers the high connectivity scheme needed to support
the demanding data bandwidth required for vision processing. Slave port bus
contention is resolved by the interconnect block which decides on the winning master
according to its priority scheme.
All the VMPs work in parallel, using their own DMA controller to transfer data
between their local memories and off-chip or on-chip memories.
A high-speed, 64-bit width, 16Kbyte, on-chip ECC SRAM is connected to the
interconnect block for fast memory storage.
A separate 32-bit low-bandwidth Peripheral Bus (APB) is provided to connect all of
the various peripherals (e.g., CAN, UART, I2C, etc.).
4.1 MIPS1004K CPU Sub-System
EyeQ3® employs the MIPS1004Kf 500MHz cache coherent processor system which
contains four 1004Kf (34Kf with cache coherency support) CPUs. Three out of four
CPUs can be powered off/on by SW.
4.1.1 MIPS Cores Configuration
* One Virtual Processor Engine (VPE)
* Two Task Contexts (TCs)
* Memory Map Unit (MMU) Type: TLB
* 16 dual entries in JTLB
* 2:1 core clock to FPU clock
* Load/Store unit
Eight FSB entries
Nine Load-Queue entries
Inter-Thread Communications
* PRID company options field = 25
* ICache
32KB Cache
* DCache
CUT1: 64K DCache w/o ECC; CUT2: 32KB DCache w/ECC
Fixed aliasing in HW
* Parity Enabled
* Debug Config Options
* EJTAG HW Breakpoint Options
Four Instruction breakpoints
Two Data breakpoints
* MIPS Trace Options
EyeQ3™ Data SheetEyeQ3™ Data Sheet
EyeQ3® Architecture
11/18/201511/9/2015 16
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Trace Enabled
Off Chip Trace Memory
4 Triggers
Two-bit source field in trace word not enabled
* Probe Interface Block (PIB) options—16b Trace Data width for off chip memory
4.1.2 Coherence Manager Configuration
General:
Data Memory Port Interface: 64 bits
Exception Base Reset for each Core: 0xB000_0000
Interrupts:
Number of Interrupts: 48
No External Interrupt Controller
Interrupts: FdcInt, SWInd, PerfInt and TimerInt are router by GIC.
ITU:
16 FIFOs
ITU RS Entries: 9
4.2 Vector Microcode Processor (VMP)
Designed by Mobileye and customized to implement efficiently vision algorithms.
The four VMP modules are generic vector processing units without cache. Each
VMP connects to the Interconnect via its own OCP bus (Master port). Each Unit is
also connected to the Interconnect via its AHB bus (Slave port). Each VMP has the
following features:
Vector Microcode machine
VLIW
Each field is a SIMD
Each Instruction takes one clock
o Latency is 4 clocks
o Pipeline is handled by the compiler automatically.
o Operation at 500MHz
o The four VMPs can be powered off/on by sw
o Program and Data memories are local:
No cache
o Deterministic accesses
Instruction example (dx):
EyeQ3™ Data SheetEyeQ3™ Data Sheet
EyeQ3® Architecture
11/18/201511/9/2015 17
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
{R0=Read0; Next0; R1=R0;(R2, R0)=COMB(R1, R0);
R3=HSUB(R1, R2); Write1(R3); Next1; Cont(0) }
4.3 Arteris Interconnect Block
The Interconnect block (licensed from Arteris) offers the high connectivity scheme
needed to provide the required data bandwidth of the EyeQ3® vision processing. It is
referred to as the NoC (Network on a Chip).
The NoC is comprised of 10 clock domains to connect the various cores.
4.4 Video Input Interfaces
The video interface block supports the capture of three high dynamic-range (90-
120dB), color or monochrome image video streams, each with a maximum of 8k x 8k
image resolution (i.e., components). The video interface is always in slave mode (i.e.,
sync signals are received from image sensor). The EyeQ3® provides a glueless
interface to the image sensor, which it configures via an I2C or GPIO interface.
Typical image sensors include Aptina’s 12-bit MT9M025 devices and future 16-bit
image sensors.
The video interface, upon receiving the video stream, performs pixel pre-processing
and then stores the modified 8/16bit pixel images.
The video interface features include:
Three parallel video-in ports
Programmable capture frame size up to input size (max: 8k x 8k components)
Support for both progressive and interlaced scans (de-interlacing done in DMA).
Synchronization support using data bus according to ITU-R BT.656.
Five channels for the three video-in ports (see Figure 2: Video Channels below),
with separated Filter, and Histogram for each channel.
o Sub sampling for horizontal and vertical configurable separately (step size 0-
31)
o 16bit curve approximation. One curve for each channel (with bypass option)
o Histogram supports different weights for different areas of the frame; as well as
supporting windowing (horizontal and vertical offset and size) and sub-
sampling (step size 0-31 in either horizontal, vertical or both)
o Multiple pixel arrangements - bursts from FIFOs may reverse pixel order
o Header and footer from image sensor can be captured without going through
sub-sampling and correction process.
Max pclk frequency:
o 100MHz when Histogram is enabled.
o 200MHz when Histogram is disabled.
EyeQ3™ Data SheetEyeQ3™ Data Sheet
EyeQ3® Architecture
11/18/201511/9/2015 18
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Max mclk frequency – 250MHz/n where n>1.
The figure below shows the possible video channels that can be used by the three
video input interfaces. VIA can use channels 1 to 3, VIB can use channels 3 to 5 and
VIC can use channel 5. Accordingly, the video block must be initially configured by
software to connect either VIA or VIB to channel 3 and either VIB or VIC to channel
5.
Figure 2: Video Channels
Image
sensor
16bit
Image
sensor
16bit
Image
sensor
16bit
V
I
A
V
I
B
V
I
C
Channel 2
Channel 1
Channel 4
Channel 5
Channel 3
EyeQ 3 Video Interface
4.5 Video Output Interface
The video output interface supports the display of one high dynamic-range 16-bit
color or monochrome image video stream, with a maximum of 8k x 8k image
resolution (components). The video output interface supports Master Mode (i.e.,
driving syncs to image sensor).
The essential features of the output interface are:
Supports RGB (5-6-5, 16 bit), Y:Cb:Cr 4:2:2 (8bit/component; 8 or 16 bit/pclk)
Supports format change from RGB to Y:Cb:Cr 4:2:2
Output frame size – up to 8k x 8k
LUT for data generation
64bit Internal memory word width
o 16bit components stored consecutively
o 8bit components stored as 3 consecutive components per 32bit (padded).
Max pclk frequency – 250MHz/n where n>1.
EyeQ3™ Data SheetEyeQ3™ Data Sheet
EyeQ3® Architecture
11/18/201511/9/2015 19
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
4.6 1Gb Ethernet / AVB
The 1GB Ethernet interface enables a host to transmit and receive data over Ethernet
in compliance with the IEEE 802.3-2005 standard.
The AVB is compliant with the following standards:
IEEE 802.3-2005 for Ethernet MAC, Reduced Gigabit Media Independent
Interface (RGMII).
IEEE 1588-2008 standard for precision networked clock synchronization
IEEE 802.1-AS, version D6.0 and 802.1-Qav, version D6.0 for Audio Video (AV)
traffic.
AMBA 3.0 for AXI Master/Slave ports.
The 1GB Ethernet interface supports 10/100/1000 Mbps data transfer rates by RGMII
interface to communicate with an external PHY.
The RGMII frequencies are programmable to 2.5/25/125MHz to support data rates of
10/100/1000 Mbps, respectively. It should be noted that the JEDEC standard for Tx
skew is not supported (see timing section).
The 1GB Ethernet interface contains:
1024 Core Registers.
23 DMA Registers.
2 RX FIFO in size 4KB (each FIFO)
1 TX FIFO in size 4KB.
4.7 On-chip memory
EyeQ3® supports several on-chip memories equipped with parity check with the
following features:
16-KByte, 64-bit data width, 200MHz, single-cycle memory with ECC (Error
Code Correction) mechanism.
More than 640-KByte memory spread amongst the four VMPs with parity check.
More than 100-KByte memory for the four Video I/Fs with parity check.
More than 380-KByte cache memory for the MIPS 1004K system with parity
check.
4.8 Off-chip memory
EyeQ3® supports several off-chip memories with the following features:
64/32-bit width, external LPDDR2 Mobile Double Data Rate SDRAM.
Multi SPI (single, dual and quad) Serial Flash Interface (SFI developed by
Mobileye). The SFI supports SPI NOR and NAND Flash of all the main vendors
(e.g., Micron, Spansion, Winbond, Macronix).
EyeQ3™ Data SheetEyeQ3™ Data Sheet
EyeQ3® Architecture
11/18/201511/9/2015 20
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
4.9 Peripherals
The EyeQ3® supports numerous peripherals which are located on the Arteris
Interconnect Block-SL0:
Serial Interfaces:
o Two UART controller
o Two 1Mb CCAN (Bosch) controllers
o Two 1Mbs I2C Controllers that support clock stretching
o Two SPI Controllers - 31.25Mbs (Master) / 15.62Mbs (Slave)
o 125Mb Serial Quad DDR/SDR controller
32-bit GPIO
Eight timers, including one Watch-Dog timer
Three On-Chip PLLs
Power management
Two Temperature Sensors - Two on-chip temperature sensors are employed in the
EyeQ3 – one near the MIPS cores and the other near the VMP cores. Each sensor
is calibrated at room temperature (calibration is set during testing by fuses) and
provides junction temperature data within an accuracy of +/-6°C for temperatures
above 100°C.
EyeQ3™ Data SheetEyeQ3™ Data Sheet
EyeQ3® Development Tools kit
11/18/201511/9/2015 21
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
5. EyeQ3® Development Tools kit The sections below list the EyeQ3® software and hardware development tools.
5.1 EyeQ3® Software Development Kit (SDK) Tools
The EyeQ3® software-development tools allow the customer to develop a product
based on EyeQ3®. The software development tools include:
HW Development board –EPM3 (EyeQ3® Processing Module)
EyeQ3® HIL (HW In Loop)
MIPS1004K tools
o MIPS C++ compiler
o MIPS assembler
o MIPS linker
o MIPS source-level debugger
o MIPS profiling, translating simulator
VMP s/w development tools
o Assembler & linker
o Clock-accurate simulator
o Compilers for high-level languages (EyeC - a C dialect with extensions for
vector processing, plain C and Forth)
o A graphical debugger
o A build & test system (both for standalone testing and integration with
applications targeted at the external CPUs - the MIPS cores)
o Standard libraries
o Hyper-Threads aware custom RTOS and Peripherals drivers
o EQC (EyeQClient) application: Host Logging/Playback/Testing tool
o Vision algorithms libraries
o Quick Start examples
5.2 EyeQ3® Development platform
An EyeQ3® based Development Vision System includes the following modules:
EyeQ3® HW In Loop (EyeQ3® HIL)
Up to three CMOS Image Sensor camera modules (CIS)
FS2 core debug tools (PDtrace and JTAG)
An EyeQ3® Processing Module (EPM3) integrated into a SIM3 PCB system is
shown below (in both “online” and “offline” configurations):
EyeQ3™ Data SheetEyeQ3™ Data Sheet
EyeQ3® Development Tools kit
11/18/201511/9/2015 22
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Figure 3: SIM3 in Online Mode
EyeQ3™ Data SheetEyeQ3™ Data Sheet
EyeQ3® Development Tools kit
11/18/201511/9/2015 23
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Figure 4: SIM3 in Offline Mode
EyeQ3™ Data SheetEyeQ3™ Data Sheet
EyeQ3® Development Tools kit
11/18/201511/9/2015 24
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
5.3 EyeQ3® Debug Configurations
There are two ways to build a PCB to allow for various levels of debug capability:
(1) JTAG; (2) JTAG & PDTrace;
The following diagram illustrates the FS2/Lauterbach probe connector which
requires the PDTrace and JTAG signals. Also shown are the voltage level shifters
required.
Figure 5: PDTrace Mictor Connections
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Pin List
11/18/201511/9/2015 25
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
6. Pin List This section describes the pin connections of the various EyeQ3® system peripheral
devices. Included here are various diagrams as well as detailed pin description
sections divided according to functional groups.
It should be noted that the EyeQ3 features programmable power rings to allow
various IO groups to operate and different voltage levels. These power rings often
serve multiple functional groups. As such, it is important that the user be sure to
program and power all IOs of a specific power ring consistently. Please see section
10.410.4 “GPIO(8:2) = PowerMode (8:2)” for important configuration details.
The power rings are noted at the bottom of every section of pins related to that ring.
If an application has no need for any IOs of a certain power ring, it is recommended
to connect the Voltage input (e.g., for ring2: VDDE_R2_1V8_3V3) for that ring to
GND.
Figure 6: EyeQ3® Pinout Diagram
Figure 6: EyeQ3® Pinout Diagram
Figure 6 below shows the overall EyeQ3® pinout.
All tables in this section use the following abbreviations:
A Analog signal
B Bi-directional
H Activity High
I Input
L Activity Low
LH Programmable
O Output
X(m:n) m is MSB and n is LSB
Field Code Changed
Formatted: Body Text, Indent: Firstline: 1.23 cm, Tab stops: 0 cm, Left
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Pin List
11/18/201511/9/2015 26
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Figure 6: EyeQ3® Pinout Diagram
64 BIT
MDDR
SDRAM
DDR_A(14:0)
DDR_BA(2:0)
DDR_DQ(63:0)
DDR_DQS(7:0)
DDR_DQS_N(7:0)
DDR_DM(7:0)
DDR_RAS_N
DDR_CAS_N
DDR_CLK(1:0)
DDR_CLK_N(1:0)
DDR_CLKE(1:0)
DDR_CS_N(1:0)
DDR_RETENTION_N
DDR_VREF
DDR_ATO
DDR_DTO(1:0)
DDR_ZQ
GPIO
CANA_TX
CANA_RX
CANB_TX /GPIO22 (DEF:GPIO)
CANB_RX /GPIO23 (DEF:GPIO)
PDT(15:0)
PDCLK
PDT_TRIGIN
PDT_ TRIGOUT
PDT_PROBE_N
PDT_DM
NTRST_N
TDI
TMS
TCK
TDO
TESTEN
VIA_D(15:0)
VIA_PCLK
VIA_VSYNC
VIA_HSYNC
VIA_FIELD
VIA_MCLK
16 BIT
VIDEO
INPUT
CLK &
RESET
MIPS
&
PDTRACE
I/O
JTAG
CAN
UART /
GPIO
EYEQ3 FCTEBGA
POWER
GND
VDDE_VDDQ_ISLAND_1V8_1V5_1V2
VDD_1V2
VDDE_R(0:1)_1V8_1V5_1V2
VDDE_R(2:8)_1V8_3V3
VIB0_D(15:0)
VIB0_PCLK
VIB0_VSYNC
VIB0_HSYNC
VIB0_FIELD
VIB0_MCLK
UARTA_TX/GPIO18 (DEF:GPIO)
UARTA_RX/GPIO19 (DEF:GPIO)
UARTB_TX/GPIO20 (DEF:GPIO)
UARTB_RX/GPIO21 (DEF:GPIO)
I2CB_SDA
I2CB_CLK
VIC_D(15:0)
VIC_PCLK
VIC_VSYNC
VIC_HSYNC
VIC_FIELD
VIC_MCLK
VO_D(15:0) / VIB1__D(15:0)
VO_PCLK / VIB1__PCLK
VO_VSYNC / VIB1__VSYNC
VO_HSYNC / VIB1__HSYNC
VO_EN / VIB1__FIELD
NU / VIB1__MCLK
I2CA_SDA
I2CA_CLK
SFISFI_CK
SFI_CS(1:0)
SFI_D(3:0)
I2C
I2C
16 BIT
VIDEO
OUTPUT
1GB
ETHRNT
/ AVB
RGMII_TD[3:0]
RGMII_TX_CTL
RGMII_TX_CLK
RGMII_RD[3:0]
RGMII_RX_CTL
RGMII_RX_CLK
SMA_MDIO
SMA_MDC
CAN/
GPIO
SPIA_DO/GPIO24 (DEF:GPIO)
SPIA_DI/GPIO25 (DEF:GPIO)
SPIA_CK/GPIO26 (DEF:GPIO)
SPIA_CS/GPIO27 (DEF:GPIO)
SPIB_DO/GPIO28 (DEF:GPIO)
SPIB_DI/GPIO29 (DEF:GPIO)
SPIB_CK/GPIO30 (DEF:GPIO)
SPIB_CS/GPIO31 (DEF:GPIO)
GPIO0 /TIMER_CK0
GPIO1 /TIMER_CK1
GPIO2 /TIMER_CK2 / PWRMODE2
GPIO3 /TIMER_CK3 / PWRMODE3
GPIO4 /TIMER_EOC0 / PWRMODE4
GPIO5 /TIMER_EOC1 / PWRMODE5
GPIO6 /TIMER_EOC2 / PWRMODE6
GPIO7 /TIMER_EOC3 / PWRMODE7
GPIO8 /TIMER_EXT0_INCAP1 / PWRMODE8
GPIO9 /TIMER_EXT0_INCAP2
GPIO10 / TIMER_EXT0_OUTCMP1
GPIO11 / TIMER_EXT0_OUTCMP2
GPIO12 / TIMER_CK4
GPIO13 / TIMER_EOC4
GPIO14 / TIMER_EXT1_INCAP1
GPIO15 / TIMER_EXT1_INCAP2
GPIO16 / TIMER_EXT1_OUTCMP1
GPIO17 / TIMER_EXT1_OUTCMP2
POR_VDD
RESETI_N
RESETO_N
CLK_IN
CLK_OUT
XINT (3:0)
3V3VREG1_COREPWR/VREG1_COREGND
2V5VREG1_COREPWR
3V3VREG2_COREPWR/VREG2_COREGND
2V5VREG2_COREPWR
3V3VREG3_COREPWR/VREG3_COREGND
2V5VREG3_COREPWR
1V2PLLA_COREPWR/GND
1V2PLLB_COREPWR/GND
1V2PLLC_COREPWR/GND
1V2OSC_COREPWR/GND
1V8TEMPSENS0_COREPWR
1V8TEMPSENS0_COREGND
1V8TEMPSENS1_COREPWR
1V8TEMPSENS1_COREGND
FUSE_HV
16 BIT
VIDEO
INPUT
16 BIT
VIDEO
INPUT
UART /
GPIO
SPI /
GPIO
SPI /
GPIO
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Pin List
11/18/201511/9/2015 27
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Figure 7: EyeQ3® balls top-view North-West
1 2 3 4 5 6 7 8 9 10 11
A
VDDE_R0_
1V8_1V5_1
V2
GNDDDR_RAS_
NGND
DDR_CK_N
1DDR_CK1 GND DDR_CK0
DDR_CK_N
0GND DDR_DQS0
B GND DDR_A11 NC4
VDDE_R0_
1V8_1V5_1
V2
DDR_CAS_
N
DDR_CS_N
1
VDDE_R0_
1V8_1V5_1
V2
DDR_ATO DDR_ZQ
VDDE_R0_
1V8_1V5_1
V2
DDR_DM0
C GND DDR_A13 DDR_A12 DDR_BA2 DDR_A10 DDR_BA1 DDR_BA0 DDR_A9DDR_CS_N
0NC3 DDR_DQ4
DDDR_DQS_
N4
VDDE_R1_
1V8_1V5_1
V2
DDR_A14 NC5 DDR_CKE0 DDR_A6 DDR_A8 DDR_A5 DDR_A4 DDR_A1 DDR_DQ6
E DDR_DQS4 DDR_DM4 DDR_DQ32DDR_RETE
NTION_NDDR_CKE1 DDR_A7 DDR_A3 DDR_A2 DDR_A0 DDR_DTO0 DDR_DTO1
F GND DDR_DQ33 DDR_DQ35 DDR_DQ34
VDDE_VDD
Q_ISLAND_
1V8_1V5_1
V2
VDDE_VDD
Q_ISLAND_
1V8_1V5_1
V2
GND
VDDE_R0_
1V8_1V5_1
V2
VDD_1V2 VDD_1V2 VDD_1V2
GDDR_DQS_
N5
VDDE_R1_
1V8_1V5_1
V2
DDR_DQ36 DDR_DQ37 VREF VDD_1V2 VDD_1V2 VDD_1V2 VDD_1V2 VDD_1V2 VDD_1V2
H DDR_DQS5 DDR_DM5 DDR_DQ43 DDR_DQ39 DDR_DQ38 GND VDD_1V2 VDD_1V2 VDD_1V2 VDD_1V2 VDD_1V2
J GND DDR_DQ44 DDR_DQ41 DDR_DQ42 DDR_DQ40 VDD_1V2 VDD_1V2 VDD_1V2 GND GND GND
KDDR_DQS_
N6DDR_DM6 DDR_DQ45 DDR_DQ46 DDR_DQ47
VDDE_R1_
1V8_1V5_1
V2
VDD_1V2 VDD_1V2 GND GND GND
L DDR_DQS6
VDDE_R1_
1V8_1V5_1
V2
DDR_DQ51 DDR_DQ48 DDR_DQ50
VDDE_R1_
1V8_1V5_1
V2
VDD_1V2 VDD_1V2 GND GND GND
M GND DDR_DQ52 DDR_DQ53 DDR_DQ54 DDR_DQ49 GND VDD_1V2 VDD_1V2 GND GND GND
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Pin List
11/18/201511/9/2015 28
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Figure 8: EyeQ3® balls top-view North-East
12 13 14 15 16 17 18 19 20 21 22 23
DDR_DQS_
N0GND DDR_DQS1
DDR_DQS_
N1GND DDR_DQS2
DDR_DQS_
N2GND DDR_DQS3
DDR_DQS_
N3GND GND A
VDDE_R0_
1V8_1V5_1
V2
DDR_DQ1
VDDE_R0_
1V8_1V5_1
V2
DDR_DM1 DDR_DQ23 DDR_DM2
VDDE_R0_
1V8_1V5_1
V2
DDR_DQ30 DDR_DM3
VDDE_R0_
1V8_1V5_1
V2
GND VDD_1V2 B
DDR_DQ5 DDR_DQ0 DDR_DQ9 DDR_DQ8 DDR_DQ22 DDR_DQ18 DDR_DQ16 DDR_DQ26 DDR_DQ27 NC1 TMS VDD_1V2 C
DDR_DQ3 DDR_DQ2 DDR_DQ13 DDR_DQ10 DDR_DQ20 DDR_DQ19 DDR_DQ17 DDR_DQ28 DDR_DQ25 NC2 TCK TDO D
DDR_DQ7 DDR_DQ14 DDR_DQ15 DDR_DQ12 DDR_DQ11 DDR_DQ21 DDR_DQ31 DDR_DQ29 DDR_DQ24 TDI NTRST_N TESTEN E
GND VDD_1V2 VDD_1V2 VDD_1V2 VDD_1V2
VDDE_R0_
1V8_1V5_1
V2
GND FUSE_HV XINT1 XINT0 NC0 RESETO_N F
VDD_1V2 VDD_1V2 VDD_1V2 VDD_1V2 VDD_1V2 VDD_1V2VDDE_R7_
1V8_3V3GPIO10 GPIO8 GPIO11 POR_VDD RESETI_N G
VDD_1V2 VDD_1V2 VDD_1V2 VDD_1V2 VDD_1V2VDDE_R7_
1V8_3V3
VDDE_R7_
1V8_3V3GPIO2 GPIO9 GPIO7 GPIO1 GPIO14 H
GND GND GND GND VDD_1V2 VDD_1V2VDDE_R7_
1V8_3V3GPIO3 GPIO4 GPIO5 GPIO6 GPIO13 J
GND GND GND GND VDD_1V2
1V8TEMPSE
NS1_COREP
WR
1V8TEMPSE
NS1_CORE
GND
GPIO0 GPIO12 SPIB_CK SPIB_DO SPIB_CS K
GND GND GND GND VDD_1V2VDDE_R8_
1V8_3V3
VDDE_R8_
1V8_3V3GPIO15 GPIO16 SPIB_DI I2CA_SCL I2CA_SDA L
GND GND GND GND VDD_1V2 VDD_1V2VDDE_R3_
1V8_3V3
VDDE_R3_
1V8_3V3GPIO17 XINT2 XINT3 GND M
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Pin List
11/18/201511/9/2015 29
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Figure 9: EyeQ3® balls top-view South-West
NDDR_DQS_
N7DDR_DQ56 DDR_DQ57 DDR_DQ58 DDR_DQ55 VDD_1V2 VDD_1V2
1V8TEMPSE
NS0_CORE
GND
GND GND GND
P DDR_DQS7 DDR_DM7 DDR_DQ60 DDR_DQ59 DDR_DQ63 VDD_1V2 VDD_1V2
1V8TEMPSE
NS0_COREP
WR
GND GND GND
R GND
VDDE_R1_
1V8_1V5_1
V2
DDR_DQ61 DDR_DQ62 VDD_1V2 VDD_1V2 VDD_1V2 VDD_1V2 GND GND GND
T GNDVDDE_R5_
1V8_3V3PDT_D2 PDT_D1 PDT_D0
VDDE_R5_
1V8_3V3
VDDE_R5_
1V8_3V3VDD_1V2 VDD_1V2 VDD_1V2 VDD_1V2
UVDDE_R5_
1V8_3V3PDT_D5 PDT_D4 PDT_D3 I2CB_SDA
RGMII_RD
1
RGMII_TX_
CTL
VDDE_R5_
1V8_3V3VDD_1V2 VDD_1V2 VDD_1V2
V PDT_D6 PDT_D7 PDT_D8 PDT_D9 I2CB_SCLRGMII_RD
2
RGMII_RD
0
VDDE_R5_
1V8_3V3
VDDE_R5_
1V8_3V3
VDDE_R5_
1V8_3V3
VDDE_R2_
1V8_3V3
W PDT_D10 PDT_D11 PDT_CLKPDT_TRIGO
UTRGMII_TD0
RGMII_TX_
CLK
RGMII_RD
3SMA_MDIO VIB1_PCLK VIB1_FIELD SFI_CS1
Y PDT_D12 PDT_D13 PDT_DMPDT_TRIGI
NRGMII_TD1
RGMII_RX_
CLK
RGMII_RX_
CTLSMA_MDC VIB1_MCLK
VIB1_HSYN
CSFI_CS0
AA PDT_D14 PDT_D15PDT_PROB
E_NRGMII_TD2 RGMII_TD3 VIB1_D4 VIB1_D9 VIB1_D13
VIB1_VSYN
CSFI_D1 SFI_D3
ABVDDE_R5_
1V8_3V3GND VIB1_D0 VIB1_D1 VIB1_D2 VIB1_D7 VIB1_D11 VIB1_D12 VIB1_D14 SFI_D0 SFI_D2
AC GNDVDDE_R5_
1V8_3V3REXT_R5 VIB1_D3 VIB1_D5 VIB1_D6 VIB1_D8 VIB1_D10 VIB1_D15 REXT_R2 GND
1 2 3 4 5 6 7 8 9 10 11
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Pin List
11/18/201511/9/2015 30
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Figure 10: EyeQ3® balls top-view South-East
GND GND GND GND VDD_1V21V2OSC_CO
REPWR
1V2OSC_CO
REGND
1V2PLLB_C
OREPWRVIA_FIELD VIA_HSYNC VIA_VSYNC GND N
GND GND GND GND VDD_1V21V2PLLA_C
OREPWR
1V2PLLA_C
OREGND
1V2PLLB_C
OREGNDVIA_D7 VIA_PCLK VIA_D15 VIA_D14 P
GND GND GND GND1V2PLLC_C
OREPWR
VREG1_CO
REGND
2V5VREG1_
COREPWR
3V3VREG1_
COREPWRVIA_D11 VIA_MCLK VIA_D12 VIA_D13 R
VDD_1V2 VDD_1V2 VDD_1V2 VDD_1V21V2PLLC_C
OREGND
VREG2_CO
REGND
2V5VREG2_
COREPWR
3V3VREG2_
COREPWRVIA_D10 VIA_D8 VIA_D6 VIA_D9 T
VDD_1V2 VDD_1V2 VDD_1V2 VDD_1V2 VDD_1V2VREG3_CO
REGND
2V5VREG3_
COREPWR
3V3VREG3_
COREPWRVIA_D4 VIA_D3 VIA_D2 VIA_D5 U
VDDE_R2_
1V8_3V3
VDDE_R6_
1V8_3V3
VDDE_R6_
1V8_3V3
VDDE_R4_
1V8_3V3
VDDE_R4_
1V8_3V3
VDDE_R4_
1V8_3V3
VDDE_R4_
1V8_3V3VIC_D11 VIC_D13 VIC_D15 VIA_D1 VIA_D0 V
SFI_CK UARTA_TX UARTA_RX VIB0_D0VIB0_VSYN
CVIB0_MCLK VIB0_FIELD VIC_D1 VIC_D4 VIC_D14 CLK_IN CLK_OUT W
SFI_CS2 UARTB_RX UARTB_TX VIB0_D1VIB0_HSYN
CVIB0_PCLK VIB0_D12 VIC_D7 VIC_D8 VIC_VSYNC VIC_HSYNC VIC_FIELD Y
CANB_RX SPIA_DO SPIA_DI VIB0_D3 VIB0_D6 VIB0_D10 VIB0_D15 VIC_D2 VIC_D6 VIC_D12 VIC_PCLK VIC_MCLK AA
CANB_TX CANA_RX SPIA_CK VIB0_D2 VIB0_D7 VIB0_D11 VIB0_D13 VIC_D0 VIC_D3 VIC_D9 GND VDD_1V2 AB
GND CANA_TX SPIA_CS VIB0_D4 VIB0_D5 VIB0_D8 VIB0_D9 VIB0_D14 VIC_D5 VIC_D10 VDD_1V2 GND AC
12 13 14 15 16 17 18 19 20 21 22 23
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Pin List
11/18/201511/9/2015 31
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
6.1 DDR-SDRAM connectivity
EyeQ3® DDR controller supports LPDDR2 using the signals and pin descriptions as
shown in the table below. The EyeQ3® data port width is configurable to either 32-
bit or 64-bit widths (Note that EyeQ3® LITE data port width is fixed to 32-bit).
Table 1: LPDDR2-SDRAM ball description
Signal name I/O Act Voltage (V)
Curr. (mA)
Reset state
Description
DDR_A(9:0) O H 1.2 0 Command and address (device0)
DDR_A(14:10)/ LP2_DDR_A(4:0)*
O H 1.2 0 Command and address (device1)
DDR_BA(2:0)/ LP2_DDR_A(7:5)*
O H 1.2 0 Command and address (device1)
DDR_RAS_N/ LP2_DDR_A(8)*
O H 1.2 0 Command and address (device1)
DDR_CAS_N/ LP2_DDR_A(9)*
O H 1.2 0 Command and address (device1)
DDR_CS_N0 O L 1.2 1 Chip select (device0)
DDR_CS_N1* O L 1.2 1 Chip select (device1)
DDR_CKE0‡ O H 1.2 0 Clock enable (deivce0)
DDR_CKE1*‡ O H 1.2 0 Clock enable (device1)
DDR_CLK0 O H 1.2 0 Clock (device0)
DDR_CLK_N0 O L 1.2 1 Inverted clock (device0)
DDR_CLK1* O H 1.2 0 Clock (device1)
DDR_CLK_N1* O L 1.2 1 Inverted clock (device1)
DDR_DQ(31:0) B H 1.2 Z Data bus (low bits)
DDR_DQ(63:32) B H 1.2 Z Data bus (high bits)
DDR_DQS(3:0) B H 1.2 Z Data strobe (low bits)
DDR_DQS(7:4) B H 1.2 Z Data strobe (high bits)
DDR_DQS_N(3:0) B L 1.2 Z Inverted data strobe (low bits)
DDR_DQS_N(7:4) B L 1.2 Z Inverted data strobe (high bits)
DDR_DM(3:0) O H 1.2 Z Byte enable (low bits)
DDR_DM(7:4) O H 1.2 Z Byte enable (high bits)
DDR_RETENTION_N I L 1.2 Z Retains ddr_cke state while EyeQ3® supply powered down.
If power down is never employed this pin can be pulled-up.
DDR_VREF A 1.2 reference voltage
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Pin List
11/18/201511/9/2015 32
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Signal name I/O Act Voltage (V)
Curr. (mA)
Reset state
Description
DDR_ATO O 1.2 Z DDR PHY DLL analog test output
DDR_DTO(1:0) O 1.2 Z DDR PHY DLL digital test output
DDR_ZQ A 1.2 Z External reference to calibrate the output impedance.
NON_PROGAMMABLE POWER RING
* Secondary use of the pins for point to point interface between EyeQ3® and the
LPDDR2 devices (for 64-bit width).
‡ These lines should have pull-downs.
6.2 Serial Flash Interface (SFI)
EyeQ3® provides a Serial Flash Interface to support the internal vision logic (see
below for MCU Serial Flash Interface). This interface allows accesses to SPI NOR
and NAND Flash devices such as: Numonyx, Spansion, Winbond, and Macronix.
The interface implements the Multi-SPI protocol and supports single, dual, quad w/o
ddr mode transfer.
The serial interface has 3 chip selects to support 3 SPI Flash devices: up to 64MB
each .There is option to join spaces: 0 and 1 to one big space of 128MB. The
interface supports SPI Flash frequencies up to 125MHz in SDR mode and up to
62.5MHz in DDR mode.
The pin description is shown in the table below.
Table 2: Vision Serial Flash ball description
Signal name # of balls
I/O Act Voltage (V)
Curr. (mA)
Reset State*
Description
SFI_CK 1 O H 1.8/3.3 4/8 0 Clock – active only when sfi_cs is asserted
SFI_CS(2:0) 3 O L 1.8/3.3 4/8 1 Chip select
SFI_D0
1 I/O H 1.8/3.3 4/8 0 Serial output for single bit data mode or I/O for Dual or Quad mode.
SFI_D1 /
MODE1
1 I/O H 1.8/3.3 4/8 0 Serial input for single bit data mode or I/O for Dual or Quad mode.
Mode pin usage upon power on reset (por_vdd) this pin is used to select SFI sing/quad mode.
SFI_D2 /
MODE2
1 I/O H 1.8/3.3 4/8 1 Write protect (Output) in single or dual data mode I/O in Quad mode.
Should have an external pull-up (to configure unused mode on power-up)
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Pin List
11/18/201511/9/2015 33
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Signal name # of balls
I/O Act Voltage (V)
Curr. (mA)
Reset State*
Description
SFI_D3 /
MODE3
1 I/O H 1.8/3.3 4/8 1 Hold (Output) in single or dual data mode I/O in Quad mode.
Should have an external pull-up (to configure unused mode on power-up)
POWER RING 2: SFI Voltage is set by GPIO2 pin (0=1.8V, 1=3.3V) at the release of power on reset (por_vdd)
* When EyeQ3 pin reseti_n is asserted all SFI pins are at tri-state to enable an
external programmer to program the SFI flash content. When EyeQ3 pin
POR_VDD is low (0), even if reseti_n is also asserted, SFI pins are not tri-stated
and thus the external programmer cannot program the SFI flash content. For
further information on reseti_n and its interaction with POR_VDD, see section “88
Reset.”
6.3 Video Input Interface
The EyeQ3® provides a glue-less interface to three high dynamic image sensors
(which allow up to 16-bit pixels) to perform video stream capture.
Please note that, though the signal names herein appear as one, they actually refer to
the three separate ports: A, B and C (via, vib and vic ports).
Table 3: Video Interface ball description Signal name # of
balls I/O Act Voltage
(V) Curr. (mA)
Reset State
Description
VIA_D(15:0) /
VIB0_D(15:0) /
VIC_D(15:0)
16 I H 1.8/3.3 - - Video Data input (see note 1 below for internal pull-up configuration)
VIA_HSYNC /
VIB0_HSYNC /
VIC_HSYNC
1 I
LH 1.8/3.3 - Z Horizontal sync (see note 1 below for internal pull-up configuration)
VIA_VSYNC /
VIB0_VSYNC/
VIC_VSYNC
1 I
LH 1.8/3.3 - Z Vertical sync (see note 1 below for internal pull-up configuration)
VIA_PCLK S /
VIB0_PCLK S
/
VIC_PCLK S
1 I LH 1.8/3.3 - - Pixel clock
VIA_MCLK /
VIB0_MCLK /
VIC_MCLK
1 O H 1.8/3.3 4/8
1 Image sensor clock – should be disabled by software if not needed.
VIA_FIELD /
VIB0_FIELD /
VIC_FIELD
1 I H 1.8/3.3 - - Field indication for interlace video (see note 1 below for internal pull-up configuration)
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Pin List
11/18/201511/9/2015 34
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Signal name # of balls
I/O Act Voltage (V)
Curr. (mA)
Reset State
Description
POWER RING 3: VIA Voltage is set by GPIO3 pin (0=1.8V, 1=3.3V) at the release of power on reset (por_vdd)
POWER RING 4: VIB0/VIC Voltage is set by GPIO4 pin (0=1.8V, 1=3.3V) at the release of power on reset (por_vdd)
s note “S” denotes “Schmidt Trigger” buffer
Note (1): a weak (50Kohm) internal pull-down is enabled according to value programmed in the VPCR as shown in the following table (See OLB document for more details):
bit values description
000 (DEFAULT) No input device connected. All pins (d[15:0], hsync,
vsync, field, pclk) have weak internal pull down (50Kohm).
001 8bit input device connected. Unused data (d[7:0]) have weak
internal pull down (50Kohm).
010 10bit input device connected. Unused data (d[5:0]) have weak
internal pull down (50Kohm).
011 12bit input device connected. Unused data (d[3:0]) have weak
internal pull down (50Kohm).
100 16bit input device connected. All pins used, no weak internal pull
downs used.
101,110,111 illegal values will be interpreted as 100.
6.4 Video Output (and alternate Video Input) Interface
The EyeQ3® provides a glue-less interface to video display (which allows up to 16-
bit pixels) to perform video stream display. The pin description is shown in the table
below. This port is also used as an alternate video input that uses video_in channel
#5, see paragraph 4.44.4 Video Input Interfaces).
Table 4: Video Output Interface balls description Signal name # of
balls I/O Act Voltage
(V) Curr. (mA)
Reset State
Description
VIB1_D(15:0) / VO_D(15:0) **
16 B H 1.8/3.3 4/8
Z Video stream
DEFAULT is INPUT
VIB1_HSYNC/ VO_HSYNC**
1 B H 1.8/3.3 4/8
Z Horizontal sync
DEFAULT is INPUT
VIB1_VSYNC / VO_VSYNC**
1 B H 1.8/3.3 4/8
Z Vertical sync
DEFAULT is INPUT
VIB1_PCLK /
VO_PCLK** S
1 B H 1.8/3.3 4/8
Z Pixel clock
DEFAULT is INPUT
VIB1_MCLK /
NU
1 O H 1.8/3.3 4/8
1 Image sensor clock
VIB1_FIELD /
VO_EN **
1 B H 1.8/3.3 4/8
- Field indication for interlace video
POWER RING 5: vib1 Voltage is set by GPIO5 pin (0=1.8V, 1=3.3V) at the release of power on reset (por_vdd)
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Pin List
11/18/201511/9/2015 35
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
** has a weak (50Kohm) internal pull-down. s note “S” denotes “Schmidt Trigger” buffer
6.5 PDTrace Interface
The EyeQ3® provides a PDTrace port for MIPS debug. The pin description is shown
in the table below.
Table 5: PDTrace Interface ball description
Signal name # of balls
I/O Act Voltage (V)
Curr. (mA)
Reset State
Description
PDT_D(15:0) 16 O H 1.8/3.3 4/8 Z pdtrace data
PDT_TRIGOUT 1 O H 1.8/3.3 4/8 Z pdt trigger output (debug ack)
PDT_PROBE_N*** 1 I L 1.8/3.3 Z pdt enable (low true)
PDT_CLK 1 O H 1.8/3.3 4/8 - pdt clock
PDT_DM 1 O H 1.8/3.3 4/8 1 pdt debug mode entered
PDT_TRIGIN** 1 I H 1.8/3.3 - pdt trigger in (debug request)
POWER RING 5: pdt Voltage 1.8/3.3V is set by GPIO5 pin (0=1.8V, 1=3.3V) at the release of power on reset (por_vdd)
** has a weak (50Kohm) internal pull-down. *** has a weak (50Kohm) internal pull-up.
6.6 1Gb Ethernet / AVB Interface
The EyeQ3® provides an RGMII connection to communicate with external Ethernet
PHY. The pin description is shown in the table below.
Table 6: Ethernet Interface ball description Signal name # of
balls I/O Act Voltage
(V) Curr. (mA)
Reset State
Description
RGMII_TD[3:0] 4 O H 1.8/3.3 4/8 Transmit Data
RGMII_TX_CTL 1 O H 1.8/3.3 4/8 Transmit Control
RGMII_TX_CLK 1 O H 1.8/3.3 4/8 Transmit Clock
RGMII_RD[3:0]* 4 I H 1.8/3.3 - Receive Data
RGMII_RX_CTL* 1 I H 1.8/3.3 - Receive Control
RGMII_RX_CLK* 1 I H 1.8/3.3 - Receive Clock
SMA_MDIO 1 I/O H 1.8/3.3 4/8 Z Data (DEFAULT is INPUT), should external have pull-up.
SMA_MDC 1 O H 1.8/3.3 4/8 0 Clock
POWER RING 5: Ethernet I/F Voltage is set by GPIO5 pin (0=1.8V, 1=3.3V) at the release of power on reset (por_vdd)
* CUT1: These inputs do not have internal pull-downs thus the PCB should implement external pull downs if the lines are not used.
CUT2: These inputs have weak (50K) internal pull-downs.
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Pin List
11/18/201511/9/2015 36
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
6.7 I2C (a/b) Interfaces
The EyeQ3® provides two Master/Slave I2C interfaces to communicate with external
peripherals such as Image Sensors. It supports up to 1Mbs transfer rate (Fast Plus
mode). The pin description is shown in the table below.
Table 7: I2C balls description
Signal name # of balls
I/O Act Voltage (V)
Curr. (mA)
Reset State
Description
I2CA_SDA 1 B H 1.8/3.3 note1 1 I2C data; requires external pull-up according to I2C spec. (See note 3 here)
Even if unused should have external pull-up.
I2CA_SCLK 1 B H 1.8/3.3 note1 1 I2C clock; requires external pull-up according to I2C spec. (See note 3 here)
Even if unused should have external pull-up.
I2CB_SDA 1 B H 1.8/3.3 note1 1 I2C data; requires external pull-up according to I2C spec. (See note 3 here)
Even if unused should have external pull-up.
I2CB_SCLK 1 B H 1.8/3.3 note1 1 I2C clock; requires external pull-up according to I2C spec. (See note 3 here)
Even if unused should have external pull-up.
POWER RING 3: I2CA Voltage is set by GPIO3 pin (0=1.8V, 1=3.3V) at the release of power on reset (por_vdd)
POWER RING 5: I2CB Voltage is set by GPIO5 pin (0=1.8V, 1=3.3V) at the release of power on reset (por_vdd)
Notes:
(1) Current Drive for I2C pads (where VDDE is VDDE_R(3,5)_1V8_3V3)
FAST mode (400 KHz) (DEFAULT):
1V8: Drive @0.2*VDDE = 4.5mA-6.0mA
3V3: Drive @0.2*VDDE = 3.5mA-5.5mA
FAST PLUS mode (1MHz):
1V8: Drive @0.2*VDDE = 5.0mA-6.0mA
3V3: Drive @0.2*VDDE = 5.8mA-8.1mA
(2) These pads have are 2 parameters critical for proper function of the interface:
Bus Load Parameter: The pad has programmable external current sources (see MCSR register description in OLB Spec.
– bit “i2c_hload”) which, depending on the load, will add a current source to maintain rise and fall
times. The default is for less than 100pF loads (i.e., no current source used).
Spike Filter Parameter:
The pad has programmable spike filter (see MCSR register description in OLB Spec. – bit
“i2c_filter_en”) - The filter value is fixed in conjunction with High Speed or Fast Plus mode value
(enhs) programmed in I2C IP registers such that when the filter is enabled: if enhs=0 (DEFAULT),
50ns spikes are filtered and if enhs=1, 10ns spikes are filtered.
(3) External Pull-Up Resistor Values (note: “High Speed” values are for Fast Plus also, i.e.,
frequencies up to 3.4Mb/s. The default for EyeQ3 is Fast mode – i.e., frequencies up to 400Kb/s –
the EyeQ3 is programmed to 200Kb/s):
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Pin List
11/18/201511/9/2015 37
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
6.8 UART (a/b) Interfaces (with alt. GPIO connectivity)
The EyeQ3® provides two UART interfaces to communicate with external
peripherals such as a keyboard. It supports up to 5MHz transfer rate. The pin
description is shown in the table below.
Table 8: UART balls description Signal name # of
balls I/O Act Voltage
(V) Curr. (mA)
Reset State
Description
UARTA_TX /
GPIO18
1 O / B H / LH
1.8/3.3 2/4 z UART transmit data or Programmable general purpose input and output
DEFAULT STATE is GPIO input
UARTA_RX /
GPIO19
1 I / B H / LH
1.8/3.3 2/4 z UART receive data or Programmable general purpose input and output
DEFAULT STATE is GPIO input, if unused should external have pull-up.
UARTB_TX /
GPIO20
1 O / B H / LH
1.8/3.3 2/4 z UART transmit data or Programmable general purpose input and output
DEFAULT STATE is GPIO input
UART_RX /
GPIO21
1 I / B H / LH
1.8/3.3 2/4 z UART receive data or Programmable general purpose input and output
DEFAULT STATE is GPIO input, if unused should external have pull-up.
POWER RING 6: UART Voltage is set by GPIO6 pin (0=1.8V, 1=3.3V) at the release of power on reset (por_vdd)
6.9 CAN (a/b) Interfaces (with alt. GPIO connectivity)
The EyeQ3® provides two CAN interfaces to communicate with external peripherals,
such as the automobile’s CAN network. EyeQ3® supports up to 1Mbs throughput.
The pin description is shown in the table below.
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Pin List
11/18/201511/9/2015 38
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Table 9: CAN balls description
Signal name # of balls
I/O Act Voltage
(V)
Curr.
(mA)
Reset State
Description
CANA_TX /
-
1 O H 1.8/3.3 1/4 1 CAN transmit data
CANA_RX /
-
1 I H 1.8/3.3 2/4 Z CAN receive data
CANB_TX /
GPIO22
1 O / B H / LH 1.8/3.3 2/4 Z CAN transmit data or Programmable general purpose input and output
DEFAULT STATE is GPIO input
CANB_RX /
GPIO23
1 I / B H / LH 1.8/3.3 2/4 Z CAN receive data or Programmable general purpose input and output
DEFAULT STATE is GPIO input, if unused should external have pull-up.
POWER RING 6: CAN Voltage is set by GPIO6 (0=1.8V, 1=3.3V) at the release of power on reset (por_vdd)
6.10 SPI (a/b) Interfaces (with alt. GPIO connectivity)
The EyeQ3® provides two SPI interfaces to communicate with external peripherals.
The maximum throughput frequencies are 31.25MHZ (Master)/15.62MHz (Slave).
The pin description is shown in the table below.
Table 10: SPI balls description
Signal name # of balls
I/O Act Voltage
(V)
Curr.
(mA)
Reset State
Description
SPIA_DO /
GPIO24
1 O / B H / LH 1.8/3.3 2/4 z SPI transmit data or Programmable general purpose input and output
DEFAULT STATE is GPIO input
Note: When SPI is enabled, regardless of the state of the SPI_CS, the data out line is always active and so if multiple slaves are connected this line needs to be tri-stated externally.
SPIA_DI /
GPIO25
1 I / B H / LH 1.8/3.3 2/4 z SPI receive data or Programmable general purpose input and output
DEFAULT STATE is GPIO input
SPIA_CK /
GPIO26
1 B / B H / LH 1.8/3.3 2/4 z SPI clock or Programmable general purpose input and output
DEFAULT STATE is GPIO input
SPIA_CS /
GPIO27
1 B / B H / LH 1.8/3.3 2/4 z SPI chip select or Programmable general purpose input and output
DEFAULT STATE is GPIO input
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Pin List
11/18/201511/9/2015 39
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Signal name # of balls
I/O Act Voltage
(V)
Curr.
(mA)
Reset State
Description
SPIB_DO /
GPIO28
1 O / B H / LH 1.8/3.3 2/4 z SPI transmit data or Programmable general purpose input and output
DEFAULT STATE is GPIO input
Note: When SPI is enabled, regardless of the state of the SPI_CS, the data out line is always active and so if multiple slaves are connected this line needs to be tri-stated externally.
SPIB_DI /
GPIO29
1 I / B H / LH 1.8, 3.3 2/4 z SPI receive data or Programmable general purpose input and output
DEFAULT STATE is GPIO input
SPIB_CK /
GPIO30
1 B / B H / LH 1.8, 3.3 2/4 z SPI clock or Programmable general purpose input and output
DEFAULT STATE is GPIO input
SPIB_CS /
GPIO31
1 B / B H / LH 1.8, 3.3 2/4 z SPI chip select or Programmable general purpose input and output
DEFAULT STATE is GPIO input
POWER RING 6: spia Voltage is set by GPIO6 pin (0=1.8V, 1=3.3V) at the release of power on reset (por_vdd)
POWER RING 8: spib Voltage is set by GPIO8 pin (0=1.8V, 1=3.3V) at the release of power on reset (por_vdd)
6.11 General Purpose Input Output (GPIO) and Timer I/O
The EyeQ3® provides 18 GPIO pins to communicate with external devices such as
LEDs, buzzers, etc.. The pin description is shown in the table below.
Table 11: GPIO / Timer balls description Signal name # of
balls I/O Act Voltage
(V) Curr. (mA)
Reset State
Description
GPIO0 /
TIMER_CK0
1 B LH 1.8/3.3 2/4 z Programmable general purpose input and output or Timer clock
DEFAULT STATE is GPIO input
GPIO1 /
TIMER_CK1
1 B LH 1.8/3.3 2/4 z Programmable general purpose input and output or Timer clock
DEFAULT STATE is GPIO input
GPIO2 /
TIMER_CK2 /
PWRMODE2
1 B LH 1.8/3.3 2/4 z Programmable general purpose input and output or Timer clock or power mode select
DEFAULT STATE is GPIO input
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Pin List
11/18/201511/9/2015 40
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
GPIO3 /
TIMER_CK3 /
PWRMODE3
1 B LH 1.8/3.3 2/4 z Programmable general purpose input and output or Timer clock or power mode select
DEFAULT STATE is GPIO input
GPIO4 /
TIMER_EOC0 /
PWRMODE4
1 B LH 1.8/3.3 2/4 z Programmable general purpose input and output or Timer end of count or power mode select
DEFAULT STATE is GPIO input
GPIO5 /
TIMER_EOC1 /
PWRMODE5
1 B LH 1.8/3.3 2/4 z Programmable general purpose input and output or Timer end of count or power mode select
DEFAULT STATE is GPIO input
GPIO6 /
TIMER_EOC2 /
PWRMODE6
1 B LH 1.8/3.3 2/4 z Programmable general purpose input and output or Timer end of count or power mode select
DEFAULT STATE is GPIO input
GPIO7 /
TIMER_EOC3 /
PWRMODE7
1 B LH 1.8/3.3 2/4 z Programmable general purpose input and output or Timer end of count or power mode select
DEFAULT STATE is GPIO input
GPIO8 /
TIMER_EXT0_INCAP1 /
PWRMODE8
1 B LH 1.8/3.3 2/4 z Programmable general purpose input and output or Timer external input capture or power mode select
DEFAULT STATE is GPIO input
GPIO9 /
TIMER_EXT0_INCAP2
1 B LH 1.8/3.3 2/4 z Programmable general purpose input and output or Timer external input capture
DEFAULT STATE is GPIO input
GPIO10 /
TIMER_EXT0_OUTCMP1
1 B LH 1.8/3.3 2/4 z Programmable general purpose input and output or Timer external output compare
DEFAULT STATE is GPIO input
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Pin List
11/18/201511/9/2015 41
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
GPIO11 /
TIMER_EXT0_OUTCMP2
1 B LH 1.8/3.3 2/4 z Programmable general purpose input and output or Timer external output compare
DEFAULT STATE is GPIO input
POWER RING 7: GPIO(0;11) Voltage is set by GPIO7 pin (0=1.8V, 1=3.3V) at the release of power on reset (por_vdd)
GPIO12 /
TIMER_CK4
1 B LH 1.8/3.3 2/4 z Programmable general purpose input and output or Timer clock
DEFAULT STATE is GPIO input
GPIO13 /
TIMER_EOC4
1 B LH 1.8/3.3 2/4 z Programmable general purpose input and output or Timer end of count
DEFAULT STATE is GPIO input
GPIO14 /
TIMER_EXT1_INCAP1
1 B LH 1.8/3.3 2/4 z Programmable general purpose input and output or Timer external input capture or power mode select
DEFAULT STATE is GPIO input
GPIO15 /
TIMER_EXT1_INCAP2
1 B LH 1.8/3.3 2/4 z Programmable general purpose input and output or Timer external input capture
DEFAULT STATE is GPIO input
GPIO16 /
TIMER_EXT1_OUTCMP1
1 B LH 1.8/3.3 2/4 z Programmable general purpose input and output or Timer external output compare
DEFAULT STATE is GPIO input
GPIO17 /
TIMER_EXT1_OUTCMP2
1 B LH 1.8/3.3 2/4 z Programmable general purpose input and output or Timer external output compare
DEFAULT STATE is GPIO input
POWER RING 8: GPIO(12:17) Voltage is set by GPIO8 pin (0=1.8V, 1=3.3V) at the release of power on reset (por_vdd)
6.12 Clocks, Reset, Controls Interface
The following section describes the pins for clocks (and their circuitry), reset,
interrupts, temp sensors, and miscellaneous controls.
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Pin List
11/18/201511/9/2015 42
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Table 12: Clocks, Resets, Interrupts, Analog pins description
Signal name # of balls
I/O Act Voltage (V)
Curr. (mA)
Reset State
Description
CLK_IN 1 A - - crystal ring input.
Ball sfi_d0 should be connected to a weak pull-down (10K) for an external clock and to a weak pull-up (10K) for a crystal.
CLK_OUT 1 A - 0 Crystal ring out
VREG_BYPASS 0 I 2.5 - put all 3 VREGs in BYPASS –
This pad will only be connected to a BUMP and not to a BALL (i.e., available for production testing only).
NO POWER RING: all of the above signals are connected to fixed power (2.5V)
POR_VDD S
1 A 1.8/3.3 - input for external asynchronous Reset during power on, should be asserted (low) until all EyeQ3® power supplies are on and stable
RESETI_N S
1 I L 1.8/3.3 - - input for external Reset
RESETO_N 1 O L 1.8/3.3 2/4 0 output to indicate external reset signal
XINT(1:0)/GPI 2 I H 1.8/3.3 - - external interrupt input signals
disabled on power-up; configurable polarity and level/edge in MIPS GIC
has weak (50K ohm) internal pull-down
Can be used as a GPI (General Purpose Input) – e.g., for PCB version number. Such usage MUST be coordinated with SW to avoid enabling as XINT.
FUSE_HV
1 A - High Voltage for Fuse should be connected to gnd (but can float).
POWER RING 7: Voltage is set by GPIO7 pin (0=1.8V, 1=3.3V) at the release of power on reset (por_vdd)
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Pin List
11/18/201511/9/2015 43
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Signal name # of balls
I/O Act Voltage (V)
Curr. (mA)
Reset State
Description
XINT(3:2) 2 I H 1.8/3.3 - - external interrupt input signals
disabled on power-up; configurable polarity and level/edge in MIPS GIC
has weak (50K ohm) internal pull-down
POWER RING 8: xint(3:2) Voltage is set by GPIO8 pin (0=1.8V, 1=3.3V) at the release of power on reset (por_vdd)
3V3VREG1_COREPWR(1) 1 A 3.3 - 3.3V for 2.5V VREG for PLLA
VREG1_COREGND* 1 A 3.3 - GND for 2.5V VREG for PLLA – must be connected to AGND on PCB
2V5VREG1_COREPWR 1 B 2.5 - This testpoint should be left floating (it has an internal decoupling cap for noise immunity).
If the pin is used to monitor the 2.5V VREG output it must not be loaded with more than 100pF and should be well isolated from noise.
3V3VREG2_COREPWR(1) 1 A 3.3 - 3.3V for 2.5V VREG for PLLB
VREG2_COREGND* 1 A 3.3 - GND for 2.5V VREG for PLLB – must be connected to AGND on PCB
2V5VREG2_COREPWR 1 B 2.5 - This testpoint should be left floating (it has an internal decoupling cap for noise immunity).
If the pin is used to monitor the 2.5V VREG output it must not be loaded with more than 100pF and should be well isolated from noise.
3V3VREG3_COREPWR(1) 1 A 3.3 - 3.3V for 2.5V VREG for PLLC
VREG3_COREGND* 1 A 3.3 - GND for 2.5V VREG for PLLC – must be connected to AGND on PCB
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Pin List
11/18/201511/9/2015 44
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Signal name # of balls
I/O Act Voltage (V)
Curr. (mA)
Reset State
Description
2V5VREG3_COREPWR 1 B 2.5 - This testpoint should be left floating (it has an internal decoupling cap for noise immunity).
If the pin is used to monitor the 2.5V VREG output it must not be loaded with more than 100pF and should be well isolated from noise.
1V2PLLA_COREPWR* 1 A 1.2 - Analog Power for PLLA – must be connected to Analog 1V2 on PCB
1V2PLLA_COREGND* 1 A 1.2 - Analog Ground for PLLA – must be connected to AGND on PCB
1V2PLLB_COREPWR* 1 A 1.2 - Analog Power for PLLB– must be connected to Analog 1V2 on PCB
1V2PLLB_COREGND* 1 A 1.2 - Analog Ground for PLLB – must be connected to AGND on PCB
1V2PLLC_COREPWR* 1 A 1.2 - Analog Power for PLLC– must be connected to Analog 1V2 on PCB
1V2PLLC_COREGND* 1 A 1.2 - Analog Ground for PLLC – must be connected to AGND on PCB
1V2OSC_COREPWR* 1 A 1.2 - Analog Power for the OSC– must be connected to Analog 1V2 on PCB
1V2OSC_COREGND* 1 A 1.2 - Analog Ground for the OSC – must be connected to AGND on PCB
1V8TEMPSENS0_COREPWR*
1 A 1.8 - 1.8V for TSENS0– must be connected to Analog 1V8 on PCB
1V8TEMPSENS0_COREGND*
1 A 1.8 - Analog Ground for TSENS0 – must be connected to AGND on PCB
1V8TEMPSENS1_COREPWR*
1 A 1.8 - 1.8V for TSENS1– must be connected to Analog 1V8 on PCB
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Pin List
11/18/201511/9/2015 45
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Signal name # of balls
I/O Act Voltage (V)
Curr. (mA)
Reset State
Description
1V8TEMPSENS1_COREGND*
1 A 1.8 - Analog Ground for TSENS1 – must be connected to AGND on PCB
NO POWER RING: all of the above signals are connected to fixed power
* these analog pins should be connected to a separate analog plane which is then connected to the digital plane via ferrite bead (i.e., AGND to DGND, A1V2 to 1V2, A1V8 to 1V8). s note “S” denotes “Schmidt Trigger” buffer
(1) For CUT1 ONLY: the voltage ramp-up must be greater than 1ms and the
maximum allowed ripple must be less than or equal to 200mV peak to peak.
6.13 JTAG Interface
The JTAG port is used to debug the PCB and the software (MIPS debug mode). It
supports up to 30MHz clock rate. The balls description is shown in the table below.
Table 13: Jtag0 for boundary balls scan Signal name # of
balls I/O Act Voltage
(V) Curr. (mA)
Reset State
Description
TESTEN* 1 I H 1.8 / 3.3 - - Refer to section 8.3
NTRST_N* S
1 I L 1.8 / 3.3 - - Reset Jtag port
TDI 1 I H 1.8 / 3.3 - - Jtag Data Insert
TDO 1 O H 1.8 / 3.3 4/8 z Jtag data out
TMS 1 I H 1.8 / 3.3 - - Jtag Test Mode Select
This pin MUST be pulled up. If it is perceived as low during normal operation it can cause the chip to fail.
TCK S
1 I H 1.8 / 3.3 - - Jtag clock – 33MHZ
POWER RING 7: Voltage is set by GPIO7 pin (0=1.8V, 1=3.3V) at the release of power on reset (por_vdd)
* has a weak (50Kohm) internal pull-down. s note “S” denotes “Schmidt Trigger” buffer
6.14 Power Interface
The power balls are used for the Core and I/O. The pin description is shown in the
table below.
Table 14: Power pin description Signal name # of balls
EyeQ3® Description
VDD_1V2 74 Digital Core Power 1.2V supplies
GND 79 Digital Core Ground
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Pin List
11/18/201511/9/2015 46
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Signal name # of balls EyeQ3®
Description
VDDE_VDDQ_ISLAND_1V8_1V5_1V2 2 DDR Island power
VDDE_R0_1V8_1V5_1V2 10 RING0 POWER - Digital LPDDR2
VDDE_R1_1V8_1V5_1V2 6 RING1 POWER - Digital LPDDR2
VDDE_R2_1V8_3V3 2 RING2 POWER - SFI
I/O Power Supply 1.8 or 3.3V Voltage is set by gpio2 pin at the release of power on reset (por_vdd)
VDDE_R3_1V8_3V3 2 RING3 POWER – VIA, I2CA
I/O Power Supply 1.8 or 3.3V Voltage is set by gpio3 pin at the release of power on reset (por_vdd)
VDDE_R4_1V8_3V3 4 RING4 POWER – VIB0, VIC
I/O Power Supply 1.8 or 3.3V Voltage is set by gpio4 pin at the release of power on reset (por_vdd)
VDDE_R5_1V8_3V3 10 RING5 POWER – Powers PDT, RGMII, I2CB, VIB1
I/0 Power Supply 1.8 or 3.3V Voltage is set by gpio5 pin at the release of power on reset (por_vdd)
VDDE_R6_1V8_3V3 2 RING6 POWER – UARTA/B, CANA/B, SPIA
I/0 Power Supply 1.8 or 3.3V Voltage is set by gpio6 pin at the release of power on reset (por_vdd)
VDDE_R7_1V8_3V3 4 RING7 POWER – GPIO(0:11)/TIMERS, POR_VDD, RESETI_N, RESETO_N, TESTEN, XINT(0:1), JTAG, FUSE_HV
I/0 Power Supply 1.8 or 3.3V Voltage is set by gpio7 pin at the release of power on reset (por_vdd)
VDDE_R8_1V8_3V3 2 RING8 POWER – SPIB/GPIO(28:31), GPIO(12:17)/TIMERS, XINT(2:3)
I/0 Power Supply 1.8 or 3.3V Voltage is set by gpio8 pin at the release of power on reset (por_vdd)
REXT_R2 1 RING2 external PULL DOWN resistor used for accurate mode of internal voltage compensation cell. MUST be connected to external resistor of 121Kohm with +/-1% accuracy.
Should be placed close to pad.
REXT_R5 1 RING5 external PULL DOWN resistor used for accurate mode of internal voltage compensation cell. MUST be connected to external resistor of 121Kohm with +/-1% accuracy.
Should be placed close to pad.
6.15 No Connects
The following pins are no connects.
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Pin List
11/18/201511/9/2015 47
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Table 15: NC pin description
Signal name # of balls
I/O Act Voltage (V)
Curr. (mA)
Reset State
Description
NC0 1 I - - - - Must be left unconnected.
Has an week internal pull-down.
NC1 1 I - - - - Must be left unconnected.
Has an week internal pull-down.
NC2 1 O - - - - Must be left unconnected.
NC3 1 O - - - - Must be left unconnected.
NC4 1 O - - - - Must be left unconnected.
NC5 1 O - - - - Must be left unconnected.
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Electrical Specifications
11/18/201511/9/2015 48
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
7. Electrical Specifications This section provides power and timing details and includes the following
subsections:
Absolute Maximum Ratings
Power Supply Specifications
DC IO Characteristics
AC Characteristics
7.1 Absolute Maximum Ratings
Stresses that occur above or below those listed in the table below may cause
permanent damage to the EyeQ3®.
Note: These are stress ratings only. Functional operation of the device at these or
any other conditions beyond those listed in Section 7.27.2 is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Table 16: Absolute maximum ratings
Parameter Maximum Units
VDD_1V2 1.26 V
VDDE_R(0:1)_1V8_1V5_1V2 note 1 V
VDDE_R(2:8)_1V8_3V3 1.95/3.6 V
VDDE_VDDQ_ISLAND_1V8_1V5_1V2 note 1 V
3V3VREG(1:3)_COREPWR 3.6 V
1V2PLL(A:C)_COREPWR 1.26 V
1V2OSC_COREPWR 1.26 V
1V8TEMPSENS(0:1)_COREPWR 2.75 V
note 1: VDDE_R(0:1)_1V8_1V5_1V2, VDDE_VDDQ_ISLAND_1V8_1V5_1V2
values are described in Table 21: LPDDR2 Interface DC Electrical
CharacteristicsTable 21: LPDDR2 Interface DC Electrical Characteristics.
* This device employs CMOS technology on all signal balls. It should be
handled as an ESD sensitive device. Voltage on any signal pin that exceeds
the power supply voltage by more than +0.5 V can induce destructive latch-
up.
7.2 Power Supply Specifications
The typical estimated total power consumption is less than 3W depending on various
factors such as: the specific application being run, the corresponding IO activity, as
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Electrical Specifications
11/18/201511/9/2015 49
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
well as board components and layout. Special power-saving features are
implemented, like having the clock of the functional blocks being shut off
automatically when the blocks are idle. For further power saving, a special on-chip
power management circuit enables the EyeQ3TM
SW to power off and on each of the
4 VMPs and 3 MIPSs blocks, on an individual basis. There is also a power saving
mode that allows the EyeQ3 to be completely powered down while still maintaining
the DDR contents for subsequent fast power on.
Table 17: Voltage variation
Loading power Nominal Voltage Voltage Variation
VDD_1V2;
1V2PLL(A:C)_COREPWR;
1V2OSC_COREPWR
1.2V +/- 5%
VDDE_R(0:1)_1V8_1V5_1V2;
VDDE_VDDQ_ISLAND_1V8_1V5_1V2
when using LPDDR2
1.2V +/- 5%
3V3VREG(1:3)_COREPWR(1) 3.3V 3.0V – 3.6V
1V8TEMPSENS(0:1)_COREPWR 1.8V +/- 5% (1)
For CUT1 ONLY: For the 3V3VREG(1-3)_COREPWR inputs: the voltage ramp-up
must be greater than 1ms and the maximum allowed ripple must be less than or equal to 200mV peak to peak.
Table 18: Steady state current Power
Power Supply Voltage Range Typical(2) Maximum
VDD_1V2 (3) 1.2V+/- 5% 2A 3.5A(1)
VDDE_R(2:8)_1V8_3V3 when using 3V3(3)
3.3V +/- 10% - 300mA
VDDE_R(2:8)_1V8_3V3 when using 1V8(3)
1.8V +/- 5% - 400mA
VDDE_R(0:1)_1V8_1V5_1V2;
VDDE_VDDQ_ISLAND_1V8_1V5_1V2
when using LPDDR2(3)
1.2V +/- 5% 0.3A 0.9A
NOTES: (1) The worst case transient current is the transient current that depends on the worst case application and data. The maximum current should be measured on the customer board at worst case conditions. For pre-PCB calculations the worst case transient current given here should be used.
(2) For thermal estimations, the application should be run on the customer board at worst case conditions (temperature and voltage) and the typical current should be measured. For pre-PCB estimations the typical case current given here should be used.
(3) These values are estimates and will vary depending on the application running and the agents on the board.
7.2.1 Power Up/Down Sequence
The following sections describe the various power sequencing required by the EyeQ3.
There are no other special power-up or power-down sequences other than those
described here.
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Electrical Specifications
11/18/201511/9/2015 50
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
7.2.1.1 DDR
The following sections discuss the power up sequence as it relates to the EyeQ3. For
the power up sequence recommendation that accounts for the external DDR device,
please refer to the EyeQ3 PCB Design Guide.
7.2.1.1.1 DDR PHY
The following section describes the relation of the EyeQ3 Core power (VDD_1V2,
referred to as VDD (Core)) versus the EyeQ3 IO power
(VDDE_R(0:1)_1V8_1V5_1V2, referred to as VDD (IO)).
There are no specific requirements for VDD (Core) and VDD (IO) power sequencing
on power on/off.
The user should be aware that if the I/O is powered up before the core, there can be
large current draws between these two events because the I/O is powered-up but is
not supplied with valid control signals, thus it can be in an undefined high-current
state. Conversely, if the core is powered up before the I/O, the core may consume a
slightly higher current than normal due to not being supplied with valid CMOS level
signals from the I/O, but this will be a low additional current draw. It is generally
recommended that the VDD (Core) and VDD (IO) supplies be powered-up together,
and it is generally also acceptable for the VDD (Core) supply to power-up a very
short time before the VDD (IO) supply. If the VDD (IO) supply must power-up
before the VDD (Core) supply, it is advised to keep the time between these two
events less than 100ms to limit excessive VDD (IO) current draws.
7.2.1.1.2 When using LPDDR2
To operate LPDDR2 a special power on/off sequence is required (as defined by the
specific LPDDR2 component). The 1.8v (i.e., of the LPDDR2 core) should always be
200mV higher than the 1.2V (i.e., of the LPDDR2 I/O) both for power on and power
off (as specified in the LPDDR2 standard).
As such, the 1.8V (for the LPDDR2 core and EyeQ3 Temperature Sensor power)
must be powered first, followed by the 1.2V (for the LPDDR2 I/Os, EyeQ3 DDR
I/Os). This is done in HW via the 1.8V's “good” signal which will enable the 1.2V
supply. As a result, EyeQ3 LPDDR2 1.2V I/Os and 1.2V Core Circuitry will get the
same power.
7.2.2 IO Power Sequence
The IO pad rails (VDDE) must be powered before driving voltage on the IO signal
(VPAD) into the EyeQ3. For details please see EyeQ3 PCB Design Guide.
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Electrical Specifications
11/18/201511/9/2015 51
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
7.3 DC I/O Characteristics
The following tables describe the IO pads for power rings that allow multiple voltage
inputs (1.8V or 3.3V). If 1.8V operation is selected then the pads will operate
according to Table 19: 1.8V DC IO Characterization; if 3.3V operation is selected
then the pads will operate according to Table 21: 3.3V DC IO Characterization.
Table 19: 1.8V DC IO Characterization*
Parameter Description Condition Min Max Units
VIH Input High voltage 0.65 *VDDE VDDE +0.3 V
VIL Input low voltage -0.3 0.35 *VDDE V
VOL Output low voltage IOL = 1mA for BDX
IOL = 2mA for BD2X
IOL = 4mA for BD4X
- 0.4 V
VOH Output High voltage IOL = 1mA for BDX
IOL = 2mA for BD2X
IOL = 4mA for BD4X
VDDE - 0.4 - V
CPIN Input pin capacitance for output mode - 3 pF
* VDDE indicates the VDDE_Rn_1V8_3V3 pin input being driven at 1.8V
Table 20: 3.3V DC IO Characterization*
Parameter Description Condition Min Max Units
VIH Input High voltage 2.0 VDDE +0.3 V
VIL Input low voltage -0.3 0.8 V
VOL Output low voltage IOL = 2mA for BDX
IOL = 4mA for BD2X
IOL = 8mA for BD4X
- 0.4 V
VOH Output High voltage IOH = 2mA for BDX
IOH = 4mA for BD2X
IOH = 8mA for BD4X
VDDE - 0.4 - V
CPIN Input pin capacitance for output mode - 3 pF
* VDDE indicates the VDDE_Rn_1V8_3V3 pin input being driven at 3.3V
7.3.1 Special cases
In the case where the IO voltage is driven but the Core voltage is not, there is no
additional current consumption during core-off mode and the state of the IOs will be
tri-state – this applies to all BDX, BD2X, BD4X and I2C pads.
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Electrical Specifications
11/18/201511/9/2015 52
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Note that voltage on any signal pin that exceeds the power supply voltage (to the pad
ring) by more than +0.5 V can induce destructive latch-up.
7.4 DDR SDRAM DC Characteristics
The following table provides the recommended operating conditions for EyeQ3®
LPDDR2 interface.
Table 21: LPDDR2 Interface DC Electrical Characteristics
Symbol Parameter/Condition Min. Nom. Max. Unit Notes
VDDE_R(0:1)_1V8_1V5_1V2 (VDDQ)
VDDE_VDDQ_ISLAND_1V8_1V5_1V2
I/O supply voltage 1.14 1.2 1.26
V
DDR_VREF (VREF) Reference supply voltage 0.49*VDDQ 0.5*VDDQ 0.51*VDDQ V 1,2
VIH(DC) DC input voltage High VREF+0.13 VDDQ V
VIL(DC) DC input voltage Low GND-0.3 VREF-0.13 V
VOH DC output logic High 0.9*VDDQ V
VOL DC output logic Low 0.1*VDDQ V
Notes:
1. Peak-to-peak noise on DDR_VREF may not exceed 5% DDR_VREF (DC).
2. DDR_VREF of the receiving device(s) should track the variations in the DC
value of VDDE_R(0:1)_1V8_1V5_1V2 of the sending device for best noise
margins.
7.5 AC Characteristics
The AC timing specifications are listed in the following sections:
Clock AC
SPI Timing
SFI Timing
Serial i2c pin timing
RGMII interface timing
Video Stream interface timing
PDT interface timing
Reset Pin Timing
MDDR-SDRAM interface timing
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Electrical Specifications
11/18/201511/9/2015 53
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
7.5.1 Clock AC
Referring to the OSC input pins:
Table 22: Crystal Input
Description Value
Crystal Frequency 27-30 MHz
7.5.1 SPI Timing
The following diagram describes the SPI timing.
SCLK
MTSR
SLSO
MRST
t51a
t52t52 t53
t51b
t50
t56 t57
SCLK
MTSR
SLSI
MRST
t61
t56 t57
t54
t55h t55l
t58
t60t60
t59
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Electrical Specifications
11/18/201511/9/2015 54
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
While the SPI I/F can operate at 1.8V or 3.3V, the following table describes the
timing of the above diagrams based on 3.3V, 30pF operation.
Table 23: Serial Port Interface timing(2)
Parameter Symbol
Values Unit
Min Max
MA
ST
ER
MO
DE
1
SCLK period t50 32.00 nS
2a
SLSO assertion to SCLK leading
(7) edge t51a a*t50-1.37
(4) a*t50+3.87
(4) nS
2b
MTSR delay from SCLK leading
(7) edge t51b b*t50-1.37
(5) b*t50+3.87
(5) nS
3
MRST setup to SCLK falling edge t52 7.83-N0
(1) nS
4
MRST hold from SCLK falling edge t53 0.00+N1
(1) nS
SL
AV
E M
OD
E
5
SCLK clock period t54 64.00 nS
6
SCLK input clock low/high time t55h,t55l 0.45*t54 0.55*t54 nS
7
MTSR setup to SCLK latching edge t56 0.92
(3) nS
8
MTSR hold from SCLK latching edge t57 0.26
(3) nS
9
SLSI setup to first SCLK latching edge t58 0.92
(3) nS
10
SLSI hold from last SCLK latching edge t59 0.26
(3) nS
11
MRST delay from SCLK shift edge t60 21.51
(3) 34.68
(3) nS
(1) By adding delay elements which are selected by programming the SPI IP,
one can relax the setup time and stress the hold time).
N0 = 7.6ns*NUM_FBCLK_DLYELEMENTS (i.e., the total feedback
clock delay). N1 = 8.4ns*NUM_FBCLK_DLYELEMENTS (i.e., the total
feedback clock delay).
(2) 3.3V, 30pF operation.
(3) Values in the table are based on 50% duty cycle. Any offset from this value
must be taken into account.
(4) The parameter “a” is either “1” or “1/2” depending on programming
(SPH=0: a=1; SPH=1: a=0.5).
(5) The parameter “b” is either “0” or “1/2” depending on programming
(SPH=0: b=0.5; SPH=1: b=0).
(6) Following the last bit, SLSO will deassert one SCLK cycle after the SCLK
output has been deasserted.
(7) Depending on programming (SPO=0: rising edge; SPO=1: falling edge).
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Electrical Specifications
11/18/201511/9/2015 55
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
For 1.8V operation with 30pF load
For 3.3V operation with 30pF load
7.5.2 Serial Flash Interface (SFI) Timing
7.5.2.1 Frequency versus external load
The SFI clock frequency is given by the following formula:
SFI clock = VCO/(Ndiv*L);
VCO – constant frequency of 1500MHz.
Ndiv – can be configured from 6 to 15.
L – can be 2,4,8
7.5.2.2 SDR mode
Tcss
MSB MSB -1 LSB
Tcsh
MSB
Tcs
Tch Tcl Tr TfTv
MSB
TsuThd
SDR SerFin timing
sfi_cs
sfi_ck
sfi_d[0..3]
sfi_cs
sfi_ck
sfi_d[0..3]
Write
Read
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Electrical Specifications
11/18/201511/9/2015 56
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
7.5.2.3 DDR Mode
OpCode
sfi_cs
sfi_ck
DDR SerFin timing
MSBL
S
B
Tv Tv
MSB LSB
Tsu Tsu ThdThd
sfi_cs
sfi_ck
Write
Read
sfi_d[0..3]
sfi_d[0..3]
While the SFI I/F can operate at 1.8V or 3.3V, the following table describes the
timing of the above diagrams based on 3.3V operation.
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Electrical Specifications
11/18/201511/9/2015 57
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Table 24: Serial Flash SDR & DDR Timing (3.3V@15pF/30pF load)
Symbol Description
15pF 30pF
Min Max Min Max Units
fsfi_ck SDR
Serial Flash clock frequency
125 125 MHz
DDR 62.5 62.5 MHz
Tcsh Active hold time 2.97+(Tsfi_ck-8)/2
2.85+(Tsfi_ck-8)/2
ns
Tcss Active setup time 2.76+(Tsfi_ck-8)/2
2.75+(Tsfi_ck-8)/2
ns
Tcs CS High time 32 32 ns
Tv
SDR Clock to output Valid
(write)
-1.52 1.49 -2.21 1.57 ns
DDR Tsfi_ck/4- 1.52
Tsfi_ck/4+ 1.56
Tsfi_ck/4- 2.09
Tsfi_ck/4+ 1.61
ns
Tsu SDR Data in setup time
(read)
0.43 - 0.43 - ns
DDR 1.5 - 1.62 - ns
Thd SDR Data in hlod time
(read)
0.3 - 0.3 - ns
DDR 0.3 - 0.3 - ns
7.5.3 Serial i2c pin timing
Figure 11: I2C timing waveform
Table 25: I2C Interface Timing(Fast Mode Plus – 1Mbs)
Symbol Description Min Max Units
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Electrical Specifications
11/18/201511/9/2015 58
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
fsclk i2c_sclk clock frequency
0 1000 KHz
thd.sta Hold time START condition
0.26 - µs
tlow Low period of the i2c_sclk clock
0.5 - µs
thigh High period of the i2c_sclk clock
0.26 - µs
tsu.sta Set-up time START condition
0.26 - µs
thd.dat Data hold time 0 - us
tsu.dat Data set-up time 50 - ns
tr sda/sclk rise time - 120 ns
tf sda/sclk fall time - 120 ns
tsu.sto Set-up time for STOP condition
0.26 - µs
tbuf bus free time between stop and start
0.5 - µs
Cb Capacitive load for
i2c_sda and
i2c_sclk lines
550 pF
Because i2c_sclk and i2c_sda are open-drain-type outputs, with external pull-up, the
time i2c_sclk or i2c_sda takes to reach a high level depends on external signal
capacitance and pull-up resistor values. Recommended pull-up resistance values are
as follows:
7.5.4 RGMII Interface timing
The following diagrams describe the RGMII interface timing.
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Electrical Specifications
11/18/201511/9/2015 59
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Figure 12: RGMII TX timing
TxCLK
TxD[3:0],
TxCTRL
tns tps tns tps
Table 26: RGMII TX Timing
3.3V 1.8V
Symbol Description Min Max Min Max Units
tns negative skew -0.887 0 -1.057 0 ns
tps positive skew 0 1.345 0 1.607 ns
Note: JEDEC standard skew (+/-0.5nS ....) is not supported.
Figure 13: RGMII RX timing
rx_clk
rx_d[3:0]
rx_ctrl
Tsu ThlTsu Thl
Table 27: RGMII RX Timing
3.3V 1.8V
Symbol Description Min Max Min Max Units
Tsu Set-up Time 0.87 0.95 ns
Thl Hold Time 0.45 0.47 ns
7.5.5 Video Input Interface timing
All video-in input pins are sampled internally with pclk and synchronized to
EyeQ3® system clock. The following data relates to all video Input interfaces A, B
and C (via, vib and vic), for either 1.8V or 3.3V operation.
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Electrical Specifications
11/18/201511/9/2015 60
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Figure 14: Video Input Interface inputs timing
T1 T2
Tpclk
vid[15:0] (input)
vsync, hsync, field (inputs)
pclk
(input)
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Electrical Specifications
11/18/201511/9/2015 61
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Table 28: Video Input Interface timing
3.3V 1.8V
Symbol Description Min Max Min Max Units
Tpclk pclk period 10(2)
/5(1)
-
10(2)
/5(1)
- ns
Tmclk mclk period 10 1000 10 1000 ns
T1 Inputs (vid, vsync, hsync, field) setup time
1.85 1.89 ns
T2 Inputs (vid, vsync, hsync, field) hold time
0.25 0.30 ns
(1) When Histogram is disabled.
(2) When Histogram is enabled.
7.5.6 Video Output Interface
All video-out pins are outputs and change on the vopclk falling edge (according to the
P_pol parameter). The Video Output timing is based on an output load of 10pF, at
either 1.8V or 3.3V operation.
Figure 15: Video Output Interface outputs timing
T1T2
Tvopclk
vod[15:0] (output)
vovsync, vohsync, vode (outputs)
vopclk
(P_pol=1)
vopclk
(P_pol=0)
capture data
edgedata generation
edge
Table 29: Video Output Interface timing
3.3V 1.8V
Symbol Description Min Max Min Max Units
Tvopclk vopclk period 8 1000 8 1000 ns
T1 skew from clock (vsync, hsync, vode, vod[15:0])
1.15 1.55 ns
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Electrical Specifications
11/18/201511/9/2015 62
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
T2 skew from clock (vsync, hsync, vode, vod[15:0])
- 1.45 - 1.45 ns
Note: VoPCLK is defined as 250MHz/n where n>1.
7.5.7 PDtrace Interface timing
The PDT clock is divided down from the internally generated 320MHz clock to be
driven out of the chip at 160MHz. The PDtrace timing is based on an output load of
10pF.
Figure 16: PDTrace Timing Diagram
T1
T2 T2T3 T3
pdt_ck
pdt_d
Table 30: PDtrace timing (3.3V)
Symbol Description Min Max Units
T1 Pdt_ck phase duration
42.194 63.524 %
T2 skew between pdt_d to pdt_clk
- 0.672 ns
T3 skew between pdt_d to pdt_clk
- 0.487 ns
7.5.8 reseti-n pin timing
The reseti_n must be asserted true (low) for at least 1ms (at 30MHz). This is,
of course, after the OSC is stable after power-up which takes 3.4ms (i.e.,
following the deassertion of the POR_VDD – which was asserted for 3.4ms –
the reseti_n is to be asserted for 1ms). Note that the reseti_n signal goes
through a 1ms de-bounce circuit such that the SoC internals will not receive
reset until after 1ms of asserting reseti_n; furthermore, the internal reset signal
will not be deasserted until 1ms after the reseti_n line has been deasserted.
See figure below:
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Electrical Specifications
11/18/201511/9/2015 63
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
reseti_n (input)
reset_n (in SoC)
Note: for further information on reseti_n and its interaction with POR_VDD,
see section “88 ResetReset.”
7.5.9 DDR SDRAM AC Characteristics
The following Table provides the AC electrical characteristics for EyeQ3®
LPDDR2 interface
Table 31: LPDDR2 Interface AC Electrical Characteristics
Symbol Parameter/Condition Min. Nom. Max. Unit Notes
VIH(AC) Input logic threshold High VREF+0.22 V 2
VIL(AC) Input logic threshold Low VREF-0.22 V
SR Output driver slew rate 1.59 1.99 V/ns 1
FMAX Maximum operating frequency 500 MHz
DMAX Maximum operating data rate 1000 Mb/s
Notes:
1. Slew rate is an average value of rising and falling edges.
2. VREF refers to DDR_VREF
7.6 DDR SDRAM Timing Specification
The timing specification for the DDR SDRAM interface provided below at the
die and not at the pins.
Read, write and input setup and hold values are referenced to Vref.
Timing budgets are created by accounting for all skew, jitter and uncertainty
effects as well as specification requirements and subtracting them from the
initial Set Up and Hold time budgets. After all of the uncertainty contributors
have been subtracted, the margin that remains is the system set-up and hold
margin.
Figure 17: System Set-Up and Hold Uncertainties and Margin
Formatted: Font: 12 pt, ComplexScript Font: 12 pt
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Electrical Specifications
11/18/201511/9/2015 64
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
The components within a budget fall into three categories: transmitter
uncertainty, interconnect uncertainty and receiver uncertainty.
When EyeQ3 is the transmitter, the EyeQ3 Set-Up/Hold margin = System
Set-Up/Hold Margin + interconnect uncertainty (PCB) + receiver
uncertainty (LPDDR2).
When EyeQ3 is the receiver, the EyeQ3 Set-Up/Hold margin = System
Set-Up/Hold Margin + interconnect uncertainty (PCB) + transmitter
uncertainty (LPDDR2).
7.6.1 LPDDR2 Address/Command/Control timing specification
The Figure below provides the Command/Address/Control timing for EyeQ3®
LPDDR2 SDRAM interface.
Figure 18: LPDDR2 Command/Address/Control Timing Diagram
ddr_clk_n(n)ddr_clk(n)
tCLtCH
tOSCA
ddr_cs_n(n)
tOHCA
tOSCA
ddr_a(9:0)/
LP2_ddr_a(9:0)tOHCA
tOSCA tOHCA
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Electrical Specifications
11/18/201511/9/2015 65
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Table 32: LPDDR2 Command/Address/Control Timing Specifications
Symbol Parameter/Condition CK=2.5ns
(400MHz)
CK=2ns
(500MHz)
Unit Notes
Min. Max. Min. Max.
tCH Clock HIGH pulse width 0.46 0.54 0.46 0.54 tCK Duty cycle
tCL Clock LOW pulse width 0.46 0.54 0.46 0.54 tCK Duty cycle
tOSCA_typ Command/Address/Control output setup with respect to ddr_clk(n)
351 361 ps 1,2
tOHCA_typ Command/Address/Control output hold with respect to ddr_clk(n)
445 361 ps 2
tOSCA_fast Command/Address/Control output setup with respect to ddr_clk(n)
351 361 ps 1,2
tOHCA_fast Command/Address/Control output hold with respect to ddr_clk(n)
445 361 ps 2
tOSCA_slow Command/Address/Control output setup with respect to ddr_clk(n)
351 361 ps 1,2
tOHCA_slow Command/Address/Control output hold with respect to ddr_clk(n)
445 361 ps 2
Notes:
1. During an Address/Command/Control operation, the impact of
simultaneously switching outputs (SSO) is to cause noise on the I/O power
rail. It is assumed that SSO will account for 3.75% of a clock cycle.
2. EyeQ3 Set Up/Hold margin.
3. All timing specifications in this section are related to 50% duty cycle, and
do not include min/max duty cycle calculations, which should be taken in
account by simulation.
4. Since CKE and CS are changed only at rising edge of clock, uncertainty is
shorter with half clock cycle, so tCK/2 can be reduced from tCKCS and
tCKCKE.
5. CKE timing violations can be ignored since only change of CKE is done at
boot stage at low frequency ~30MHz.
6. Data eye training implemented at reading operation. It means that DQS
signal is shifted to the center of the valid data eye for each byte separately.
It is recommended to consider it at simulation configuration stage.
7.6.2 LPDDR2 write timing specification
The Figure below provides the write timing for EyeQ3® LPDDR2 SDRAM
interface.
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Electrical Specifications
11/18/201511/9/2015 66
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Figure 19: LPDDR2 Write Timing Diagram
ddr_clk_nddr_clk
ddr_dq
tDS tDH
ddr_dqs_nddr_dqs
ddr_dm
tCKDQS
tDS tDH
tDS tDHtDS tDH
Table 33: LPDDR2 Write Timing Specifications
Symbol Parameter/Condition CK=2.5ns
(400MHz)
CK=2ns
(500MHz)
Unit Notes
Min. Max. Min. Max.
tCKDQS ddr_dqs output rising with respect to ddr_clk output rising
-130 130 -215 215 ps
tDS_typ ddr_dq and ddr_dm output setup with respect to ddr_dqs output
351 361 ps 1,2
tDH_typ ddr_dq and ddr_dm output hold with respect to ddr_dqs output
445 361 ps 2
tDS_fast ddr_dq and ddr_dm output setup with respect to ddr_dqs output
351 361 ps 1,2
tDH_fast ddr_dq and ddr_dm output hold with respect to ddr_dqs output
445 361 ps 2
tDS_slow ddr_dq and ddr_dm output setup with respect to ddr_dqs output
351 361 ps 1,2
tDH_slow ddr_dq and ddr_dm output hold with respect to ddr_dqs output
445 361 ps 2
Notes:
1. During a Write operation, the impact of simultaneously switching outputs
(SSO) is to cause noise on the I/O power rail. It is assumed that SSO will
account for 3.75% of a clock cycle.
2. EyeQ3 setup/hold margin.
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Electrical Specifications
11/18/201511/9/2015 67
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
7.6.3 LPDDR2 read timing specification
The Figure below provides the read timing for EyeQ3® LPDDR2 SDRAM
interface.
Figure 20: LPDDR2 Read Timing Diagram
ddr_dq
ddr_clk_nddr_clk
ddr_dqs_nddr_dqs
ddr_dqs_nddr_dqs
(shifted)
90o Shift
tDISKEW(max)
CISKEW(min)
tDISKEW(min)
CISKEW(max)
Table 34: LPDDR2 Read Timing Specifications
Symbol Parameter/Condition CK=2.5ns
(400MHz)
CK=2ns
(500MHz)
Unit Notes
Min. Max. Min. Max.
tCISKEW_typ EyeQ3 internal skew between ddr_dqs and ddr_dq
-177 177 -123 123 ps 1,2
tCISKEW_fast EyeQ3 internal skew between ddr_dqs and ddr_dq
-177 177 -123 123 ps 1,2
tCISKEW_slow EyeQ3 internal skew between ddr_dqs and ddr_dq
-177 177 -123 123 ps 1,2
Notes:
1. tCISKEW represents the total amount of EyeQ3 internal skew consumed by
the PHY between ddr_dqs and any corresponding ddr_dq bit that will be
captured.
2. The amount of skew that can be tolerated from ddr_dqs to a corresponding
ddr_dq signal is called tDISKEW. This can be determined by the following
equation: tDISKEW = ± (T/4 – abs(tCISKEW)), where T is the clock period
and abs(tCISKEW) is the absolute value of tCISKEW.
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Reset
11/18/201511/9/2015 68
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
8. Reset
EyeQ3® has two external reset inputs:
Power On Reset (POR_VDD)
PushButton Reset (RESETI_N)
POR_VDD is the system reset and asserts low to place the system in a known state,
as defined by the “Reset State” pin descriptions, immediately upon assertion since
this signal functions as asynchronous reset. It should be noted that the internal MIPS
controller will not start until POR_VDD negation, at which point the mode bits are
latched into an internal register according to which MIPS0 boots. In addition, the
power ring settings are latched upon POR_VDD negation. POR_VDD must assert for
3.4ms after voltage inputs are stable.
RESETI_N is a “push-button” reset and asserts low to place the system in a known
state, as defined by the “Reset State” pin descriptions, following the 1ms debounce
time (see Sec. 7.5.87.5.8 reseti-n pin timing). The 1ms assertion is counted from the
deassertion of POR_VDD. Note: this signal is synchronous to the input clock and
thus will not assert until the clock is stable. When RESETI_N is negated, MIPS0 is
released from reset and boots according to the mode bits (previously latched upon
POR_VDD negation).
Both of these signals have the same effect on the system, whether they are asserted
together or independently, except in two cases:
SFI: When RESETI_N is asserted all SFI pins are tri-stated. When POR_VDD is
asserted all SFI pins are active (i.e., not tri-stated). If both are asserted together,
the pins are active.
GPIO: When RESETI_N is asserted all GPIO pins (i.e., pins configured as GPIO)
remain in their current state (i.e., RESETI_N does not affect their state). Pins
configured for their corresponding alternate function will be reconfigured to
GPIO functionality until RESETI_N is deasserted and SW reconfigures the
alternate function. When POR_VDD is asserted all GPIO pins are configured as
GPIO and are reset. If both are asserted together, all pins are reset. (If, for some
reason, there is a need to put the GPIOs in a reset configuration other than via
POR_VDD, this can be achieved via SW; e.g., RESETI_N will initiate a SW
routine to write "reset" values to the GPIO registers. Customers with this need
must request software specialization from Mobileye).
The following diagram describes the sequence of events as related to the reset
signals.
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Reset
11/18/201511/9/2015 69
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
1.8V
1.2V
SFI_D0***
OSC_EN****
EyeQ3 Power On Timing
OSC
POR_VDD
3.3V
3.4ms*
Valid Data
RESETI_N 1ms**
NOTES:* 3.4ms is OSC “Start Time” required till OSC provides stable clock (from the time 3.3V and 1.2V are stable and OSC_EN=1).** 1ms is needed to overcome debouncer*** SFI_D0 is pulled-up by a weak pull-up in order to enable the OSC**** OSC_EN (internal signal) is the LATCH output of the SFI_D0, the LATCH being controlled by the POR_VDD (pass through on low, latched on high)
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Boundary Scan (JTAG1149.1) Functions
11/18/201511/9/2015 70
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
9. Boundary Scan (JTAG1149.1) Functions EyeQ3® includes an IEEE 1149.1 boundary scan test port for board level testing. All
digital input, output, and input/output pins are accessible. The BSDL file is available
from Mobileye.
9.1 Boundary Scan Interface
This interface consists of five pins (TMS, TDI, TDO, NTRST, and TCK). It includes
a state machine, data register array, and instruction register.. Signals must be pulled-
up or down externally as needed.
9.2 State Machine
The TAP controller is a 5 state machine driven by the TCK and TMS pins. Upon reset
the TEST_LOGIC_RESET state is entered.
9.3 EyeQ3 TAP Controllers
There are 6 TAP controllers in EyeQ3. In normal mode (when testen = 0), 5 TAP
controllers are connected in daisy chain. They are:
1. MIPS Core0
2. MIPS Core1
3. MIPS Core2
4. MIPS Core3
5. MIPS Coherence Manager
In test mode (when testen = 1), only the System JTAG (which contains the BSR) is
connected.
9.4 MIPS JTAG Instruction Register
Please refer to MIPS EJTAG Spec.
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Boundary Scan (JTAG1149.1) Functions
11/18/201511/9/2015 71
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
9.5 System JTAG Instruction Register
After the state machine resets, the IDCODE instruction is always invoked. The
decode logic ensures the correct data flow to the data registers according to the
current instruction. Valid instructions are listed in table below (JTAG instructions).
Table 35: Supported JTAG Instructions of EyeQ3®
Name Code Description Mode Data Register
BYPASS 1111 Bypass Scan Normal Bypass
EXTEST 0000 External Test Test BSR
SAMPLE/PRELOAD 0011 Sample Boundary Test BSR
IDCODE 1110 ID Code Inspection Test ID REG
HIGHZ 0111 Force Float - put all scan pins in high-z
Test Bypass
CLAMP 0101 Clamp Test BSR
9.6 Boundary Scan Register (BSR)
Each Boundary Scan Register (BSR) cell has two stages. A flip-flop and a latch are
used for the serial shift stage and the parallel output stage. There are four modes of
operation as listed in below:
Mode Description
1 Capture 2 Shift 3 Update 4 System Function
9.6.1 Express and Normal BSRs
EyeQ3® has 2 BSRs: A normal one which includes all EyeQ3® functional IOs, and a
short BSR that includes only the Serial Flash port. The BSR accessed is selected
through a special control bit: TCRRES[228]=1 (for details please see the
“ExpressBoundaryScanMode” specification).
To initialize the express mode the following SVF script can be run: TRST ON; TRST OFF; ENDI R I DLE; ENDDR I DLE; STATE RESET I DLE; SI R 4 TDI ( 08) ; SDR 4 TDI ( 01) ; SI R 4 TDI ( 06) ; SDR 160 TDI ( 0000000000000000000000000000000000001000) ; ! Shi f t out TCRUSER. Check val ue agai ns t expect ed ( BI T 146 1) . SDR 160 TDI ( FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Boundary Scan (JTAG1149.1) Functions
11/18/201511/9/2015 72
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
TDO ( 0000000000000000000000000000000000004003) MASK ( FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF) ;
9.7 EyeQ3® Device ID Register
4 bit version number 0010
16 bit part number 0010001010101100
11-bit identity of the manufacturer 00000100000
Required by IEEE Std 1149.1 1
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Power-On Configurations
11/18/201511/9/2015 73
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
10. Power-On Configurations This section explains how to design the external hardware of the Power-On-Reset
(POR) function.
Some of the EyeQ3® balls should be connected to specific external logic as indicated
herein.
10.1 sfi_d0
A weak pull-up must be located on this ball.
10.2 sfi_d1 = mode1
A pull-down or pull-up should be located on this ball in order to set up the EyeQ3®
SFI data width mode. The mode bits are sampled ONLY when the POR pin is de-
asserted (i.e., on the rising edge). Mode1=0: SFI boots in single data mode
Mode1=1: SFI boots in quad data mode
10.3 sfi_d(2-3) = board version
This pins should be pulled-up or pulled-down externally to indicate the PCB version
number. These bits are sampled ONLY when the POR pin is de-asserted (i.e., on the
rising edge).
10.4 GPIO(8:2) = PowerMode (8:2)
A pull-down or pull-up should be located on this ball in order to establish the power
ring voltages (i.e., rings 8 thru 2, respectively) to either 1.8V or 3.3V IO. The mode
bits are sampled ONLY when the POR pin is de-asserted (i.e., on the rising edge).
0: the I/Os power supply is 1.8V
1: the I/Os power supply is 3.3V
To determine which IOs reside in which power ring, see the respective IO Table
describing the IO in question.
Note1: GPIO(8:2) reside on Power Ring 7 which is controlled by GPIO(7). As such,
if GPIO(7)=0, Ring7 IOs are configured for 1.8V operation; consequently, all the
powermode pins must use 1.8V. So, for example, if one wanted to use Ring2 at 3.3V,
GPIO(2) must be pulled up to 1.8V; conversely, if one wanted to use Ring2 at 1.8V,
GPIO(2) must be pulled down to GND. Furthermore, for the sake of clarity, if Ring7
was configured for 3.3V operation (i.e., GPIO[7]=1 by being connected to 3.3V), then
all powermode pins (i.e., GPIO[2:8]) must use 3.3V or GND for configuration.
Note2: The IO cell does have built-in protection circuitry to insure that no physical
damage will occur if the wrong configuration is applied (i.e., rail voltage doesn’t
match configuration bits) – this, of course, assumes that the rail voltage and the
logical IO pin voltage match. Nevertheless, if the configuration bits do not
appropriately reflect the applied rail voltage, the performance of the IO cell is not
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Power-On Configurations
11/18/201511/9/2015 74
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
guaranteed. Furthermore, such a mismatch must be corrected as soon as possible and
not persist during normal operation.
10.5 por_vdd – Power On Reset
Used as input for external asynchronous Reset during power on. The por_vdd should
be kept asserted (low) until after all EyeQ3® power supplies are stable for 3.4ms.
That is, since the internal OSC has a 3.4ms startup time therefore if the OSC is being
used the por_vdd must be held 3.4ms.
10.6 ntrst_n –JTAG Reset
There is a pull-down on ntrst_n, so leaving it unconnected will keep the TAPs in reset
state. The ntrst_n should be asserted after all EyeQ3® power supplies are on for at
least 1µs.
10.7 clk_in and clk_out
The following diagram illustrates the crystal oscillator hookup.
Figure 21: Application diagram of the crystal oscillator
clk_in clk_out
CA=5pF CB=5pF
Rfd=909K
sfi_d0
* The crystal oscillator used to provide the 30MHz must be precisely
30.000000MHz (+/-100ppm).
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Power-On Configurations
11/18/201511/9/2015 75
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
The values of the capacitors and resistors should be calculated based on the
recommendations of the specific crystal oscillator used which must take into account
conditions such as PCB materials and trace lengths. Note: components should be
placed as close as possible to the EyeQ3® oscillator pin inputs.
It should be noted that since the clk_in and clk_out pins are analog signals dependent
on the attendant circuitry, no voltage value can be provided.
The crystal must support the following conditions:
Drive Level ≥ 100uW
CO (shunt capacitance, including parasitics) < 6PF
CA = CB = 5pF
CL = 8pF
ESR ≤ 50 Ohm
The following parts are approved for general use, however ONLY the Jauch part
support the automotive temperature range (-40C to +105C).
SUNTSU_SCQ
EPSON_FA20H
JAUCH_JXS22
EyeQ3™ Data SheetEyeQ3™ Data Sheet
External Connection Examples
11/18/201511/9/2015 76
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
11. External Connection Examples
11.1 DDR-SDRAM
11.1.1 DDR supported
Examples:
Micron - MT42L32M32D2AC-25 AAT
Winbond – W97AH2KBVA1K/2K
ISSI - IS46LD32320A2
The common EyeQ3® configurations are as follows:
1. Two 32-bit data width LPDDR2 devices.
2. Single 32-bit data width LPDDR2 device.
Figure 22: Two 32-bit data width LPDDR2 devices interface
EyeQ3ddr_a[9:0]
ddr_ck[0]
ddr_ck_n[0]
ddr_cke[0]
ddr_cs_n[0]
ddr_dm[3:0]
ddr_dq[31:0]
ddr_dqs[3:0]
ddr_dqs_n[3:0]
CA[9:0]
CK
CK#
CKE
CS#
DM[3:0]
DQ[31:0]
DQS[3:0]
DQS#[3:0]
ddr_a[14:10]/ddr_a[4:0]*
ddr_ck[1]
ddr_ck_n[1]
ddr_cke[1]
ddr_cs_n[1]
ddr_dm[7:4]
ddr_dq[63:32]
ddr_dqs[7:4]
ddr_dqs_n[7:4]
ddr_ba[2:0]/ddr_a[7:5]*
ddr_ras_n/ddr_a[8]*
ddr_cas_n/ddr_a[9]*CA[9:0]
CK
CK#
CKE
CS#
DM[3:0]
DQ[31:0]
DQS[3:0]
DQS#[3:0]
ddr_zq
ddr_retention_n
gpio
ddr_ato
ddr_dto[1:0]
240Ω
LPDDR2
(32bit)
LPDDR2
(32bit)
* Secondary use of IOs
Note: Please note that the low word LPPDR2 device’s lane #0 data (DQ[0:7]) must be
connected to EyeQ3 lane #0 (DDR_DQ[0:7]) – though the data within this lane can be
swapped for layout considerations. The other three lanes of the low word LPDDR2 device
can be swapped as desired; similarly the four lanes of the high word LPDDR2 device can be
EyeQ3™ Data SheetEyeQ3™ Data Sheet
External Connection Examples
11/18/201511/9/2015 77
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
swapped to ease the layout. (For further information on lane swapping constraints see the
BootSWparameters document).
Figure 23: Single 32-bit data width LPDDR2 device interface
EyeQ3ddr_a[9:0]
ddr_ck[0]
ddr_ck_n[0]
ddr_cke[0]
ddr_cs_n[0]
ddr_dm[3:0]
ddr_dq[31:0]
ddr_dqs[3:0]
ddr_dqs_n[3:0]
LPDDR2
(32bit)
CA[9:0]
CK
CK#
CKE
CS#
DM[3:0]
DQ[31:0]
DQS[3:0]
DQS#[3:0]
ddr_zq
ddr_retention_n
gpio
ddr_ato
ddr_dto[1:0]
240Ω
11.2 Flash memory
11.2.1 Serial flashes supported
The Serial Flash Interface implements the standard SPI protocol for serial flashes up
to 1Gbit (128MB).
Examples:
Micron: N25Q256A
Spansion: S25FL256S
Winbond: W25Q128B
Example of serial flash connection:
EyeQ3™ Data SheetEyeQ3™ Data Sheet
External Connection Examples
11/18/201511/9/2015 78
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
EYEQ3
S25FL256S
SFI_D0
SFI_D1
SFI_D2
SFI_D3
SFI_CLK
SFI_CS0
SFI_CS2
SFI_CS1
SI/IO0
SO/IO1
WP#/IO2
HOLD#/IO0
SCK
CS
N25Q256A
DQ0
DQ1
Vpp/W#/DQ2
HOLD#/DQ3
C
S#
Maximum clock rates (MHz) as a function of load and mode:
Mode SDR DDR
Load 10pF 30pF 10pF 30pF
Micron-N25Q256A 107.14 93.75 53.57 46.88
Spansion-S25FL256S 93.75 93.75 62.5 53.57
11.3 Image sensor connection
Figure 31: Interface with Aptina Image Sensor
EyeQ3™ Data SheetEyeQ3™ Data Sheet
External Connection Examples
11/18/201511/9/2015 79
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
via_d(15:4)
via_d(3:0)
via_pclk
via_vsync
via_hsync
via_field
via_mclk
Mobileye
EyeQ3
*
* leave unconnected
*
*
Aptina
PIXCLK
FRAME_VALID
LINE_VALID
DOUT(11:0)
OEn
RESETOnRESETn
SCLK
SDATA
SCL
SDA
SADDR
GND
VCC
NC
4K7
EXTCLK
TRIGGER
STANDBY
TEST
27MHz
4K7
Pull-Up | Pull-Down
FLASH*
NOTE: It is critical to insure that the image sensor is placed right-side up and not
upside down. When looking at the image sensor input array, pin A1 should be on the
lower right hand side. If the sensor is not connected with this orientation, not all
video grabbing options will be supported.
NOTE: It is recommended to employ a low noise LDO to drive the image sensor with
2.8V AVCC and 1.8V DVCC – 300mA.
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Chip Package Data
11/18/201511/9/2015 80
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
12. Chip Package Data The EyeQ3 is packaged in an FCTEBGA (Flip Chip Thermal Enhanced Ball Grid Array) of 529
balls. EyeQ3 package solder ball material is SAC305 (SnAgCu alloy composition). EyeQ3’s PCB
CTE (coefficient of thermal expansion) overall is in a range of 12~13 E-6/°C.
12.1 Mechanical Data
The following table shows the “Databook” values which are the final values to be
used for PCB design.
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Chip Package Data
11/18/201511/9/2015 81
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Chip Package Data
11/18/201511/9/2015 82
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Chip Package Data
11/18/201511/9/2015 83
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Chip Package Data
11/18/201511/9/2015 84
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Chip Package Data
11/18/201511/9/2015 85
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Chip Package Data
11/18/201511/9/2015 86
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Chip Package Data
11/18/201511/9/2015 87
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
12.2 Package Thermal Data
12.2.1 Operational Thermal Data
Theta Ja is the thermal resistance between the junction and the under air velocity 0, 1,
2 m/s are listed in the table below.
Theta Jc is the thermal resistance between the junction and package coverage.
Theta Jb is the thermal resistance between the junction and the package bottom.
The following table shows the Thermal data:
Table 36: Package Thermal Data
Air velocity
(m/s)
Theta Ja
(oC/W)
PsiJt
(oC/W)v
Theta Jc
(oC/W)
Theta Jb
(oC/W)
0 16.71 0.94 1.25 8.04
1 14.39 0.95 1.25 8.04
2.5 13.26 0.96 1.25 8.04
Note 1: The above values have been determined by simulation of a 1S2P JEDEC
board. As those values strictly depend on the PCB on which the component is
mounted, their values must be assessed through Thermal simulations. Mobileye can
provide the FlowTherm model upon request.
EyeQ3 operation is guaranteed from -40C to +125C junction temperature.
The following equations can be used to calculate the relevant temperatures:
(a) ambient temperature: Ta = Tj - (ThetaJa * Power)
(b) pcb bottom temperature: Tb = Tj – (ThetaJb * Power)
(c) pcb top temperature: Tc = Tj - (ThetaJc * Power)
For Power=2W and maximum Tj of 125C, then:
(a) ambient temperature: 125 - (16.71 * 2) => 91.58C
(b) pcb bottom temperature: 125 - (8.04 * 2) => 108.92C
(c) pcb top temperature: 125 - (1.25 * 2) => 122.5C
note: the above calculations are without considering a heat sink.
12.2.2 Package Related Temperature Data
Table 37: Package Temperature ratings
Parameter Minimum Maximum Units
Storage temperature -55 150 Co
Leaded Solder reflow temperature - 225 Co
LeadFree Solder reflow temperature - 245 Co
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Chip Package Data
11/18/201511/9/2015 88
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
12.3 Package Solder Mask
Shown above is the solder mask of the EyeQ3 FBGA substrate which is SMD
(solder mask defined). As shown below, it is recommended that the PCB be NSMD
(non-solder mask defined) and use a ball pad (mask opening) equal to the solder
mask opening of the FBGA (i.e., 0.420mm ±0.030mm); and use an additional 0.10-
0.15mm to define the solder mask opening on the PCB (i.e., 0.520-0.57mm).
Exposed Ball Pad
NSMD – PCB
Solder Masked Ball Pad
Solder Masked Substrate
SMD – EyeQ3
Exposed Ball Pad
NON Solder Masked Substrate
Solder Masked Substrate
(1) Solder Mask Opening
(2) Ball Pad Diameter
(4) Ball Pad Diameter
(3) Solder Mask Opening
(1) EyeQ3 solder mask opening –the exposed ball pad diameter : 0.42mm +/- 0.03mm
(2) EyeQ3 ball pad diameter – partly covered by solder mask: 0.52mm
(3) PCB solder mask opening –includes exposed board substrate in addition to the ball pad
diameter : 0.52mm min 0.57mm max
(4) PCB ball pad diameter –where the ball is soldered : 0.42mm
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Special Considerations and Checklist
11/18/201511/9/2015 89
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
13. Special Considerations and Checklist
13.1 Power considerations
TBD
13.2 PCB considerations
13.2.1 DDR Routing Considerations for Good Signal Integrity
13.2.1.1 Routing Priority
Signals should be routed based on the relative tightness of the skew budgets. In
order of priority:
1. The double data rate signals (DQ, DM, DQS/DQS#) should be routed first
since these have the strictest budgets: ¼ of a clock period available for set-
up or hold relative to the differential strobe.
2. Differential clock (CK/CK#) and single data rate signals, as well as Control
signals have looser budgets with ½ of a clock period for set-up and hold.
3. Rising edges of all differential DQS/DQS# signals are within ¼ of a clock
period of the rising edge of the differential clock, CK/CK#.
4. Route all Vref and support signals (debug).
13.2.1.2 Skew Control
How tightly skew needs to be controlled on the PCB depends on the maximum
operating frequency of the interface. The following table lists skew
recommendations for double data rate and single data rate domains for various
operating frequencies. Recommended PCB skew for CK to DQS timing for
different bit rates is also included. Skew in picoseconds is translated to
physical length for microstrip and stripline cases. Assumptions are 151 ps/inch
for top layer microstrip (air in cross section) and 179 ps/inch for stripline or
embedded microstrip (no air in cross section).
EyeQ3™ Data SheetEyeQ3™ Data Sheet
Special Considerations and Checklist
11/18/201511/9/2015 90
Formatted: Font: Bold, Complex ScriptFont: Bold
Formatted: Font: Bold, Complex ScriptFont: Bold, Superscript
Formatted: Font: Bold, Complex ScriptFont: Bold
Table 38: Recommended Skew Budgets
800Mbps 1066Mbps
DQ to DQS Domain Skew in ps. 25 18
Skew in Inches of Microstrip 0.17 0.12
Skew in Inches of Stripline 0.14 0.10
Addr/Cmd to CK/CK# Domain Skew in ps. 50 37
Skew in Inches of Microstrip 0.33 0.25
Skew in Inches of Stripline 0.28 0.21
DQS to CK Skew in ps. 188 141
Skew in Inches of Microstrip 1.25 0.94
Skew in Inches of Stripline 1.04 0.78
13.2.1.3 Vias and Layer Changes
Any via that attaches to a trace will change the delay of that trace. In order to
preserve a tight skew relationship, all signals within a byte lane should have
the same number of vias and layer changes. This will help to insure that data
signals, along with the accompanying strobe, will see the same effective delay.
13.2.1.4 Serpentine Traces
In order to match lengths within a byte lane, delay must be added to some
traces to match the longest length. This is often done with serpentine routing.
Care must be taken, as coupling between parallel portions of a serpentine can
excite crosstalk in the adjacent parallel section, effectively causing the signal
to arrive at the far end of the net earlier than desired. Essentially, coupling will
cause a portion of the signal to travel orthogonal to the trace in the coupled
regions causing the signal to arrive early.
Stripline vs. Microstrip
Propagation times are shorter in microstrips than in striplines. Consequently,
the mechanical length in a microstrip will need to be longer than the
mechanical length in a stripline in order to achieve the same propagation delay.
For this reason, all signals within a single byte of the DQ-DQS domain should
be routed in the same substrate configuration, i.e. all in a microstrip or all in a
stripline. Similarly, each path in the byte lane should have the same number of
vias and layer transitions. All paths within a byte lane should be as similar as
possible. Deviations from these rules should be simulated in order to determine
how best to compensate for any difference.
The same rules apply to the address/command bus since this interface uses
double data rate signaling as well.