faculty of applied science an:p engineering examiners: p...

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UNIVERSITY OF TORONTO FACULTY OF APPLIED SCIENCE AN:p ENGINEERING

ECE241F - Digital Syst~ms Final Examination

December 19, 2017, 2:00pm-4:30pm Duration: 2.5 hours

Examiners: P. Anderson, P. Chow and B. Wang

Exam Type D: Examiner specified aids: One single sheet of letter size paper (8.5 x 11 inch), both sides may be used.

Calculator Type 4: No calculators or other electronic devices are allowed.

All questions are to be answered on the examination paper. There are two extra pages at the end and you may use the back of a page. If you use more than the given space, please direct the marker to the appropriate page and indicate clearly on that page which question(s) you are answering there. It is your responsibility to make sure the marker can find your solution.

The number of marks for each question are indicated.

The examination has 23 pages, including this one.

Last Name: ____________ _ First Name: ____________ _

Student Number: ___________ _ UTORID: __________ _

MARKS

1 2 ·3 4 5 6 7 8 9 10 11 Total

/13 /7 /15 /10 /6 /5 /5 /10 /6 /15 /18 /110

Question 1 [13 Marks]

(a) [6 Marks] For the logic function, f (a, b, c, d) = L m (3, 6, 8, 10, 14) + D (2, 7, 11) as shown by the Kamaugh map given below.

ab cd 00 01 1 1 10

. ·1 1 00 0 0 I 0 .

' "' ..

01 0 0 0 0 -- . . ·- ..

11 1 ' X 0 X

; .. i---·--r--- ... ·4··-··

! 10 X : 1 , 1 1

; ;

(i) [ 4 Marks] Determine the minimal cost logic expressions in both SOP and POS forms.

SOP form:

POS form:

(ii) [2 Marks] Based on the appropriate minimal cost logic expression, draw a NOR-gate circuit to implement the logic function and give its cost. Cost is defined as the sum of the total number of gates plus the total number of inputs. You can assume that both the inverted and the non-inverted literals are availc_ble.

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Question 1 continued ...

(b) [7 Marks] For the logic function, f = abd +ca+ cd

(i) [4 Marks] Implement the logic function using only 2-to-1 multiplexers by completing the partial circuit given below. Use as few multiplexers as possible. Only the true form of the literals are available.

(ii)

a

0

1

[3 Marks] Implement the logic function using only 3-input LUTs. Use as few as possible. Your LUTs are organized as shown, with 12 being the most significant bit of the input. Draw the programming bits of the LUT inside the box with the bit for input (12,Il,IO) = (0,0,0) at the top.

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f

12=[} M f

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You are given a FSM state table as shown below. Reduce the number of states as much as possible. Draw a new reduced state table using S1, S2 ... as state names in your table.

Current

State Next State Output

x=0 x=l z

A D B 0

B F E 1

C D G 0

D C F 0

E F B 1

F E C 1

G F G 1

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Question 3 [ 15 Marks]

For both parts of this question, assume that the propagation delay though each gate is 2 + 0.1 x (Number of Inputs) ns and that all inputs to the adder (xi, Yi and c0) arrive at the same time.

(a) [5 Marks] An 8-bit ripple-carry adder is built using logic gates as illustrated below. How long does it take to compute the 9-bit sum? Show how you arrive at your answer, and be sure to identify the critical path.

Cg C7 Cs C4 C3 Cz -C1 Co FA FA FA FA FA FA FA FA

Sg S5 S2 So

5

. Question 3 continued ...

(b) [10 Marks] A partial 8-bit look-ahead adder is shown below. Write down the expressions for the bits,.c2 and c3 and draw the logic. circuit for c2 and c2 in the space below. Determine the time required to compute the 9-bit sum using this look-ahead adder. Show how you arrive at your answer.

X2 Y2 Xo Yo

FA FA FA FA

Co

P2 Po 52 So

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This is a sequential circuit with two inputs, a, b and one output, z. The circuit consists of combinational logic and one bit of memory (i.e. one flip-flop). The output of the flip-flop has been made observable through the output "state".

elk

a

b

state

z

(a) [6 Marks] Fill in the truth table and determine the next state and the output logic functions.

a b state next state z

(b) [4 Marks] Implement the circuit by completing the Verilog code below.

module top_module input elk, a, b, output reg state, output z

) ;

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The partial CMOS circuit (pull-up network) given below is supposed to implement a logic function, f . Complete the. pull-down network directly .on the circuit .diagram below assuming only the un

complemented forms of the inputs are available (i.e. w, x, y and z). Also, determine the logic function · .realized. You do not need to simplify the logic expression.

z -<t X "1

w 4

y "1 z-C

---------- f

f=

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Question 6 [5 Marks] Number Conversions

Complete the table doing the necessary conversions. Assume the number of bits (n) for the binary number

formats is 6. The first row is done for you:

Decimal 2's Complement Sign/magnitude

10 001010 001010

-10

173

-1

110011

110011

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.Question 7 [5 Marks] Multipliers

.. One is often multiplying by .10 ( decimal). Construct the circuit for an unsigned multiplier that multiplies

·an 8-bit input A by IO· (decimal) using the:conventional array oultiplier method you saw in class. Do not

include any unnecessary logic such as for multiplication by zero.

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Question 8 [ 10 Marks]

An FSM can be built using a memory as shown in the circuit below.

1 RO bit O (least significant bit}

DO LO AO D1 A1

D2 A2 -------· --· --

D3 5, 04 -----·--·-----

RO 05 06

Memory 07 08 09

RESET 5 5,

Clock s,el

REG DIN

RESET Clock

(a) [2 Mark] Fill in the table below with "DO" to "D9" (the first line is answered for you)

The bit that controls the loading of RO DO The bit that controls the function of the adder (add= 1 r A+Bl, add= 0 rA-Bl) The bits from the memory into one side of the adder The bit that controls the input into the other side of the adder The bits that, on the clock edge, will form part of the next memory address

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(b) [2 Mark] In the space below, put in the bit pattern that will cause 7 to be added to DIN and stored in

.RO on the clock edge. Put a "d" in for "don't care" bits.

( c) [2 Mark] The "next address" of memory is the "next state" of the FSM. What will be the effect of

RO bit O on the address of the memory? Describe this in an if-then-else statement

(d) [4 Marks] Assume that the circuit starts by asserting RESET for one clock cycle to force all register

outputs to be set to O and then begins a sequence of operations determined by the program in the

memory. Show the memory contents that will cause DIN to be stored in RO and then adds 1 to RO if

the value stored was odd. You do not need to worry about any further steps. You may not need all the lines in the table. There is a second copy of the table below - indicate which is to be marked if

they are both used.

Address D9 D8 D7

000

001

010

011

Address D9 D8 D7

000

001

010

011

I I 11. I __

I

I I I I

D5 D4 D3 D2 DO

i I I I I I I I

D5 D4 D3 D2 I Dl I DO

I I I I

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The circuit shown has the following characteristics:

D Q 01 D Q t Clock_to_ Q lns A B

tsetup 0.5ns Clock

thold 0.8ns

oz 3ns oc oc 0ns

(a) [2 Marks] Define setup (tsetup) and hold time (thold) and explain what can happen if these times are not properly observed.

(b) [2 Marks] For the given circuit to operate correctly, what is the maximum frequency for the Clock? You may express the answer as a fraction, i.e., no need to complete the calculation.

Maximum frequency = '-I _______________ _,

(c) [2 Marks] Now assume that 00 = 0.3ns. For the given circuit to operate correctly, what is the maximum frequency for the Clock? You may express the answer as a fraction, i.e., no need to complete the calculation.

Maximum frequency = '-I _______________ _,

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For each of the following code sequences, draw the circuit that will result, or if the circuit will cause an error, explain the error. You may use symbols such as flip flops, latches, multiplexers, gates, etc. to draw your circuits.

(a) [3 Marks]

module circuitA ( input d, input ena, output reg q) ;

always©(*) if (ena)

q = d;

endmodule

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(b) [3 Marks]

module circuitB ( input elk, input resetn, input in, output out);

// synchronous reset

reg [3:0] q;

always ©(posedge elk) if ( ! resetn)

else q <= O;

begin

end

q[O] <= q[1]; q[3] <= in; q[1] <= q[2]; q[2] <= q[3];

assign out= q[O];

end.module

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(c) [3 Marks]

module circuitC ( .input elk, input resetn, //· synchronous reset input in, output out);

reg [3:0] q;


else q <= O;

begin

end

q[3] =

q[2]

q[1]

q[O] =

assign out= q[O];

endmodule

in; q[3]; q[2];

q[1];

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( d) [3 Marks]

module circuitD ( input elk, input resetn, input in, output out);


reg [3:0] q;


else q <= O;

begin

end

q[O] = q[1]; q[1]=q[2]; q[2] = q[3]; q[3] = in;

assign out= q[O];

end.module

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(e) [3 Marks]

module circuitE ( input elk, input resetn, input in, output out);


reg [3: OJ q;

always @(posedge elk) if ( ! resetn)

begin

else

q[O] <= O; q[3] <= O;

end

begin q[O] <= q[1]; q[3] <= in;

end

always @(posedge elk) if ( ! resetn)

q[2: 1] <= 0;

else begin

q[l] <= q[2]; q[2] <= q[3];

end

assign out= q[O]; end.module

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(a) [3 Marks] The figure below is the schematic symbol for a 16-bit register with a synchronous Reset and a Load Enable. The register loads the value at D when En is high. Write a Verilog module for this register.

Reset D1s-o

En Register

01s-0

(b) [2 Marks] If you are using a 50MHz clock, how many clock pulses must you count for a period of 1 second? What is the minimum number of bits you would need in your counter?

Number of Clock Pulses =

Minimum Number of bits in counter=

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(c) [3 Marks] The figure below is a schematic symbol for a parallel load counter with a Load Enable. When Load Enable is high on a rising cbck edge, the D inputs are loaded into the counter. If Load Enable is low, the counter counts down on every rising clock edge. Assuming that the clock runs at 50 Mhz, write a Verilog module for this counter so that it can count for at least 1 second.

Load Enable 0

Counter

Q

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(d) [5 Marks] A sensor on a wheel axle outputs the speed of the wheel as a 16-bit value, where 0 means the wheel is stopped and the maximum value corresponds to the maximum speed of the wheel. Your task is to sample the speed of the wheel constantly at 1 second intervals, store the value in a register and set a flag, called READY, to indicate when a new value is available. The READY signal stays high until a signal called GOTIT, which comes from another circuit, is pulsed high for one cycle. If the GOTIT signal has not been received when it is time to take another sample, then no new sample is taken for that time and the value currently in the register is held. You are given a 50 MHz system clock.

Draw the schematic for your circuit. If you use an FSM in the schematic, just draw a box that says FSM showing the inputs and outputs to the FSM, but give the state diagram for the FSM separately. You may use the register and counter from Parts (a) and (c) and any other _gates that you require.

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(e) [5 Marks] Write the Verilog module that corresponds to your schematic in Part (d). You do not need to.rewrite the register and counter modules from Parts (a) and (c) here.

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