nAmIB I A U n IVERS ITY OF SCIEnCE AnD TECHnOLOGY

FACULTY OF COMPUTING AND INFORMATICS

DEPARTMENT OF COMPUTER SCIENCE

QUALIFICATION: BACHELOR OF COMPUTER SCIENCE

QUALIFICATION CODE: 07BACS LEVEL: 5

COURSE: COMPUTER ORGANISATION AND ARCHITECTURE COURSE CODE: COA511S

DATE: JULY 2016 SESSION: THEORY

DURATION: 2 HOURS MARKS: 100

SECOND OPPORTUNITY EXAMINATION QUESTION PAPER

EXAMINER(S)

MODERATOR:

MR. A.M. GAMUNDANI

DR. F. BHUNU SHAVA

THIS QUESTION PAPER CONSISTS OF 3 PAGES

(Excluding this front page)

INSTRUCTIONS

1. Answer ALL the questions.

2. Write clearly and neatly.

3. Number the answers clearly.

PERMISSIBLE MATERIALS

1. Scientific Calculator

Section A: [10 Marks] -Answer All Questions. Each Question Weighs 1 Mark.

[1].Combinational circuits are often referred to as "memoryless" circuits because their output depends only on their current input and no history of prior inputs is retained. [True/ False]

[2].A branch can be either forward or backward. [True/False]

[3]. The principal price to pay for variable-length instructions is an increase in the complexity of the processor. [True/False]

[4]. The exception modes have full access to system resources and can change modes freely.[True/False]

[5]. Microprogramming eases the task of designing and implementing the control unit and provides support for the family concept.[True/False]

[G].In a traditional scalar organization there is a single pipelined functional unit for integer operations and one for floating-point operations. [True/False]

[7].An attractive feature of an SMP is that the existence of multiple processors is transparent to the user. [True/False]

[8]. The demand on power requirements has not grown as chip density and clock frequency have risen. [True/False]

[9].A kernel typically will have few to no branching statements.[True/False]

[10]. The sequence of instruction cycles are always the same as the written sequence of instructions that make up the program. [True/False]

Section B: [15 Marks]- Answer All Questions. Each Question Weighs 1 Mark.

[1]. The essence of the approach is the ability to execute instructions independently and concurrently in different pipelines. A. Scalar B. Branch C. Superscalar D. Flow dependency

[2]. Vector and array processors fall into the ____ category of computer systems. A. SIMD B. SISD C. MISD D. MIMD

[3]. One way to control power density is to use more of the chip area for ___ _ A. Multicore B. Cache memory C. Silicon D. Resistors

[4]. The parallel code in the form of a function to be run on GPU is the ___ _ A. Grid B. Thread C. Kernel D. None of all these

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[5]. The ____ is connected to the address lines of the system bus. A. MBR B. MAR C. PC D. IR

[G). A _____ system is a set of interrelated subsystems. A. Secondary B. Hierarchical C. Complex D. Functional

[7].A(n) _____ Mean is a good candidate for comparing the execution time performance of several systems. A. Composite C. Harmonic

B. Arithmetic D. Evaluation

[8]. The _____ are used to designate the source or destination of the data on the data bus. A. System lines B. Data lines C. Control lines D. Address lines

[9].A line includes a ____ that identifies which particular block is currently being stored. A. Cache B. Hit C. Tag D. Locality

[10]. With the data transfer is synchronized to both the rising and falling edge ofthe clock, rather than just the rising edge. A. CDRAM B. SDRAM C. DDR-DRAM D. RDRAM

[11]. _____ is the standardized scheme for multiple-disk database design. A. RAID C. CLV

B. CAV D. SSD

[12]. The Thunderbolt protocol layer is responsible for link maintenance including hot-plug detection and data encoding to provide highly efficient data transfer. A. Cable B. Application C. Common transport D. Physical

[13]. With the virtual address is the same as the physical address. A. Unsegmented unpaged memory B. Unsegmented paged memory C. Segmented unpaged memory D. Segmented paged memory

[14]. In the number 472.156 the 2 is the ___ _ A. Most significant digit B. Radix point C. Least significant digit D. None of all these

[15]. _____ means that the number is too small to be represented and it may be reported as 0. A. Negative underflow C. Positive underflow

B. Exponent underflow D. Significand underflow

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Section C [75 Marks]: Answer All Questions.

Questionl

(a} Briefly explain the distinction between computer organization and computer architecture?

(b) Describe the mapping functions used in implementing cache memory.

(c) Give reasons why peripherals are usually not connected to the system bus. (d) Define an Instruction set Architecture (ISA) (e) What is the difference between an address bus and a data bus?

Question 2

[4 Marks]

[6 Marks] [4 Marks] [2 Marks] [4 Marks]

(a} Explain the three 1/0 operation techniques. [6 Marks] (b) Evaluate the following decimal integer computations, using the two's compliment, represent your answers an binary numbers

(i) (-8) + 4 (ii) 3 -8

(c) Which two rules did you apply in solving b (i} and b (ii} respectively? (d) Explain any two major functions of an 1/0 Module.

(e) Distinguish between Hardware and Software speculation mechanisms.

Question 3

(a} Identify and explain any four bus design considerations.

[2 Marks] [2 Marks] [2 Marks] [4 Marks]

[4 Marks]

[8 Marks] (b) You want to improve performance of a system's memory. Describe how the following may affect performance.

(i) Size of cache

(ii) Size of main memory (c) Explain how interrupts in bus arbitration are handled. (d) What is the purpose of swapping in operating system functionality?

Question 4

[2 Marks] [2 Marks] [6 Marks] [2 Marks]

(a} Suppose three values (x, y and z) are stored in a machine's memory. Describe the sequence of events (loading registers from memory, saving values in memory, and so on) that lead to the computation of x + y +z. [8 Marks]

(b) Explain the distinction between Instruction level parallelism and Machine parallelism. [4 Marks] (c) Demonstrate the two's compliment operation using (-14), (a signed decimal integer). [3 Marks]

*****END OF EXAMINATION PAPER*****

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