fakultät für informatik informatik 12 technische universität dortmund embedded system hardware -...
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fakultät für informatikinformatik 12
technische universität dortmund
Embedded System Hardware
- Reconfigurable Hardware -
Peter MarwedelInformatik 12TU Dortmund
Germany
2008/11/15
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- 2 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Energy Efficiency of FPGAs
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- 3 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Reconfigurable Logic
Full custom chips may be too expensive, software too slow.Combine the speed of HW with the flexibility of SW
HW with programmable functions and interconnect. Use of configurable hardware;
common form: field programmable gate arrays (FPGAs)Applications: bit-oriented algorithms like
encryption, fast “object recognition“ (medical and military) Adapting mobile phones to different standards.
Very popular devices from XILINX (XILINX Vertex II are recent devices) Actel, Altera and others
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- 4 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Floor-plan of VIRTEX II FPGAs
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- 5 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Virtex II Configurable Logic Block (CLB)
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- 6 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Virtex II Slice (simplified)
Look-up tables LUT F and G can be used to compute any Boolean function of 4 variables.
a b c d G0 0 0 0 00 0 0 1 10 0 1 0 10 0 1 1 00 1 0 0 10 1 0 1 00 1 1 0 00 1 1 1 11 0 0 0 11 0 0 1 01 0 1 0 01 0 1 1 11 1 0 0 01 1 0 1 11 1 1 0 11 1 1 1 0
Example:
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- 7 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Virtex II (Pro) Slice
[© and source: Xilinx Inc.: Virtex-II Pro™ Platform FPGAs: Functional Description, Sept. 2002, //www.xilinx.com]
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- 8 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Number of resourcesavailable in Virtex II Pro devices
[© and source: Xilinx Inc.: Virtex-II Pro™ Platform FPGAs: Functional Description, Sept. 2002, //www.xilinx.com]
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- 9 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
InterconnectH
iera
rchi
cal R
outin
g R
esou
rces
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- 10 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Virtex II Pro Devices includeup to 4 PowerPC processor cores
[© and source: Xilinx Inc.: Virtex-II Pro™ Platform FPGAs: Functional Description, Sept. 2002, //www.xilinx.com]
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fakultät für informatikinformatik 12
technische universität dortmund
Memory
Peter MarwedelInformatik 12TU Dortmund
Germany
2008/11/15
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- 12 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Memory
For the memory, efficiency is again a concern: speed (latency and throughput); predictable timing energy efficiency size cost other attributes (volatile vs. persistent, etc)
Memories?
Oops! Memories!
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- 13 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Access times and energy consumption increases with the size of the memory
Example (CACTI Model): "Currently, the size of some applications is doubling every 10 months" [STMicroelectronics, Medea+ Workshop, Stuttgart, Nov. 2003]
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- 14 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Access times and energy consumptionfor multi-ported register files
Rixner’s et al. model [HPCA’00], Technology of 0.18 m
Cycle Time (ns) Area (2x106) Power (W)
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
16 32 64 128
Register File Size
0
1
2
3
4
5
6
7
16 32 64 128
GP6M2 GP6M3
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4
6
8
10
12
14
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Register File Size
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- 15 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
How much of the energy consumption of a system is memory-related?
Mobile PCThermal Design (TDP) System Power
Note: Based on Actual Measurements
600/500 MHz uP37%
LCD 10"19%
HDD9%
Memory+Graphics12%
Power Supply10%
Other13%
Mobile PCAverage System Power
600/500 MHz uP13%
LCD 10"30%
HDD19%
Memory+Graphics15%
Power Supply10%
Other13%
CPU Dominates Thermal Design Power
Multiple Platform Components Comprise
Average Power [Courtesy: N. Dutt; Source: V. Tiwari]
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- 16 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Energy consumption in mobile devices
[O. Vargas (Infineon Technologies): Minimum power consumption in mobile-phone memory subsystems; Pennwell Portable Design - September 2005;] Thanks to Thorsten Koch (Nokia/ Univ. Dortmund) for providing this source.
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- 17 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Access-times will be a problem
Speed gap between processing and main DRAM increases
2
4
8
2 4 5
Performance
years
CPU
(1.5
-2 p
.a.)
DRAM (1.07 p.a.)
31
early 60ties (Atlas):page fault ~ 2500 instructions
2002 (2 GHz µP):access to DRAM ~ 500 instructions
penalty for cache miss about same as for page fault in Atlas
Similar problems for PCs and MPSoCs
[P. Machanik: Approaches to Addressing the Memory Wall, TR Nov. 2002, U. Brisbane]
2x every 2 years
10
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- 18 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Hierarchical memoriesusing scratch pad memories (SPM)
Address space
ARM7TDMI cores, well-known for low power consumption
scratch pad memory
0
FFF..
main
SPM
processor
HierarchyHierarchy
ExampleExample
no tag memory
SPM
selectSelection is by an appropriate address decoder (simple!)
SPM is a small, physically separate memory mapped into the address space
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- 19 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Comparison of currents using measurements
E.g.: ATMEL board with ARM7TDMI andext. SRAM
Current32 Bit-Load Instruction (Thumb)
48,2 50,9 44,4 53,1
11677,2 82,2
1,16
0
50
100
150
200
Prog Main/ DataMain
Prog Main/ DataSPM
Prog SPM/ DataMain
Prog SPM/ Data SPM
mA
Core+SPM (mA) Main Memory Current (mA)
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- 20 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Why not just use a cache ? (1)
0
1
2
3
4
5
6
7
8
9
256 512 1024 2048 4096 8192 16384
memory size
En
erg
y p
er
ac
ce
ss
[n
J]
.
Scratch pad
Cache, 2way, 4GB space
Cache, 2way, 16 MB space
Cache, 2way, 1 MB space
[R. Banakar, S. Steinke, B.-S. Lee, 2001]
2. Energy for parallel access of sets, in comparators, muxes.
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- 21 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Influence of the associativity
Parameters different from previous slides
[P. Marwedel et al., ASPDAC, 2004]
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fakultät für informatikinformatik 12
technische universität dortmund
Communication
Peter MarwedelInformatik 12TU Dortmund
Germany
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- 23 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Communication
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- 24 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Communication:Hierarchy
Inverse relation between volume and urgency quite common:
Sensor/actuator busses
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- 25 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Communication- Requirements -
Real-time behavior Efficient, economical
(e.g. centralized power supply) Appropriate bandwidth and communication delay Robustness Fault tolerance Maintainability Diagnosability Security Safety
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- 26 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Basic techniques:Electrical robustness
Single-ended vs. differential signals
Voltage at input of Op-Amp positive '1'; otherwise '0'
Combined with twisted pairs; Most noise added to both wires.
ground
Local groundLocal ground
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- 27 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Evaluation
Advantages: Subtraction removes most of the noise Changes of voltage levels have no effect Reduced importance of ground wiring Higher speed
Disadvantages: Requires negative voltages Increased number of wires and connectors
Applications: USB, FireWire, ISDN Ethernet (STP/UTP CAT 5 cables) differential SCSI High-quality analog audio signals
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- 28 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Real-time behavior
Carrier-sense multiple-access/collision-detection (CSMA/CD, Standard Ethernet) no guaranteed response time.Alternatives:
token rings, token bussesCarrier-sense multiple-access/collision-avoidance
(CSMA/CA)• WLAN techniques with request preceding transmission• Each partner gets an ID (priority). After each bus transfer,
all partners try setting their ID on the bus; partners detecting higher ID disconnect themselves from the bus. Highest priority partner gets guaranteed response time; others only if they are given a chance.
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- 29 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Other basic techniques
Fault tolerance:error detecting and error correcting bus protocols
Privacy:encryption, virtually private networks
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- 30 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Sensor/actuator busses
1. Sensor/actuator busses: Real-time behavior very important; different techniques:
Many wires less wires expensive & flexible
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- 31 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Field busses: Profibus
More powerful/expensive than sensor interfaces; mostly serial. Emphasis on transmission of small number of bytes.Examples:
1.Process Field Bus (Profibus) Designed for factory and process automation.Focus on safety; comprehensive protocol mechanisms.Claiming 20% market share for field busses.Token passing.≦93.75 kbit/s (1200 m);1500 kbits/s (200m);12 Mbit/s (100m)Integration with Ethernet via Profinet.
[http://www.profibus.com/]
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- 32 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Controller area network (CAN)
2. Controller area network (CAN) Designed by Bosch and Intel in 1981; used in cars and other equipment; differential signaling with twisted pairs, arbitration using CSMA/CA, throughput between 10kbit/s and 1 Mbit/s, low and high-priority signals, maximum latency of 134 µs for high priority signals, coding of signals similar to that of serial (RS-232) lines of
PCs, with modifications for differential signaling. See //www.can.bosch.com
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- 33 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Time-Triggered-Protocol (TTP)
3. The Time-Triggered-Protocol (TTP) [Kopetz et al.]for fault-tolerant safety systems like airbags in cars.
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- 34 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
FlexRay
4. FlexRay: developed by the FlexRay consortium(BMW, Ford, Bosch, DaimlerChrysler, …)Combination of a variant of the TTP and the Byteflight [Byteflight Consortium, 2003] protocol.Specified in SDL.
• Improved error tolerance and time-determinism• Meets requirements with transfer rates >> CAN std.
High data rate can be achieved:• initially targeted for ~ 10Mbit/sec;• design allows much higher data rates
• TDMA (Time Division Multiple Access) protocol:Fixed time slot with exclusive access to the bus
• Cycle subdivided into a static and a dynamic segment.
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- 35 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
TDMA in FlexRay
Exclusive bus access enabled for short time in each case.Dynamic segment for transmission of variable length information.Fixed priorities in dynamic segment: Minislots for each potential sender.Bandwidth used only when it is actually needed.
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- 36 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Time intervals in Flexray
show flexray animationfrom dortmund
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Microtick (µt) = Clock period in partners, may differ between partners Macrotick (mt) = Basic unit of time, synchronized between partners
(=riµt, ri varies between partners i) Slot=Interval allocated per sender in static segment (=pmt, p: fixed (configurable)) Minislot = Interval allocated per sender in dynamic segment (=qmt, q: variable)
Short minislot if no transmission needed; starts after previous minislot. Cycle = Static segment + dynamic segment + network idle time
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- 37 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Structure of Flexray networks
Bus guardian protects the system against failing processors, e.g. so-called “babbling idiots”
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- 38 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
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- 39 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Other field busses
LIN MAP:MAP is a bus designed for car factories. EIB:The European Installation Bus (EIB) is a bus
designed for smart homes. European Installation Bus (EIB)Designed for smart buildings; CSMA/CA; low data rate.
IEEE 488: Designed for laboratory equipment. Attempts to use standard Ethernet.
However, timing predictability remains a serious issue.
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- 40 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Wireless communication
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- 41 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Wireless communication: Examples
IEEE 802.11 a/b/g/n UMTS DECT Bluetooth ZigBee
Timing predictability of wireless communication?
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- 42 -technische universitätdortmund
fakultät für informatik
p.marwedel, informatik 12, 2008
Summary
FPGAs
Memories
• “Small is beautiful”(in terms of energy consumption, access times, size)
Communication structures